2 * Freescale Vybrid vf610 ADC driver
4 * Copyright 2013 Freescale Semiconductor, Inc.
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
21 #include <linux/module.h>
22 #include <linux/platform_device.h>
23 #include <linux/interrupt.h>
24 #include <linux/delay.h>
25 #include <linux/kernel.h>
26 #include <linux/slab.h>
28 #include <linux/clk.h>
29 #include <linux/completion.h>
31 #include <linux/of_irq.h>
32 #include <linux/regulator/consumer.h>
33 #include <linux/of_platform.h>
34 #include <linux/err.h>
36 #include <linux/iio/iio.h>
37 #include <linux/iio/buffer.h>
38 #include <linux/iio/sysfs.h>
39 #include <linux/iio/trigger.h>
40 #include <linux/iio/trigger_consumer.h>
41 #include <linux/iio/triggered_buffer.h>
43 /* This will be the driver name the kernel reports */
44 #define DRIVER_NAME "vf610-adc"
46 /* Vybrid/IMX ADC registers */
47 #define VF610_REG_ADC_HC0 0x00
48 #define VF610_REG_ADC_HC1 0x04
49 #define VF610_REG_ADC_HS 0x08
50 #define VF610_REG_ADC_R0 0x0c
51 #define VF610_REG_ADC_R1 0x10
52 #define VF610_REG_ADC_CFG 0x14
53 #define VF610_REG_ADC_GC 0x18
54 #define VF610_REG_ADC_GS 0x1c
55 #define VF610_REG_ADC_CV 0x20
56 #define VF610_REG_ADC_OFS 0x24
57 #define VF610_REG_ADC_CAL 0x28
58 #define VF610_REG_ADC_PCTL 0x30
60 /* Configuration register field define */
61 #define VF610_ADC_MODE_BIT8 0x00
62 #define VF610_ADC_MODE_BIT10 0x04
63 #define VF610_ADC_MODE_BIT12 0x08
64 #define VF610_ADC_MODE_MASK 0x0c
65 #define VF610_ADC_BUSCLK2_SEL 0x01
66 #define VF610_ADC_ALTCLK_SEL 0x02
67 #define VF610_ADC_ADACK_SEL 0x03
68 #define VF610_ADC_ADCCLK_MASK 0x03
69 #define VF610_ADC_CLK_DIV2 0x20
70 #define VF610_ADC_CLK_DIV4 0x40
71 #define VF610_ADC_CLK_DIV8 0x60
72 #define VF610_ADC_CLK_MASK 0x60
73 #define VF610_ADC_ADLSMP_LONG 0x10
74 #define VF610_ADC_ADSTS_SHORT 0x100
75 #define VF610_ADC_ADSTS_NORMAL 0x200
76 #define VF610_ADC_ADSTS_LONG 0x300
77 #define VF610_ADC_ADSTS_MASK 0x300
78 #define VF610_ADC_ADLPC_EN 0x80
79 #define VF610_ADC_ADHSC_EN 0x400
80 #define VF610_ADC_REFSEL_VALT 0x800
81 #define VF610_ADC_REFSEL_VBG 0x1000
82 #define VF610_ADC_ADTRG_HARD 0x2000
83 #define VF610_ADC_AVGS_8 0x4000
84 #define VF610_ADC_AVGS_16 0x8000
85 #define VF610_ADC_AVGS_32 0xC000
86 #define VF610_ADC_AVGS_MASK 0xC000
87 #define VF610_ADC_OVWREN 0x10000
89 /* General control register field define */
90 #define VF610_ADC_ADACKEN 0x1
91 #define VF610_ADC_DMAEN 0x2
92 #define VF610_ADC_ACREN 0x4
93 #define VF610_ADC_ACFGT 0x8
94 #define VF610_ADC_ACFE 0x10
95 #define VF610_ADC_AVGEN 0x20
96 #define VF610_ADC_ADCON 0x40
97 #define VF610_ADC_CAL 0x80
99 /* Other field define */
100 #define VF610_ADC_ADCHC(x) ((x) & 0x1F)
101 #define VF610_ADC_AIEN (0x1 << 7)
102 #define VF610_ADC_CONV_DISABLE 0x1F
103 #define VF610_ADC_HS_COCO0 0x1
104 #define VF610_ADC_CALF 0x2
105 #define VF610_ADC_TIMEOUT msecs_to_jiffies(100)
107 #define DEFAULT_SAMPLE_TIME 1000
109 /* V at 25°C of 696 mV */
110 #define VF610_VTEMP25_3V0 950
111 /* V at 25°C of 699 mV */
112 #define VF610_VTEMP25_3V3 867
113 /* Typical sensor slope coefficient at all temperatures */
114 #define VF610_TEMP_SLOPE_COEFF 1840
117 VF610_ADCIOC_BUSCLK_SET,
118 VF610_ADCIOC_ALTCLK_SET,
119 VF610_ADCIOC_ADACK_SET,
123 VF610_ADCIOC_VR_VREF_SET,
124 VF610_ADCIOC_VR_VALT_SET,
125 VF610_ADCIOC_VR_VBG_SET,
136 enum conversion_mode_sel {
137 VF610_ADC_CONV_NORMAL,
138 VF610_ADC_CONV_HIGH_SPEED,
139 VF610_ADC_CONV_LOW_POWER,
147 VF610_ADCK_CYCLES_13,
148 VF610_ADCK_CYCLES_17,
149 VF610_ADCK_CYCLES_21,
150 VF610_ADCK_CYCLES_25,
153 struct vf610_adc_feature {
154 enum clk_sel clk_sel;
155 enum vol_ref vol_ref;
156 enum conversion_mode_sel conv_mode;
162 u32 default_sample_time;
175 struct regulator *vref;
177 u32 max_adck_rate[3];
178 struct vf610_adc_feature adc_feature;
180 u32 sample_freq_avail[5];
182 struct completion completion;
183 /* Ensure the timestamp is naturally aligned */
186 s64 timestamp __aligned(8);
190 static const u32 vf610_hw_avgs[] = { 1, 4, 8, 16, 32 };
191 static const u32 vf610_lst_adder[] = { 3, 5, 7, 9, 13, 17, 21, 25 };
193 static inline void vf610_adc_calculate_rates(struct vf610_adc *info)
195 struct vf610_adc_feature *adc_feature = &info->adc_feature;
196 unsigned long adck_rate, ipg_rate = clk_get_rate(info->clk);
197 u32 adck_period, lst_addr_min;
200 adck_rate = info->max_adck_rate[adc_feature->conv_mode];
203 /* calculate clk divider which is within specification */
204 divisor = ipg_rate / adck_rate;
205 adc_feature->clk_div = 1 << fls(divisor + 1);
207 /* fall-back value using a safe divisor */
208 adc_feature->clk_div = 8;
211 adck_rate = ipg_rate / adc_feature->clk_div;
214 * Determine the long sample time adder value to be used based
215 * on the default minimum sample time provided.
217 adck_period = NSEC_PER_SEC / adck_rate;
218 lst_addr_min = adc_feature->default_sample_time / adck_period;
219 for (i = 0; i < ARRAY_SIZE(vf610_lst_adder); i++) {
220 if (vf610_lst_adder[i] > lst_addr_min) {
221 adc_feature->lst_adder_index = i;
227 * Calculate ADC sample frequencies
228 * Sample time unit is ADCK cycles. ADCK clk source is ipg clock,
229 * which is the same as bus clock.
231 * ADC conversion time = SFCAdder + AverageNum x (BCT + LSTAdder)
232 * SFCAdder: fixed to 6 ADCK cycles
233 * AverageNum: 1, 4, 8, 16, 32 samples for hardware average.
234 * BCT (Base Conversion Time): fixed to 25 ADCK cycles for 12 bit mode
235 * LSTAdder(Long Sample Time): 3, 5, 7, 9, 13, 17, 21, 25 ADCK cycles
237 for (i = 0; i < ARRAY_SIZE(vf610_hw_avgs); i++)
238 info->sample_freq_avail[i] =
239 adck_rate / (6 + vf610_hw_avgs[i] *
240 (25 + vf610_lst_adder[adc_feature->lst_adder_index]));
243 static inline void vf610_adc_cfg_init(struct vf610_adc *info)
245 struct vf610_adc_feature *adc_feature = &info->adc_feature;
247 /* set default Configuration for ADC controller */
248 adc_feature->clk_sel = VF610_ADCIOC_BUSCLK_SET;
249 adc_feature->vol_ref = VF610_ADCIOC_VR_VREF_SET;
251 adc_feature->calibration = true;
252 adc_feature->ovwren = true;
254 adc_feature->res_mode = 12;
255 adc_feature->sample_rate = 1;
257 adc_feature->conv_mode = VF610_ADC_CONV_LOW_POWER;
259 vf610_adc_calculate_rates(info);
262 static void vf610_adc_cfg_post_set(struct vf610_adc *info)
264 struct vf610_adc_feature *adc_feature = &info->adc_feature;
268 switch (adc_feature->clk_sel) {
269 case VF610_ADCIOC_ALTCLK_SET:
270 cfg_data |= VF610_ADC_ALTCLK_SEL;
272 case VF610_ADCIOC_ADACK_SET:
273 cfg_data |= VF610_ADC_ADACK_SEL;
279 /* low power set for calibration */
280 cfg_data |= VF610_ADC_ADLPC_EN;
282 /* enable high speed for calibration */
283 cfg_data |= VF610_ADC_ADHSC_EN;
285 /* voltage reference */
286 switch (adc_feature->vol_ref) {
287 case VF610_ADCIOC_VR_VREF_SET:
289 case VF610_ADCIOC_VR_VALT_SET:
290 cfg_data |= VF610_ADC_REFSEL_VALT;
292 case VF610_ADCIOC_VR_VBG_SET:
293 cfg_data |= VF610_ADC_REFSEL_VBG;
296 dev_err(info->dev, "error voltage reference\n");
299 /* data overwrite enable */
300 if (adc_feature->ovwren)
301 cfg_data |= VF610_ADC_OVWREN;
303 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
304 writel(gc_data, info->regs + VF610_REG_ADC_GC);
307 static void vf610_adc_calibration(struct vf610_adc *info)
311 if (!info->adc_feature.calibration)
314 /* enable calibration interrupt */
315 hc_cfg = VF610_ADC_AIEN | VF610_ADC_CONV_DISABLE;
316 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
318 adc_gc = readl(info->regs + VF610_REG_ADC_GC);
319 writel(adc_gc | VF610_ADC_CAL, info->regs + VF610_REG_ADC_GC);
321 if (!wait_for_completion_timeout(&info->completion, VF610_ADC_TIMEOUT))
322 dev_err(info->dev, "Timeout for adc calibration\n");
324 adc_gc = readl(info->regs + VF610_REG_ADC_GS);
325 if (adc_gc & VF610_ADC_CALF)
326 dev_err(info->dev, "ADC calibration failed\n");
328 info->adc_feature.calibration = false;
331 static void vf610_adc_cfg_set(struct vf610_adc *info)
333 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
336 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
338 cfg_data &= ~VF610_ADC_ADLPC_EN;
339 if (adc_feature->conv_mode == VF610_ADC_CONV_LOW_POWER)
340 cfg_data |= VF610_ADC_ADLPC_EN;
342 cfg_data &= ~VF610_ADC_ADHSC_EN;
343 if (adc_feature->conv_mode == VF610_ADC_CONV_HIGH_SPEED)
344 cfg_data |= VF610_ADC_ADHSC_EN;
346 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
349 static void vf610_adc_sample_set(struct vf610_adc *info)
351 struct vf610_adc_feature *adc_feature = &(info->adc_feature);
352 int cfg_data, gc_data;
354 cfg_data = readl(info->regs + VF610_REG_ADC_CFG);
355 gc_data = readl(info->regs + VF610_REG_ADC_GC);
357 /* resolution mode */
358 cfg_data &= ~VF610_ADC_MODE_MASK;
359 switch (adc_feature->res_mode) {
361 cfg_data |= VF610_ADC_MODE_BIT8;
364 cfg_data |= VF610_ADC_MODE_BIT10;
367 cfg_data |= VF610_ADC_MODE_BIT12;
370 dev_err(info->dev, "error resolution mode\n");
374 /* clock select and clock divider */
375 cfg_data &= ~(VF610_ADC_CLK_MASK | VF610_ADC_ADCCLK_MASK);
376 switch (adc_feature->clk_div) {
380 cfg_data |= VF610_ADC_CLK_DIV2;
383 cfg_data |= VF610_ADC_CLK_DIV4;
386 cfg_data |= VF610_ADC_CLK_DIV8;
389 switch (adc_feature->clk_sel) {
390 case VF610_ADCIOC_BUSCLK_SET:
391 cfg_data |= VF610_ADC_BUSCLK2_SEL | VF610_ADC_CLK_DIV8;
394 dev_err(info->dev, "error clk divider\n");
401 * Set ADLSMP and ADSTS based on the Long Sample Time Adder value
404 switch (adc_feature->lst_adder_index) {
405 case VF610_ADCK_CYCLES_3:
407 case VF610_ADCK_CYCLES_5:
408 cfg_data |= VF610_ADC_ADSTS_SHORT;
410 case VF610_ADCK_CYCLES_7:
411 cfg_data |= VF610_ADC_ADSTS_NORMAL;
413 case VF610_ADCK_CYCLES_9:
414 cfg_data |= VF610_ADC_ADSTS_LONG;
416 case VF610_ADCK_CYCLES_13:
417 cfg_data |= VF610_ADC_ADLSMP_LONG;
419 case VF610_ADCK_CYCLES_17:
420 cfg_data |= VF610_ADC_ADLSMP_LONG;
421 cfg_data |= VF610_ADC_ADSTS_SHORT;
423 case VF610_ADCK_CYCLES_21:
424 cfg_data |= VF610_ADC_ADLSMP_LONG;
425 cfg_data |= VF610_ADC_ADSTS_NORMAL;
427 case VF610_ADCK_CYCLES_25:
428 cfg_data |= VF610_ADC_ADLSMP_LONG;
429 cfg_data |= VF610_ADC_ADSTS_NORMAL;
432 dev_err(info->dev, "error in sample time select\n");
435 /* update hardware average selection */
436 cfg_data &= ~VF610_ADC_AVGS_MASK;
437 gc_data &= ~VF610_ADC_AVGEN;
438 switch (adc_feature->sample_rate) {
439 case VF610_ADC_SAMPLE_1:
441 case VF610_ADC_SAMPLE_4:
442 gc_data |= VF610_ADC_AVGEN;
444 case VF610_ADC_SAMPLE_8:
445 gc_data |= VF610_ADC_AVGEN;
446 cfg_data |= VF610_ADC_AVGS_8;
448 case VF610_ADC_SAMPLE_16:
449 gc_data |= VF610_ADC_AVGEN;
450 cfg_data |= VF610_ADC_AVGS_16;
452 case VF610_ADC_SAMPLE_32:
453 gc_data |= VF610_ADC_AVGEN;
454 cfg_data |= VF610_ADC_AVGS_32;
458 "error hardware sample average select\n");
461 writel(cfg_data, info->regs + VF610_REG_ADC_CFG);
462 writel(gc_data, info->regs + VF610_REG_ADC_GC);
465 static void vf610_adc_hw_init(struct vf610_adc *info)
467 /* CFG: Feature set */
468 vf610_adc_cfg_post_set(info);
469 vf610_adc_sample_set(info);
471 /* adc calibration */
472 vf610_adc_calibration(info);
474 /* CFG: power and speed set */
475 vf610_adc_cfg_set(info);
478 static int vf610_set_conversion_mode(struct iio_dev *indio_dev,
479 const struct iio_chan_spec *chan,
482 struct vf610_adc *info = iio_priv(indio_dev);
484 mutex_lock(&indio_dev->mlock);
485 info->adc_feature.conv_mode = mode;
486 vf610_adc_calculate_rates(info);
487 vf610_adc_hw_init(info);
488 mutex_unlock(&indio_dev->mlock);
493 static int vf610_get_conversion_mode(struct iio_dev *indio_dev,
494 const struct iio_chan_spec *chan)
496 struct vf610_adc *info = iio_priv(indio_dev);
498 return info->adc_feature.conv_mode;
501 static const char * const vf610_conv_modes[] = { "normal", "high-speed",
504 static const struct iio_enum vf610_conversion_mode = {
505 .items = vf610_conv_modes,
506 .num_items = ARRAY_SIZE(vf610_conv_modes),
507 .get = vf610_get_conversion_mode,
508 .set = vf610_set_conversion_mode,
511 static const struct iio_chan_spec_ext_info vf610_ext_info[] = {
512 IIO_ENUM("conversion_mode", IIO_SHARED_BY_DIR, &vf610_conversion_mode),
516 #define VF610_ADC_CHAN(_idx, _chan_type) { \
517 .type = (_chan_type), \
520 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
521 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
522 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
523 .ext_info = vf610_ext_info, \
524 .scan_index = (_idx), \
532 #define VF610_ADC_TEMPERATURE_CHAN(_idx, _chan_type) { \
533 .type = (_chan_type), \
535 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
536 .scan_index = (_idx), \
544 static const struct iio_chan_spec vf610_adc_iio_channels[] = {
545 VF610_ADC_CHAN(0, IIO_VOLTAGE),
546 VF610_ADC_CHAN(1, IIO_VOLTAGE),
547 VF610_ADC_CHAN(2, IIO_VOLTAGE),
548 VF610_ADC_CHAN(3, IIO_VOLTAGE),
549 VF610_ADC_CHAN(4, IIO_VOLTAGE),
550 VF610_ADC_CHAN(5, IIO_VOLTAGE),
551 VF610_ADC_CHAN(6, IIO_VOLTAGE),
552 VF610_ADC_CHAN(7, IIO_VOLTAGE),
553 VF610_ADC_CHAN(8, IIO_VOLTAGE),
554 VF610_ADC_CHAN(9, IIO_VOLTAGE),
555 VF610_ADC_CHAN(10, IIO_VOLTAGE),
556 VF610_ADC_CHAN(11, IIO_VOLTAGE),
557 VF610_ADC_CHAN(12, IIO_VOLTAGE),
558 VF610_ADC_CHAN(13, IIO_VOLTAGE),
559 VF610_ADC_CHAN(14, IIO_VOLTAGE),
560 VF610_ADC_CHAN(15, IIO_VOLTAGE),
561 VF610_ADC_TEMPERATURE_CHAN(26, IIO_TEMP),
562 IIO_CHAN_SOFT_TIMESTAMP(32),
566 static int vf610_adc_read_data(struct vf610_adc *info)
570 result = readl(info->regs + VF610_REG_ADC_R0);
572 switch (info->adc_feature.res_mode) {
589 static irqreturn_t vf610_adc_isr(int irq, void *dev_id)
591 struct iio_dev *indio_dev = (struct iio_dev *)dev_id;
592 struct vf610_adc *info = iio_priv(indio_dev);
595 coco = readl(info->regs + VF610_REG_ADC_HS);
596 if (coco & VF610_ADC_HS_COCO0) {
597 info->value = vf610_adc_read_data(info);
598 if (iio_buffer_enabled(indio_dev)) {
599 info->scan.chan = info->value;
600 iio_push_to_buffers_with_timestamp(indio_dev,
602 iio_get_time_ns(indio_dev));
603 iio_trigger_notify_done(indio_dev->trig);
605 complete(&info->completion);
611 static ssize_t vf610_show_samp_freq_avail(struct device *dev,
612 struct device_attribute *attr, char *buf)
614 struct vf610_adc *info = iio_priv(dev_to_iio_dev(dev));
618 for (i = 0; i < ARRAY_SIZE(info->sample_freq_avail); i++)
619 len += scnprintf(buf + len, PAGE_SIZE - len,
620 "%u ", info->sample_freq_avail[i]);
622 /* replace trailing space by newline */
628 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(vf610_show_samp_freq_avail);
630 static struct attribute *vf610_attributes[] = {
631 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
635 static const struct attribute_group vf610_attribute_group = {
636 .attrs = vf610_attributes,
639 static int vf610_read_raw(struct iio_dev *indio_dev,
640 struct iio_chan_spec const *chan,
645 struct vf610_adc *info = iio_priv(indio_dev);
650 case IIO_CHAN_INFO_RAW:
651 case IIO_CHAN_INFO_PROCESSED:
652 mutex_lock(&indio_dev->mlock);
653 if (iio_buffer_enabled(indio_dev)) {
654 mutex_unlock(&indio_dev->mlock);
658 reinit_completion(&info->completion);
659 hc_cfg = VF610_ADC_ADCHC(chan->channel);
660 hc_cfg |= VF610_ADC_AIEN;
661 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
662 ret = wait_for_completion_interruptible_timeout
663 (&info->completion, VF610_ADC_TIMEOUT);
665 mutex_unlock(&indio_dev->mlock);
669 mutex_unlock(&indio_dev->mlock);
673 switch (chan->type) {
679 * Calculate in degree Celsius times 1000
680 * Using the typical sensor slope of 1.84 mV/°C
681 * and VREFH_ADC at 3.3V, V at 25°C of 699 mV
683 *val = 25000 - ((int)info->value - VF610_VTEMP25_3V3) *
684 1000000 / VF610_TEMP_SLOPE_COEFF;
688 mutex_unlock(&indio_dev->mlock);
692 mutex_unlock(&indio_dev->mlock);
695 case IIO_CHAN_INFO_SCALE:
696 *val = info->vref_uv / 1000;
697 *val2 = info->adc_feature.res_mode;
698 return IIO_VAL_FRACTIONAL_LOG2;
700 case IIO_CHAN_INFO_SAMP_FREQ:
701 *val = info->sample_freq_avail[info->adc_feature.sample_rate];
712 static int vf610_write_raw(struct iio_dev *indio_dev,
713 struct iio_chan_spec const *chan,
718 struct vf610_adc *info = iio_priv(indio_dev);
722 case IIO_CHAN_INFO_SAMP_FREQ:
724 i < ARRAY_SIZE(info->sample_freq_avail);
726 if (val == info->sample_freq_avail[i]) {
727 info->adc_feature.sample_rate = i;
728 vf610_adc_sample_set(info);
740 static int vf610_adc_buffer_postenable(struct iio_dev *indio_dev)
742 struct vf610_adc *info = iio_priv(indio_dev);
743 unsigned int channel;
747 ret = iio_triggered_buffer_postenable(indio_dev);
751 val = readl(info->regs + VF610_REG_ADC_GC);
752 val |= VF610_ADC_ADCON;
753 writel(val, info->regs + VF610_REG_ADC_GC);
755 channel = find_first_bit(indio_dev->active_scan_mask,
756 indio_dev->masklength);
758 val = VF610_ADC_ADCHC(channel);
759 val |= VF610_ADC_AIEN;
761 writel(val, info->regs + VF610_REG_ADC_HC0);
766 static int vf610_adc_buffer_predisable(struct iio_dev *indio_dev)
768 struct vf610_adc *info = iio_priv(indio_dev);
769 unsigned int hc_cfg = 0;
772 val = readl(info->regs + VF610_REG_ADC_GC);
773 val &= ~VF610_ADC_ADCON;
774 writel(val, info->regs + VF610_REG_ADC_GC);
776 hc_cfg |= VF610_ADC_CONV_DISABLE;
777 hc_cfg &= ~VF610_ADC_AIEN;
779 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
781 return iio_triggered_buffer_predisable(indio_dev);
784 static const struct iio_buffer_setup_ops iio_triggered_buffer_setup_ops = {
785 .postenable = &vf610_adc_buffer_postenable,
786 .predisable = &vf610_adc_buffer_predisable,
787 .validate_scan_mask = &iio_validate_scan_mask_onehot,
790 static int vf610_adc_reg_access(struct iio_dev *indio_dev,
791 unsigned reg, unsigned writeval,
794 struct vf610_adc *info = iio_priv(indio_dev);
796 if ((readval == NULL) ||
797 ((reg % 4) || (reg > VF610_REG_ADC_PCTL)))
800 *readval = readl(info->regs + reg);
805 static const struct iio_info vf610_adc_iio_info = {
806 .driver_module = THIS_MODULE,
807 .read_raw = &vf610_read_raw,
808 .write_raw = &vf610_write_raw,
809 .debugfs_reg_access = &vf610_adc_reg_access,
810 .attrs = &vf610_attribute_group,
813 static const struct of_device_id vf610_adc_match[] = {
814 { .compatible = "fsl,vf610-adc", },
817 MODULE_DEVICE_TABLE(of, vf610_adc_match);
819 static int vf610_adc_probe(struct platform_device *pdev)
821 struct vf610_adc *info;
822 struct iio_dev *indio_dev;
823 struct resource *mem;
827 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct vf610_adc));
829 dev_err(&pdev->dev, "Failed allocating iio device\n");
833 info = iio_priv(indio_dev);
834 info->dev = &pdev->dev;
836 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
837 info->regs = devm_ioremap_resource(&pdev->dev, mem);
838 if (IS_ERR(info->regs))
839 return PTR_ERR(info->regs);
841 irq = platform_get_irq(pdev, 0);
843 dev_err(&pdev->dev, "no irq resource?\n");
847 ret = devm_request_irq(info->dev, irq,
849 dev_name(&pdev->dev), indio_dev);
851 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n", irq);
855 info->clk = devm_clk_get(&pdev->dev, "adc");
856 if (IS_ERR(info->clk)) {
857 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
859 return PTR_ERR(info->clk);
862 info->vref = devm_regulator_get(&pdev->dev, "vref");
863 if (IS_ERR(info->vref))
864 return PTR_ERR(info->vref);
866 ret = regulator_enable(info->vref);
870 info->vref_uv = regulator_get_voltage(info->vref);
872 of_property_read_u32_array(pdev->dev.of_node, "fsl,adck-max-frequency",
873 info->max_adck_rate, 3);
875 ret = of_property_read_u32(pdev->dev.of_node, "min-sample-time",
876 &info->adc_feature.default_sample_time);
878 info->adc_feature.default_sample_time = DEFAULT_SAMPLE_TIME;
880 platform_set_drvdata(pdev, indio_dev);
882 init_completion(&info->completion);
884 indio_dev->name = dev_name(&pdev->dev);
885 indio_dev->dev.parent = &pdev->dev;
886 indio_dev->dev.of_node = pdev->dev.of_node;
887 indio_dev->info = &vf610_adc_iio_info;
888 indio_dev->modes = INDIO_DIRECT_MODE;
889 indio_dev->channels = vf610_adc_iio_channels;
890 indio_dev->num_channels = ARRAY_SIZE(vf610_adc_iio_channels);
892 ret = clk_prepare_enable(info->clk);
895 "Could not prepare or enable the clock.\n");
896 goto error_adc_clk_enable;
899 vf610_adc_cfg_init(info);
900 vf610_adc_hw_init(info);
902 ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
903 NULL, &iio_triggered_buffer_setup_ops);
905 dev_err(&pdev->dev, "Couldn't initialise the buffer\n");
906 goto error_iio_device_register;
909 ret = iio_device_register(indio_dev);
911 dev_err(&pdev->dev, "Couldn't register the device.\n");
912 goto error_adc_buffer_init;
917 error_adc_buffer_init:
918 iio_triggered_buffer_cleanup(indio_dev);
919 error_iio_device_register:
920 clk_disable_unprepare(info->clk);
921 error_adc_clk_enable:
922 regulator_disable(info->vref);
927 static int vf610_adc_remove(struct platform_device *pdev)
929 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
930 struct vf610_adc *info = iio_priv(indio_dev);
932 iio_device_unregister(indio_dev);
933 iio_triggered_buffer_cleanup(indio_dev);
934 regulator_disable(info->vref);
935 clk_disable_unprepare(info->clk);
940 #ifdef CONFIG_PM_SLEEP
941 static int vf610_adc_suspend(struct device *dev)
943 struct iio_dev *indio_dev = dev_get_drvdata(dev);
944 struct vf610_adc *info = iio_priv(indio_dev);
947 /* ADC controller enters to stop mode */
948 hc_cfg = readl(info->regs + VF610_REG_ADC_HC0);
949 hc_cfg |= VF610_ADC_CONV_DISABLE;
950 writel(hc_cfg, info->regs + VF610_REG_ADC_HC0);
952 clk_disable_unprepare(info->clk);
953 regulator_disable(info->vref);
958 static int vf610_adc_resume(struct device *dev)
960 struct iio_dev *indio_dev = dev_get_drvdata(dev);
961 struct vf610_adc *info = iio_priv(indio_dev);
964 ret = regulator_enable(info->vref);
968 ret = clk_prepare_enable(info->clk);
972 vf610_adc_hw_init(info);
977 regulator_disable(info->vref);
982 static SIMPLE_DEV_PM_OPS(vf610_adc_pm_ops, vf610_adc_suspend, vf610_adc_resume);
984 static struct platform_driver vf610_adc_driver = {
985 .probe = vf610_adc_probe,
986 .remove = vf610_adc_remove,
989 .of_match_table = vf610_adc_match,
990 .pm = &vf610_adc_pm_ops,
994 module_platform_driver(vf610_adc_driver);
996 MODULE_AUTHOR("Fugang Duan <B38611@freescale.com>");
997 MODULE_DESCRIPTION("Freescale VF610 ADC driver");
998 MODULE_LICENSE("GPL v2");