drivers/iio/adc/ti-ads1015.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * ADS1015 - Texas Instruments Analog-to-Digital Converter
   4  *
   5  * Copyright (c) 2016, Intel Corporation.
   6  *
   7  * IIO driver for ADS1015 ADC 7-bit I2C slave address:
   8  *      * 0x48 - ADDR connected to Ground
   9  *      * 0x49 - ADDR connected to Vdd
  10  *      * 0x4A - ADDR connected to SDA
  11  *      * 0x4B - ADDR connected to SCL
  12  */
  13
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/irq.h>
  17 #include <linux/i2c.h>
  18 #include <linux/property.h>
  19 #include <linux/regmap.h>
  20 #include <linux/pm_runtime.h>
  21 #include <linux/mutex.h>
  22 #include <linux/delay.h>
  23
  24 #include <linux/iio/iio.h>
  25 #include <linux/iio/types.h>
  26 #include <linux/iio/sysfs.h>
  27 #include <linux/iio/events.h>
  28 #include <linux/iio/buffer.h>
  29 #include <linux/iio/triggered_buffer.h>
  30 #include <linux/iio/trigger_consumer.h>
  31
  32 #define ADS1015_DRV_NAME "ads1015"
  33
  34 #define ADS1015_CHANNELS 8
  35
  36 #define ADS1015_CONV_REG        0x00
  37 #define ADS1015_CFG_REG         0x01
  38 #define ADS1015_LO_THRESH_REG   0x02
  39 #define ADS1015_HI_THRESH_REG   0x03
  40
  41 #define ADS1015_CFG_COMP_QUE_SHIFT      0
  42 #define ADS1015_CFG_COMP_LAT_SHIFT      2
  43 #define ADS1015_CFG_COMP_POL_SHIFT      3
  44 #define ADS1015_CFG_COMP_MODE_SHIFT     4
  45 #define ADS1015_CFG_DR_SHIFT    5
  46 #define ADS1015_CFG_MOD_SHIFT   8
  47 #define ADS1015_CFG_PGA_SHIFT   9
  48 #define ADS1015_CFG_MUX_SHIFT   12
  49
  50 #define ADS1015_CFG_COMP_QUE_MASK       GENMASK(1, 0)
  51 #define ADS1015_CFG_COMP_LAT_MASK       BIT(2)
  52 #define ADS1015_CFG_COMP_POL_MASK       BIT(3)
  53 #define ADS1015_CFG_COMP_MODE_MASK      BIT(4)
  54 #define ADS1015_CFG_DR_MASK     GENMASK(7, 5)
  55 #define ADS1015_CFG_MOD_MASK    BIT(8)
  56 #define ADS1015_CFG_PGA_MASK    GENMASK(11, 9)
  57 #define ADS1015_CFG_MUX_MASK    GENMASK(14, 12)
  58
  59 /* Comparator queue and disable field */
  60 #define ADS1015_CFG_COMP_DISABLE        3
  61
  62 /* Comparator polarity field */
  63 #define ADS1015_CFG_COMP_POL_LOW        0
  64 #define ADS1015_CFG_COMP_POL_HIGH       1
  65
  66 /* Comparator mode field */
  67 #define ADS1015_CFG_COMP_MODE_TRAD      0
  68 #define ADS1015_CFG_COMP_MODE_WINDOW    1
  69
  70 /* device operating modes */
  71 #define ADS1015_CONTINUOUS      0
  72 #define ADS1015_SINGLESHOT      1
  73
  74 #define ADS1015_SLEEP_DELAY_MS          2000
  75 #define ADS1015_DEFAULT_PGA             2
  76 #define ADS1015_DEFAULT_DATA_RATE       4
  77 #define ADS1015_DEFAULT_CHAN            0
  78
  79 enum chip_ids {
  80         ADSXXXX = 0,
  81         ADS1015,
  82         ADS1115,
  83 };
  84
  85 enum ads1015_channels {
  86         ADS1015_AIN0_AIN1 = 0,
  87         ADS1015_AIN0_AIN3,
  88         ADS1015_AIN1_AIN3,
  89         ADS1015_AIN2_AIN3,
  90         ADS1015_AIN0,
  91         ADS1015_AIN1,
  92         ADS1015_AIN2,
  93         ADS1015_AIN3,
  94         ADS1015_TIMESTAMP,
  95 };
  96
  97 static const unsigned int ads1015_data_rate[] = {
  98         128, 250, 490, 920, 1600, 2400, 3300, 3300
  99 };
 100
 101 static const unsigned int ads1115_data_rate[] = {
 102         8, 16, 32, 64, 128, 250, 475, 860
 103 };
 104
 105 /*
 106  * Translation from PGA bits to full-scale positive and negative input voltage
 107  * range in mV
 108  */
 109 static int ads1015_fullscale_range[] = {
 110         6144, 4096, 2048, 1024, 512, 256, 256, 256
 111 };
 112
 113 /*
 114  * Translation from COMP_QUE field value to the number of successive readings
 115  * exceed the threshold values before an interrupt is generated
 116  */
 117 static const int ads1015_comp_queue[] = { 1, 2, 4 };
 118
 119 static const struct iio_event_spec ads1015_events[] = {
 120         {
 121                 .type = IIO_EV_TYPE_THRESH,
 122                 .dir = IIO_EV_DIR_RISING,
 123                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 124                                 BIT(IIO_EV_INFO_ENABLE),
 125         }, {
 126                 .type = IIO_EV_TYPE_THRESH,
 127                 .dir = IIO_EV_DIR_FALLING,
 128                 .mask_separate = BIT(IIO_EV_INFO_VALUE),
 129         }, {
 130                 .type = IIO_EV_TYPE_THRESH,
 131                 .dir = IIO_EV_DIR_EITHER,
 132                 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
 133                                 BIT(IIO_EV_INFO_PERIOD),
 134         },
 135 };
 136
 137 #define ADS1015_V_CHAN(_chan, _addr) {                          \
 138         .type = IIO_VOLTAGE,                                    \
 139         .indexed = 1,                                           \
 140         .address = _addr,                                       \
 141         .channel = _chan,                                       \
 142         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 143                                 BIT(IIO_CHAN_INFO_SCALE) |      \
 144                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 145         .scan_index = _addr,                                    \
 146         .scan_type = {                                          \
 147                 .sign = 's',                                    \
 148                 .realbits = 12,                                 \
 149                 .storagebits = 16,                              \
 150                 .shift = 4,                                     \
 151                 .endianness = IIO_CPU,                          \
 152         },                                                      \
 153         .event_spec = ads1015_events,                           \
 154         .num_event_specs = ARRAY_SIZE(ads1015_events),          \
 155         .datasheet_name = "AIN"#_chan,                          \
 156 }
 157
 158 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) {             \
 159         .type = IIO_VOLTAGE,                                    \
 160         .differential = 1,                                      \
 161         .indexed = 1,                                           \
 162         .address = _addr,                                       \
 163         .channel = _chan,                                       \
 164         .channel2 = _chan2,                                     \
 165         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 166                                 BIT(IIO_CHAN_INFO_SCALE) |      \
 167                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 168         .scan_index = _addr,                                    \
 169         .scan_type = {                                          \
 170                 .sign = 's',                                    \
 171                 .realbits = 12,                                 \
 172                 .storagebits = 16,                              \
 173                 .shift = 4,                                     \
 174                 .endianness = IIO_CPU,                          \
 175         },                                                      \
 176         .event_spec = ads1015_events,                           \
 177         .num_event_specs = ARRAY_SIZE(ads1015_events),          \
 178         .datasheet_name = "AIN"#_chan"-AIN"#_chan2,             \
 179 }
 180
 181 #define ADS1115_V_CHAN(_chan, _addr) {                          \
 182         .type = IIO_VOLTAGE,                                    \
 183         .indexed = 1,                                           \
 184         .address = _addr,                                       \
 185         .channel = _chan,                                       \
 186         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 187                                 BIT(IIO_CHAN_INFO_SCALE) |      \
 188                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 189         .scan_index = _addr,                                    \
 190         .scan_type = {                                          \
 191                 .sign = 's',                                    \
 192                 .realbits = 16,                                 \
 193                 .storagebits = 16,                              \
 194                 .endianness = IIO_CPU,                          \
 195         },                                                      \
 196         .event_spec = ads1015_events,                           \
 197         .num_event_specs = ARRAY_SIZE(ads1015_events),          \
 198         .datasheet_name = "AIN"#_chan,                          \
 199 }
 200
 201 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) {             \
 202         .type = IIO_VOLTAGE,                                    \
 203         .differential = 1,                                      \
 204         .indexed = 1,                                           \
 205         .address = _addr,                                       \
 206         .channel = _chan,                                       \
 207         .channel2 = _chan2,                                     \
 208         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 209                                 BIT(IIO_CHAN_INFO_SCALE) |      \
 210                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),   \
 211         .scan_index = _addr,                                    \
 212         .scan_type = {                                          \
 213                 .sign = 's',                                    \
 214                 .realbits = 16,                                 \
 215                 .storagebits = 16,                              \
 216                 .endianness = IIO_CPU,                          \
 217         },                                                      \
 218         .event_spec = ads1015_events,                           \
 219         .num_event_specs = ARRAY_SIZE(ads1015_events),          \
 220         .datasheet_name = "AIN"#_chan"-AIN"#_chan2,             \
 221 }
 222
 223 struct ads1015_channel_data {
 224         bool enabled;
 225         unsigned int pga;
 226         unsigned int data_rate;
 227 };
 228
 229 struct ads1015_thresh_data {
 230         unsigned int comp_queue;
 231         int high_thresh;
 232         int low_thresh;
 233 };
 234
 235 struct ads1015_data {
 236         struct regmap *regmap;
 237         /*
 238          * Protects ADC ops, e.g: concurrent sysfs/buffered
 239          * data reads, configuration updates
 240          */
 241         struct mutex lock;
 242         struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
 243
 244         unsigned int event_channel;
 245         unsigned int comp_mode;
 246         struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
 247
 248         unsigned int *data_rate;
 249         /*
 250          * Set to true when the ADC is switched to the continuous-conversion
 251          * mode and exits from a power-down state.  This flag is used to avoid
 252          * getting the stale result from the conversion register.
 253          */
 254         bool conv_invalid;
 255 };
 256
 257 static bool ads1015_event_channel_enabled(struct ads1015_data *data)
 258 {
 259         return (data->event_channel != ADS1015_CHANNELS);
 260 }
 261
 262 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
 263                                          int comp_mode)
 264 {
 265         WARN_ON(ads1015_event_channel_enabled(data));
 266
 267         data->event_channel = chan;
 268         data->comp_mode = comp_mode;
 269 }
 270
 271 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
 272 {
 273         data->event_channel = ADS1015_CHANNELS;
 274 }
 275
 276 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
 277 {
 278         switch (reg) {
 279         case ADS1015_CFG_REG:
 280         case ADS1015_LO_THRESH_REG:
 281         case ADS1015_HI_THRESH_REG:
 282                 return true;
 283         default:
 284                 return false;
 285         }
 286 }
 287
 288 static const struct regmap_config ads1015_regmap_config = {
 289         .reg_bits = 8,
 290         .val_bits = 16,
 291         .max_register = ADS1015_HI_THRESH_REG,
 292         .writeable_reg = ads1015_is_writeable_reg,
 293 };
 294
 295 static const struct iio_chan_spec ads1015_channels[] = {
 296         ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
 297         ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
 298         ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
 299         ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
 300         ADS1015_V_CHAN(0, ADS1015_AIN0),
 301         ADS1015_V_CHAN(1, ADS1015_AIN1),
 302         ADS1015_V_CHAN(2, ADS1015_AIN2),
 303         ADS1015_V_CHAN(3, ADS1015_AIN3),
 304         IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
 305 };
 306
 307 static const struct iio_chan_spec ads1115_channels[] = {
 308         ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
 309         ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
 310         ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
 311         ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
 312         ADS1115_V_CHAN(0, ADS1015_AIN0),
 313         ADS1115_V_CHAN(1, ADS1015_AIN1),
 314         ADS1115_V_CHAN(2, ADS1015_AIN2),
 315         ADS1115_V_CHAN(3, ADS1015_AIN3),
 316         IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
 317 };
 318
 319 #ifdef CONFIG_PM
 320 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
 321 {
 322         int ret;
 323         struct device *dev = regmap_get_device(data->regmap);
 324
 325         if (on) {
 326                 ret = pm_runtime_get_sync(dev);
 327                 if (ret < 0)
 328                         pm_runtime_put_noidle(dev);
 329         } else {
 330                 pm_runtime_mark_last_busy(dev);
 331                 ret = pm_runtime_put_autosuspend(dev);
 332         }
 333
 334         return ret < 0 ? ret : 0;
 335 }
 336
 337 #else /* !CONFIG_PM */
 338
 339 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
 340 {
 341         return 0;
 342 }
 343
 344 #endif /* !CONFIG_PM */
 345
 346 static
 347 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
 348 {
 349         int ret, pga, dr, dr_old, conv_time;
 350         unsigned int old, mask, cfg;
 351
 352         if (chan < 0 || chan >= ADS1015_CHANNELS)
 353                 return -EINVAL;
 354
 355         ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
 356         if (ret)
 357                 return ret;
 358
 359         pga = data->channel_data[chan].pga;
 360         dr = data->channel_data[chan].data_rate;
 361         mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
 362                 ADS1015_CFG_DR_MASK;
 363         cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
 364                 dr << ADS1015_CFG_DR_SHIFT;
 365
 366         if (ads1015_event_channel_enabled(data)) {
 367                 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
 368                 cfg |= data->thresh_data[chan].comp_queue <<
 369                                 ADS1015_CFG_COMP_QUE_SHIFT |
 370                         data->comp_mode <<
 371                                 ADS1015_CFG_COMP_MODE_SHIFT;
 372         }
 373
 374         cfg = (old & ~mask) | (cfg & mask);
 375         if (old != cfg) {
 376                 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
 377                 if (ret)
 378                         return ret;
 379                 data->conv_invalid = true;
 380         }
 381         if (data->conv_invalid) {
 382                 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
 383                 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
 384                 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
 385                 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
 386                 usleep_range(conv_time, conv_time + 1);
 387                 data->conv_invalid = false;
 388         }
 389
 390         return regmap_read(data->regmap, ADS1015_CONV_REG, val);
 391 }
 392
 393 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
 394 {
 395         struct iio_poll_func *pf = p;
 396         struct iio_dev *indio_dev = pf->indio_dev;
 397         struct ads1015_data *data = iio_priv(indio_dev);
 398         /* Ensure natural alignment of timestamp */
 399         struct {
 400                 s16 chan;
 401                 s64 timestamp __aligned(8);
 402         } scan;
 403         int chan, ret, res;
 404
 405         memset(&scan, 0, sizeof(scan));
 406
 407         mutex_lock(&data->lock);
 408         chan = find_first_bit(indio_dev->active_scan_mask,
 409                               indio_dev->masklength);
 410         ret = ads1015_get_adc_result(data, chan, &res);
 411         if (ret < 0) {
 412                 mutex_unlock(&data->lock);
 413                 goto err;
 414         }
 415
 416         scan.chan = res;
 417         mutex_unlock(&data->lock);
 418
 419         iio_push_to_buffers_with_timestamp(indio_dev, &scan,
 420                                            iio_get_time_ns(indio_dev));
 421
 422 err:
 423         iio_trigger_notify_done(indio_dev->trig);
 424
 425         return IRQ_HANDLED;
 426 }
 427
 428 static int ads1015_set_scale(struct ads1015_data *data,
 429                              struct iio_chan_spec const *chan,
 430                              int scale, int uscale)
 431 {
 432         int i;
 433         int fullscale = div_s64((scale * 1000000LL + uscale) <<
 434                                 (chan->scan_type.realbits - 1), 1000000);
 435
 436         for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
 437                 if (ads1015_fullscale_range[i] == fullscale) {
 438                         data->channel_data[chan->address].pga = i;
 439                         return 0;
 440                 }
 441         }
 442
 443         return -EINVAL;
 444 }
 445
 446 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
 447 {
 448         int i;
 449
 450         for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
 451                 if (data->data_rate[i] == rate) {
 452                         data->channel_data[chan].data_rate = i;
 453                         return 0;
 454                 }
 455         }
 456
 457         return -EINVAL;
 458 }
 459
 460 static int ads1015_read_raw(struct iio_dev *indio_dev,
 461                             struct iio_chan_spec const *chan, int *val,
 462                             int *val2, long mask)
 463 {
 464         int ret, idx;
 465         struct ads1015_data *data = iio_priv(indio_dev);
 466
 467         mutex_lock(&data->lock);
 468         switch (mask) {
 469         case IIO_CHAN_INFO_RAW: {
 470                 int shift = chan->scan_type.shift;
 471
 472                 ret = iio_device_claim_direct_mode(indio_dev);
 473                 if (ret)
 474                         break;
 475
 476                 if (ads1015_event_channel_enabled(data) &&
 477                                 data->event_channel != chan->address) {
 478                         ret = -EBUSY;
 479                         goto release_direct;
 480                 }
 481
 482                 ret = ads1015_set_power_state(data, true);
 483                 if (ret < 0)
 484                         goto release_direct;
 485
 486                 ret = ads1015_get_adc_result(data, chan->address, val);
 487                 if (ret < 0) {
 488                         ads1015_set_power_state(data, false);
 489                         goto release_direct;
 490                 }
 491
 492                 *val = sign_extend32(*val >> shift, 15 - shift);
 493
 494                 ret = ads1015_set_power_state(data, false);
 495                 if (ret < 0)
 496                         goto release_direct;
 497
 498                 ret = IIO_VAL_INT;
 499 release_direct:
 500                 iio_device_release_direct_mode(indio_dev);
 501                 break;
 502         }
 503         case IIO_CHAN_INFO_SCALE:
 504                 idx = data->channel_data[chan->address].pga;
 505                 *val = ads1015_fullscale_range[idx];
 506                 *val2 = chan->scan_type.realbits - 1;
 507                 ret = IIO_VAL_FRACTIONAL_LOG2;
 508                 break;
 509         case IIO_CHAN_INFO_SAMP_FREQ:
 510                 idx = data->channel_data[chan->address].data_rate;
 511                 *val = data->data_rate[idx];
 512                 ret = IIO_VAL_INT;
 513                 break;
 514         default:
 515                 ret = -EINVAL;
 516                 break;
 517         }
 518         mutex_unlock(&data->lock);
 519
 520         return ret;
 521 }
 522
 523 static int ads1015_write_raw(struct iio_dev *indio_dev,
 524                              struct iio_chan_spec const *chan, int val,
 525                              int val2, long mask)
 526 {
 527         struct ads1015_data *data = iio_priv(indio_dev);
 528         int ret;
 529
 530         mutex_lock(&data->lock);
 531         switch (mask) {
 532         case IIO_CHAN_INFO_SCALE:
 533                 ret = ads1015_set_scale(data, chan, val, val2);
 534                 break;
 535         case IIO_CHAN_INFO_SAMP_FREQ:
 536                 ret = ads1015_set_data_rate(data, chan->address, val);
 537                 break;
 538         default:
 539                 ret = -EINVAL;
 540                 break;
 541         }
 542         mutex_unlock(&data->lock);
 543
 544         return ret;
 545 }
 546
 547 static int ads1015_read_event(struct iio_dev *indio_dev,
 548         const struct iio_chan_spec *chan, enum iio_event_type type,
 549         enum iio_event_direction dir, enum iio_event_info info, int *val,
 550         int *val2)
 551 {
 552         struct ads1015_data *data = iio_priv(indio_dev);
 553         int ret;
 554         unsigned int comp_queue;
 555         int period;
 556         int dr;
 557
 558         mutex_lock(&data->lock);
 559
 560         switch (info) {
 561         case IIO_EV_INFO_VALUE:
 562                 *val = (dir == IIO_EV_DIR_RISING) ?
 563                         data->thresh_data[chan->address].high_thresh :
 564                         data->thresh_data[chan->address].low_thresh;
 565                 ret = IIO_VAL_INT;
 566                 break;
 567         case IIO_EV_INFO_PERIOD:
 568                 dr = data->channel_data[chan->address].data_rate;
 569                 comp_queue = data->thresh_data[chan->address].comp_queue;
 570                 period = ads1015_comp_queue[comp_queue] *
 571                         USEC_PER_SEC / data->data_rate[dr];
 572
 573                 *val = period / USEC_PER_SEC;
 574                 *val2 = period % USEC_PER_SEC;
 575                 ret = IIO_VAL_INT_PLUS_MICRO;
 576                 break;
 577         default:
 578                 ret = -EINVAL;
 579                 break;
 580         }
 581
 582         mutex_unlock(&data->lock);
 583
 584         return ret;
 585 }
 586
 587 static int ads1015_write_event(struct iio_dev *indio_dev,
 588         const struct iio_chan_spec *chan, enum iio_event_type type,
 589         enum iio_event_direction dir, enum iio_event_info info, int val,
 590         int val2)
 591 {
 592         struct ads1015_data *data = iio_priv(indio_dev);
 593         int realbits = chan->scan_type.realbits;
 594         int ret = 0;
 595         long long period;
 596         int i;
 597         int dr;
 598
 599         mutex_lock(&data->lock);
 600
 601         switch (info) {
 602         case IIO_EV_INFO_VALUE:
 603                 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
 604                         ret = -EINVAL;
 605                         break;
 606                 }
 607                 if (dir == IIO_EV_DIR_RISING)
 608                         data->thresh_data[chan->address].high_thresh = val;
 609                 else
 610                         data->thresh_data[chan->address].low_thresh = val;
 611                 break;
 612         case IIO_EV_INFO_PERIOD:
 613                 dr = data->channel_data[chan->address].data_rate;
 614                 period = val * USEC_PER_SEC + val2;
 615
 616                 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
 617                         if (period <= ads1015_comp_queue[i] *
 618                                         USEC_PER_SEC / data->data_rate[dr])
 619                                 break;
 620                 }
 621                 data->thresh_data[chan->address].comp_queue = i;
 622                 break;
 623         default:
 624                 ret = -EINVAL;
 625                 break;
 626         }
 627
 628         mutex_unlock(&data->lock);
 629
 630         return ret;
 631 }
 632
 633 static int ads1015_read_event_config(struct iio_dev *indio_dev,
 634         const struct iio_chan_spec *chan, enum iio_event_type type,
 635         enum iio_event_direction dir)
 636 {
 637         struct ads1015_data *data = iio_priv(indio_dev);
 638         int ret = 0;
 639
 640         mutex_lock(&data->lock);
 641         if (data->event_channel == chan->address) {
 642                 switch (dir) {
 643                 case IIO_EV_DIR_RISING:
 644                         ret = 1;
 645                         break;
 646                 case IIO_EV_DIR_EITHER:
 647                         ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
 648                         break;
 649                 default:
 650                         ret = -EINVAL;
 651                         break;
 652                 }
 653         }
 654         mutex_unlock(&data->lock);
 655
 656         return ret;
 657 }
 658
 659 static int ads1015_enable_event_config(struct ads1015_data *data,
 660         const struct iio_chan_spec *chan, int comp_mode)
 661 {
 662         int low_thresh = data->thresh_data[chan->address].low_thresh;
 663         int high_thresh = data->thresh_data[chan->address].high_thresh;
 664         int ret;
 665         unsigned int val;
 666
 667         if (ads1015_event_channel_enabled(data)) {
 668                 if (data->event_channel != chan->address ||
 669                         (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
 670                                 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
 671                         return -EBUSY;
 672
 673                 return 0;
 674         }
 675
 676         if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
 677                 low_thresh = max(-1 << (chan->scan_type.realbits - 1),
 678                                 high_thresh - 1);
 679         }
 680         ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
 681                         low_thresh << chan->scan_type.shift);
 682         if (ret)
 683                 return ret;
 684
 685         ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
 686                         high_thresh << chan->scan_type.shift);
 687         if (ret)
 688                 return ret;
 689
 690         ret = ads1015_set_power_state(data, true);
 691         if (ret < 0)
 692                 return ret;
 693
 694         ads1015_event_channel_enable(data, chan->address, comp_mode);
 695
 696         ret = ads1015_get_adc_result(data, chan->address, &val);
 697         if (ret) {
 698                 ads1015_event_channel_disable(data, chan->address);
 699                 ads1015_set_power_state(data, false);
 700         }
 701
 702         return ret;
 703 }
 704
 705 static int ads1015_disable_event_config(struct ads1015_data *data,
 706         const struct iio_chan_spec *chan, int comp_mode)
 707 {
 708         int ret;
 709
 710         if (!ads1015_event_channel_enabled(data))
 711                 return 0;
 712
 713         if (data->event_channel != chan->address)
 714                 return 0;
 715
 716         if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
 717                         comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
 718                 return 0;
 719
 720         ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
 721                                 ADS1015_CFG_COMP_QUE_MASK,
 722                                 ADS1015_CFG_COMP_DISABLE <<
 723                                         ADS1015_CFG_COMP_QUE_SHIFT);
 724         if (ret)
 725                 return ret;
 726
 727         ads1015_event_channel_disable(data, chan->address);
 728
 729         return ads1015_set_power_state(data, false);
 730 }
 731
 732 static int ads1015_write_event_config(struct iio_dev *indio_dev,
 733         const struct iio_chan_spec *chan, enum iio_event_type type,
 734         enum iio_event_direction dir, int state)
 735 {
 736         struct ads1015_data *data = iio_priv(indio_dev);
 737         int ret;
 738         int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
 739                 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
 740
 741         mutex_lock(&data->lock);
 742
 743         /* Prevent from enabling both buffer and event at a time */
 744         ret = iio_device_claim_direct_mode(indio_dev);
 745         if (ret) {
 746                 mutex_unlock(&data->lock);
 747                 return ret;
 748         }
 749
 750         if (state)
 751                 ret = ads1015_enable_event_config(data, chan, comp_mode);
 752         else
 753                 ret = ads1015_disable_event_config(data, chan, comp_mode);
 754
 755         iio_device_release_direct_mode(indio_dev);
 756         mutex_unlock(&data->lock);
 757
 758         return ret;
 759 }
 760
 761 static irqreturn_t ads1015_event_handler(int irq, void *priv)
 762 {
 763         struct iio_dev *indio_dev = priv;
 764         struct ads1015_data *data = iio_priv(indio_dev);
 765         int val;
 766         int ret;
 767
 768         /* Clear the latched ALERT/RDY pin */
 769         ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
 770         if (ret)
 771                 return IRQ_HANDLED;
 772
 773         if (ads1015_event_channel_enabled(data)) {
 774                 enum iio_event_direction dir;
 775                 u64 code;
 776
 777                 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
 778                                         IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
 779                 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
 780                                         IIO_EV_TYPE_THRESH, dir);
 781                 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
 782         }
 783
 784         return IRQ_HANDLED;
 785 }
 786
 787 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
 788 {
 789         struct ads1015_data *data = iio_priv(indio_dev);
 790
 791         /* Prevent from enabling both buffer and event at a time */
 792         if (ads1015_event_channel_enabled(data))
 793                 return -EBUSY;
 794
 795         return ads1015_set_power_state(iio_priv(indio_dev), true);
 796 }
 797
 798 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
 799 {
 800         return ads1015_set_power_state(iio_priv(indio_dev), false);
 801 }
 802
 803 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
 804         .preenable      = ads1015_buffer_preenable,
 805         .postdisable    = ads1015_buffer_postdisable,
 806         .validate_scan_mask = &iio_validate_scan_mask_onehot,
 807 };
 808
 809 static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
 810         "3 2 1 0.5 0.25 0.125");
 811 static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
 812         "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
 813
 814 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
 815         sampling_frequency_available, "128 250 490 920 1600 2400 3300");
 816 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
 817         sampling_frequency_available, "8 16 32 64 128 250 475 860");
 818
 819 static struct attribute *ads1015_attributes[] = {
 820         &iio_const_attr_ads1015_scale_available.dev_attr.attr,
 821         &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
 822         NULL,
 823 };
 824
 825 static const struct attribute_group ads1015_attribute_group = {
 826         .attrs = ads1015_attributes,
 827 };
 828
 829 static struct attribute *ads1115_attributes[] = {
 830         &iio_const_attr_ads1115_scale_available.dev_attr.attr,
 831         &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
 832         NULL,
 833 };
 834
 835 static const struct attribute_group ads1115_attribute_group = {
 836         .attrs = ads1115_attributes,
 837 };
 838
 839 static const struct iio_info ads1015_info = {
 840         .read_raw       = ads1015_read_raw,
 841         .write_raw      = ads1015_write_raw,
 842         .read_event_value = ads1015_read_event,
 843         .write_event_value = ads1015_write_event,
 844         .read_event_config = ads1015_read_event_config,
 845         .write_event_config = ads1015_write_event_config,
 846         .attrs          = &ads1015_attribute_group,
 847 };
 848
 849 static const struct iio_info ads1115_info = {
 850         .read_raw       = ads1015_read_raw,
 851         .write_raw      = ads1015_write_raw,
 852         .read_event_value = ads1015_read_event,
 853         .write_event_value = ads1015_write_event,
 854         .read_event_config = ads1015_read_event_config,
 855         .write_event_config = ads1015_write_event_config,
 856         .attrs          = &ads1115_attribute_group,
 857 };
 858
 859 static int ads1015_client_get_channels_config(struct i2c_client *client)
 860 {
 861         struct iio_dev *indio_dev = i2c_get_clientdata(client);
 862         struct ads1015_data *data = iio_priv(indio_dev);
 863         struct device *dev = &client->dev;
 864         struct fwnode_handle *node;
 865         int i = -1;
 866
 867         device_for_each_child_node(dev, node) {
 868                 u32 pval;
 869                 unsigned int channel;
 870                 unsigned int pga = ADS1015_DEFAULT_PGA;
 871                 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
 872
 873                 if (fwnode_property_read_u32(node, "reg", &pval)) {
 874                         dev_err(dev, "invalid reg on %pfw\n", node);
 875                         continue;
 876                 }
 877
 878                 channel = pval;
 879                 if (channel >= ADS1015_CHANNELS) {
 880                         dev_err(dev, "invalid channel index %d on %pfw\n",
 881                                 channel, node);
 882                         continue;
 883                 }
 884
 885                 if (!fwnode_property_read_u32(node, "ti,gain", &pval)) {
 886                         pga = pval;
 887                         if (pga > 6) {
 888                                 dev_err(dev, "invalid gain on %pfw\n", node);
 889                                 fwnode_handle_put(node);
 890                                 return -EINVAL;
 891                         }
 892                 }
 893
 894                 if (!fwnode_property_read_u32(node, "ti,datarate", &pval)) {
 895                         data_rate = pval;
 896                         if (data_rate > 7) {
 897                                 dev_err(dev, "invalid data_rate on %pfw\n", node);
 898                                 fwnode_handle_put(node);
 899                                 return -EINVAL;
 900                         }
 901                 }
 902
 903                 data->channel_data[channel].pga = pga;
 904                 data->channel_data[channel].data_rate = data_rate;
 905
 906                 i++;
 907         }
 908
 909         return i < 0 ? -EINVAL : 0;
 910 }
 911
 912 static void ads1015_get_channels_config(struct i2c_client *client)
 913 {
 914         unsigned int k;
 915
 916         struct iio_dev *indio_dev = i2c_get_clientdata(client);
 917         struct ads1015_data *data = iio_priv(indio_dev);
 918
 919         if (!ads1015_client_get_channels_config(client))
 920                 return;
 921
 922         /* fallback on default configuration */
 923         for (k = 0; k < ADS1015_CHANNELS; ++k) {
 924                 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
 925                 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
 926         }
 927 }
 928
 929 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
 930 {
 931         return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
 932                                   ADS1015_CFG_MOD_MASK,
 933                                   mode << ADS1015_CFG_MOD_SHIFT);
 934 }
 935
 936 static int ads1015_probe(struct i2c_client *client,
 937                          const struct i2c_device_id *id)
 938 {
 939         struct iio_dev *indio_dev;
 940         struct ads1015_data *data;
 941         int ret;
 942         enum chip_ids chip;
 943         int i;
 944
 945         indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
 946         if (!indio_dev)
 947                 return -ENOMEM;
 948
 949         data = iio_priv(indio_dev);
 950         i2c_set_clientdata(client, indio_dev);
 951
 952         mutex_init(&data->lock);
 953
 954         indio_dev->name = ADS1015_DRV_NAME;
 955         indio_dev->modes = INDIO_DIRECT_MODE;
 956
 957         chip = (enum chip_ids)device_get_match_data(&client->dev);
 958         if (chip == ADSXXXX)
 959                 chip = id->driver_data;
 960         switch (chip) {
 961         case ADS1015:
 962                 indio_dev->channels = ads1015_channels;
 963                 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
 964                 indio_dev->info = &ads1015_info;
 965                 data->data_rate = (unsigned int *) &ads1015_data_rate;
 966                 break;
 967         case ADS1115:
 968                 indio_dev->channels = ads1115_channels;
 969                 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
 970                 indio_dev->info = &ads1115_info;
 971                 data->data_rate = (unsigned int *) &ads1115_data_rate;
 972                 break;
 973         default:
 974                 dev_err(&client->dev, "Unknown chip %d\n", chip);
 975                 return -EINVAL;
 976         }
 977
 978         data->event_channel = ADS1015_CHANNELS;
 979         /*
 980          * Set default lower and upper threshold to min and max value
 981          * respectively.
 982          */
 983         for (i = 0; i < ADS1015_CHANNELS; i++) {
 984                 int realbits = indio_dev->channels[i].scan_type.realbits;
 985
 986                 data->thresh_data[i].low_thresh = -1 << (realbits - 1);
 987                 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
 988         }
 989
 990         /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
 991         ads1015_get_channels_config(client);
 992
 993         data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
 994         if (IS_ERR(data->regmap)) {
 995                 dev_err(&client->dev, "Failed to allocate register map\n");
 996                 return PTR_ERR(data->regmap);
 997         }
 998
 999         ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1000                                               ads1015_trigger_handler,
1001                                               &ads1015_buffer_setup_ops);
1002         if (ret < 0) {
1003                 dev_err(&client->dev, "iio triggered buffer setup failed\n");
1004                 return ret;
1005         }
1006
1007         if (client->irq) {
1008                 unsigned long irq_trig =
1009                         irqd_get_trigger_type(irq_get_irq_data(client->irq));
1010                 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
1011                         ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
1012                 unsigned int cfg_comp =
1013                         ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1014                         1 << ADS1015_CFG_COMP_LAT_SHIFT;
1015
1016                 switch (irq_trig) {
1017                 case IRQF_TRIGGER_LOW:
1018                         cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1019                                         ADS1015_CFG_COMP_POL_SHIFT;
1020                         break;
1021                 case IRQF_TRIGGER_HIGH:
1022                         cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1023                                         ADS1015_CFG_COMP_POL_SHIFT;
1024                         break;
1025                 default:
1026                         return -EINVAL;
1027                 }
1028
1029                 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1030                                         cfg_comp_mask, cfg_comp);
1031                 if (ret)
1032                         return ret;
1033
1034                 ret = devm_request_threaded_irq(&client->dev, client->irq,
1035                                                 NULL, ads1015_event_handler,
1036                                                 irq_trig | IRQF_ONESHOT,
1037                                                 client->name, indio_dev);
1038                 if (ret)
1039                         return ret;
1040         }
1041
1042         ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1043         if (ret)
1044                 return ret;
1045
1046         data->conv_invalid = true;
1047
1048         ret = pm_runtime_set_active(&client->dev);
1049         if (ret)
1050                 return ret;
1051         pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1052         pm_runtime_use_autosuspend(&client->dev);
1053         pm_runtime_enable(&client->dev);
1054
1055         ret = iio_device_register(indio_dev);
1056         if (ret < 0) {
1057                 dev_err(&client->dev, "Failed to register IIO device\n");
1058                 return ret;
1059         }
1060
1061         return 0;
1062 }
1063
1064 static int ads1015_remove(struct i2c_client *client)
1065 {
1066         struct iio_dev *indio_dev = i2c_get_clientdata(client);
1067         struct ads1015_data *data = iio_priv(indio_dev);
1068
1069         iio_device_unregister(indio_dev);
1070
1071         pm_runtime_disable(&client->dev);
1072         pm_runtime_set_suspended(&client->dev);
1073         pm_runtime_put_noidle(&client->dev);
1074
1075         /* power down single shot mode */
1076         return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1077 }
1078
1079 #ifdef CONFIG_PM
1080 static int ads1015_runtime_suspend(struct device *dev)
1081 {
1082         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1083         struct ads1015_data *data = iio_priv(indio_dev);
1084
1085         return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1086 }
1087
1088 static int ads1015_runtime_resume(struct device *dev)
1089 {
1090         struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1091         struct ads1015_data *data = iio_priv(indio_dev);
1092         int ret;
1093
1094         ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1095         if (!ret)
1096                 data->conv_invalid = true;
1097
1098         return ret;
1099 }
1100 #endif
1101
1102 static const struct dev_pm_ops ads1015_pm_ops = {
1103         SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1104                            ads1015_runtime_resume, NULL)
1105 };
1106
1107 static const struct i2c_device_id ads1015_id[] = {
1108         {"ads1015", ADS1015},
1109         {"ads1115", ADS1115},
1110         {}
1111 };
1112 MODULE_DEVICE_TABLE(i2c, ads1015_id);
1113
1114 static const struct of_device_id ads1015_of_match[] = {
1115         {
1116                 .compatible = "ti,ads1015",
1117                 .data = (void *)ADS1015
1118         },
1119         {
1120                 .compatible = "ti,ads1115",
1121                 .data = (void *)ADS1115
1122         },
1123         {}
1124 };
1125 MODULE_DEVICE_TABLE(of, ads1015_of_match);
1126
1127 static struct i2c_driver ads1015_driver = {
1128         .driver = {
1129                 .name = ADS1015_DRV_NAME,
1130                 .of_match_table = ads1015_of_match,
1131                 .pm = &ads1015_pm_ops,
1132         },
1133         .probe          = ads1015_probe,
1134         .remove         = ads1015_remove,
1135         .id_table       = ads1015_id,
1136 };
1137
1138 module_i2c_driver(ads1015_driver);
1139
1140 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1141 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1142 MODULE_LICENSE("GPL v2");