2 * ADS1015 - Texas Instruments Analog-to-Digital Converter
4 * Copyright (c) 2016, Intel Corporation.
6 * This file is subject to the terms and conditions of version 2 of
7 * the GNU General Public License. See the file COPYING in the main
8 * directory of this archive for more details.
10 * IIO driver for ADS1015 ADC 7-bit I2C slave address:
11 * * 0x48 - ADDR connected to Ground
12 * * 0x49 - ADDR connected to Vdd
13 * * 0x4A - ADDR connected to SDA
14 * * 0x4B - ADDR connected to SCL
17 #include <linux/module.h>
18 #include <linux/of_device.h>
19 #include <linux/init.h>
20 #include <linux/irq.h>
21 #include <linux/i2c.h>
22 #include <linux/regmap.h>
23 #include <linux/pm_runtime.h>
24 #include <linux/mutex.h>
25 #include <linux/delay.h>
27 #include <linux/platform_data/ads1015.h>
29 #include <linux/iio/iio.h>
30 #include <linux/iio/types.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/events.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/triggered_buffer.h>
35 #include <linux/iio/trigger_consumer.h>
37 #define ADS1015_DRV_NAME "ads1015"
39 #define ADS1015_CONV_REG 0x00
40 #define ADS1015_CFG_REG 0x01
41 #define ADS1015_LO_THRESH_REG 0x02
42 #define ADS1015_HI_THRESH_REG 0x03
44 #define ADS1015_CFG_COMP_QUE_SHIFT 0
45 #define ADS1015_CFG_COMP_LAT_SHIFT 2
46 #define ADS1015_CFG_COMP_POL_SHIFT 3
47 #define ADS1015_CFG_COMP_MODE_SHIFT 4
48 #define ADS1015_CFG_DR_SHIFT 5
49 #define ADS1015_CFG_MOD_SHIFT 8
50 #define ADS1015_CFG_PGA_SHIFT 9
51 #define ADS1015_CFG_MUX_SHIFT 12
53 #define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
54 #define ADS1015_CFG_COMP_LAT_MASK BIT(2)
55 #define ADS1015_CFG_COMP_POL_MASK BIT(3)
56 #define ADS1015_CFG_COMP_MODE_MASK BIT(4)
57 #define ADS1015_CFG_DR_MASK GENMASK(7, 5)
58 #define ADS1015_CFG_MOD_MASK BIT(8)
59 #define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
60 #define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
62 /* Comparator queue and disable field */
63 #define ADS1015_CFG_COMP_DISABLE 3
65 /* Comparator polarity field */
66 #define ADS1015_CFG_COMP_POL_LOW 0
67 #define ADS1015_CFG_COMP_POL_HIGH 1
69 /* Comparator mode field */
70 #define ADS1015_CFG_COMP_MODE_TRAD 0
71 #define ADS1015_CFG_COMP_MODE_WINDOW 1
73 /* device operating modes */
74 #define ADS1015_CONTINUOUS 0
75 #define ADS1015_SINGLESHOT 1
77 #define ADS1015_SLEEP_DELAY_MS 2000
78 #define ADS1015_DEFAULT_PGA 2
79 #define ADS1015_DEFAULT_DATA_RATE 4
80 #define ADS1015_DEFAULT_CHAN 0
87 enum ads1015_channels {
88 ADS1015_AIN0_AIN1 = 0,
99 static const unsigned int ads1015_data_rate[] = {
100 128, 250, 490, 920, 1600, 2400, 3300, 3300
103 static const unsigned int ads1115_data_rate[] = {
104 8, 16, 32, 64, 128, 250, 475, 860
108 * Translation from PGA bits to full-scale positive and negative input voltage
111 static int ads1015_fullscale_range[] = {
112 6144, 4096, 2048, 1024, 512, 256, 256, 256
116 * Translation from COMP_QUE field value to the number of successive readings
117 * exceed the threshold values before an interrupt is generated
119 static const int ads1015_comp_queue[] = { 1, 2, 4 };
121 static const struct iio_event_spec ads1015_events[] = {
123 .type = IIO_EV_TYPE_THRESH,
124 .dir = IIO_EV_DIR_RISING,
125 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
126 BIT(IIO_EV_INFO_ENABLE),
128 .type = IIO_EV_TYPE_THRESH,
129 .dir = IIO_EV_DIR_FALLING,
130 .mask_separate = BIT(IIO_EV_INFO_VALUE),
132 .type = IIO_EV_TYPE_THRESH,
133 .dir = IIO_EV_DIR_EITHER,
134 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
135 BIT(IIO_EV_INFO_PERIOD),
139 #define ADS1015_V_CHAN(_chan, _addr) { \
140 .type = IIO_VOLTAGE, \
144 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
145 BIT(IIO_CHAN_INFO_SCALE) | \
146 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
147 .scan_index = _addr, \
153 .endianness = IIO_CPU, \
155 .event_spec = ads1015_events, \
156 .num_event_specs = ARRAY_SIZE(ads1015_events), \
157 .datasheet_name = "AIN"#_chan, \
160 #define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
161 .type = IIO_VOLTAGE, \
166 .channel2 = _chan2, \
167 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
168 BIT(IIO_CHAN_INFO_SCALE) | \
169 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
170 .scan_index = _addr, \
176 .endianness = IIO_CPU, \
178 .event_spec = ads1015_events, \
179 .num_event_specs = ARRAY_SIZE(ads1015_events), \
180 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
183 #define ADS1115_V_CHAN(_chan, _addr) { \
184 .type = IIO_VOLTAGE, \
188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
189 BIT(IIO_CHAN_INFO_SCALE) | \
190 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
191 .scan_index = _addr, \
196 .endianness = IIO_CPU, \
198 .event_spec = ads1015_events, \
199 .num_event_specs = ARRAY_SIZE(ads1015_events), \
200 .datasheet_name = "AIN"#_chan, \
203 #define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
204 .type = IIO_VOLTAGE, \
209 .channel2 = _chan2, \
210 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
211 BIT(IIO_CHAN_INFO_SCALE) | \
212 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
213 .scan_index = _addr, \
218 .endianness = IIO_CPU, \
220 .event_spec = ads1015_events, \
221 .num_event_specs = ARRAY_SIZE(ads1015_events), \
222 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
225 struct ads1015_thresh_data {
226 unsigned int comp_queue;
231 struct ads1015_data {
232 struct regmap *regmap;
234 * Protects ADC ops, e.g: concurrent sysfs/buffered
235 * data reads, configuration updates
238 struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
240 unsigned int event_channel;
241 unsigned int comp_mode;
242 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
244 unsigned int *data_rate;
246 * Set to true when the ADC is switched to the continuous-conversion
247 * mode and exits from a power-down state. This flag is used to avoid
248 * getting the stale result from the conversion register.
253 static bool ads1015_event_channel_enabled(struct ads1015_data *data)
255 return (data->event_channel != ADS1015_CHANNELS);
258 static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
261 WARN_ON(ads1015_event_channel_enabled(data));
263 data->event_channel = chan;
264 data->comp_mode = comp_mode;
267 static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
269 data->event_channel = ADS1015_CHANNELS;
272 static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
275 case ADS1015_CFG_REG:
276 case ADS1015_LO_THRESH_REG:
277 case ADS1015_HI_THRESH_REG:
284 static const struct regmap_config ads1015_regmap_config = {
287 .max_register = ADS1015_HI_THRESH_REG,
288 .writeable_reg = ads1015_is_writeable_reg,
291 static const struct iio_chan_spec ads1015_channels[] = {
292 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
293 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
294 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
295 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
296 ADS1015_V_CHAN(0, ADS1015_AIN0),
297 ADS1015_V_CHAN(1, ADS1015_AIN1),
298 ADS1015_V_CHAN(2, ADS1015_AIN2),
299 ADS1015_V_CHAN(3, ADS1015_AIN3),
300 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
303 static const struct iio_chan_spec ads1115_channels[] = {
304 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
305 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
306 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
307 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
308 ADS1115_V_CHAN(0, ADS1015_AIN0),
309 ADS1115_V_CHAN(1, ADS1015_AIN1),
310 ADS1115_V_CHAN(2, ADS1015_AIN2),
311 ADS1115_V_CHAN(3, ADS1015_AIN3),
312 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
316 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
319 struct device *dev = regmap_get_device(data->regmap);
322 ret = pm_runtime_get_sync(dev);
324 pm_runtime_put_noidle(dev);
326 pm_runtime_mark_last_busy(dev);
327 ret = pm_runtime_put_autosuspend(dev);
330 return ret < 0 ? ret : 0;
333 #else /* !CONFIG_PM */
335 static int ads1015_set_power_state(struct ads1015_data *data, bool on)
340 #endif /* !CONFIG_PM */
343 int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
345 int ret, pga, dr, conv_time;
346 unsigned int old, mask, cfg;
348 if (chan < 0 || chan >= ADS1015_CHANNELS)
351 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
355 pga = data->channel_data[chan].pga;
356 dr = data->channel_data[chan].data_rate;
357 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
359 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
360 dr << ADS1015_CFG_DR_SHIFT;
362 if (ads1015_event_channel_enabled(data)) {
363 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
364 cfg |= data->thresh_data[chan].comp_queue <<
365 ADS1015_CFG_COMP_QUE_SHIFT |
367 ADS1015_CFG_COMP_MODE_SHIFT;
370 cfg = (old & ~mask) | (cfg & mask);
372 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
376 if (old != cfg || data->conv_invalid) {
377 int dr_old = (old & ADS1015_CFG_DR_MASK) >>
378 ADS1015_CFG_DR_SHIFT;
380 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
381 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
382 conv_time += conv_time / 10; /* 10% internal clock inaccuracy */
383 usleep_range(conv_time, conv_time + 1);
384 data->conv_invalid = false;
387 return regmap_read(data->regmap, ADS1015_CONV_REG, val);
390 static irqreturn_t ads1015_trigger_handler(int irq, void *p)
392 struct iio_poll_func *pf = p;
393 struct iio_dev *indio_dev = pf->indio_dev;
394 struct ads1015_data *data = iio_priv(indio_dev);
395 /* Ensure natural alignment of timestamp */
398 s64 timestamp __aligned(8);
402 memset(&scan, 0, sizeof(scan));
404 mutex_lock(&data->lock);
405 chan = find_first_bit(indio_dev->active_scan_mask,
406 indio_dev->masklength);
407 ret = ads1015_get_adc_result(data, chan, &res);
409 mutex_unlock(&data->lock);
414 mutex_unlock(&data->lock);
416 iio_push_to_buffers_with_timestamp(indio_dev, &scan,
417 iio_get_time_ns(indio_dev));
420 iio_trigger_notify_done(indio_dev->trig);
425 static int ads1015_set_scale(struct ads1015_data *data,
426 struct iio_chan_spec const *chan,
427 int scale, int uscale)
430 int fullscale = div_s64((scale * 1000000LL + uscale) <<
431 (chan->scan_type.realbits - 1), 1000000);
433 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
434 if (ads1015_fullscale_range[i] == fullscale) {
435 data->channel_data[chan->address].pga = i;
443 static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
447 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
448 if (data->data_rate[i] == rate) {
449 data->channel_data[chan].data_rate = i;
457 static int ads1015_read_raw(struct iio_dev *indio_dev,
458 struct iio_chan_spec const *chan, int *val,
459 int *val2, long mask)
462 struct ads1015_data *data = iio_priv(indio_dev);
464 mutex_lock(&data->lock);
466 case IIO_CHAN_INFO_RAW: {
467 int shift = chan->scan_type.shift;
469 ret = iio_device_claim_direct_mode(indio_dev);
473 if (ads1015_event_channel_enabled(data) &&
474 data->event_channel != chan->address) {
479 ret = ads1015_set_power_state(data, true);
483 ret = ads1015_get_adc_result(data, chan->address, val);
485 ads1015_set_power_state(data, false);
489 *val = sign_extend32(*val >> shift, 15 - shift);
491 ret = ads1015_set_power_state(data, false);
497 iio_device_release_direct_mode(indio_dev);
500 case IIO_CHAN_INFO_SCALE:
501 idx = data->channel_data[chan->address].pga;
502 *val = ads1015_fullscale_range[idx];
503 *val2 = chan->scan_type.realbits - 1;
504 ret = IIO_VAL_FRACTIONAL_LOG2;
506 case IIO_CHAN_INFO_SAMP_FREQ:
507 idx = data->channel_data[chan->address].data_rate;
508 *val = data->data_rate[idx];
515 mutex_unlock(&data->lock);
520 static int ads1015_write_raw(struct iio_dev *indio_dev,
521 struct iio_chan_spec const *chan, int val,
524 struct ads1015_data *data = iio_priv(indio_dev);
527 mutex_lock(&data->lock);
529 case IIO_CHAN_INFO_SCALE:
530 ret = ads1015_set_scale(data, chan, val, val2);
532 case IIO_CHAN_INFO_SAMP_FREQ:
533 ret = ads1015_set_data_rate(data, chan->address, val);
539 mutex_unlock(&data->lock);
544 static int ads1015_read_event(struct iio_dev *indio_dev,
545 const struct iio_chan_spec *chan, enum iio_event_type type,
546 enum iio_event_direction dir, enum iio_event_info info, int *val,
549 struct ads1015_data *data = iio_priv(indio_dev);
551 unsigned int comp_queue;
555 mutex_lock(&data->lock);
558 case IIO_EV_INFO_VALUE:
559 *val = (dir == IIO_EV_DIR_RISING) ?
560 data->thresh_data[chan->address].high_thresh :
561 data->thresh_data[chan->address].low_thresh;
564 case IIO_EV_INFO_PERIOD:
565 dr = data->channel_data[chan->address].data_rate;
566 comp_queue = data->thresh_data[chan->address].comp_queue;
567 period = ads1015_comp_queue[comp_queue] *
568 USEC_PER_SEC / data->data_rate[dr];
570 *val = period / USEC_PER_SEC;
571 *val2 = period % USEC_PER_SEC;
572 ret = IIO_VAL_INT_PLUS_MICRO;
579 mutex_unlock(&data->lock);
584 static int ads1015_write_event(struct iio_dev *indio_dev,
585 const struct iio_chan_spec *chan, enum iio_event_type type,
586 enum iio_event_direction dir, enum iio_event_info info, int val,
589 struct ads1015_data *data = iio_priv(indio_dev);
590 int realbits = chan->scan_type.realbits;
596 mutex_lock(&data->lock);
599 case IIO_EV_INFO_VALUE:
600 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
604 if (dir == IIO_EV_DIR_RISING)
605 data->thresh_data[chan->address].high_thresh = val;
607 data->thresh_data[chan->address].low_thresh = val;
609 case IIO_EV_INFO_PERIOD:
610 dr = data->channel_data[chan->address].data_rate;
611 period = val * USEC_PER_SEC + val2;
613 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
614 if (period <= ads1015_comp_queue[i] *
615 USEC_PER_SEC / data->data_rate[dr])
618 data->thresh_data[chan->address].comp_queue = i;
625 mutex_unlock(&data->lock);
630 static int ads1015_read_event_config(struct iio_dev *indio_dev,
631 const struct iio_chan_spec *chan, enum iio_event_type type,
632 enum iio_event_direction dir)
634 struct ads1015_data *data = iio_priv(indio_dev);
637 mutex_lock(&data->lock);
638 if (data->event_channel == chan->address) {
640 case IIO_EV_DIR_RISING:
643 case IIO_EV_DIR_EITHER:
644 ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
651 mutex_unlock(&data->lock);
656 static int ads1015_enable_event_config(struct ads1015_data *data,
657 const struct iio_chan_spec *chan, int comp_mode)
659 int low_thresh = data->thresh_data[chan->address].low_thresh;
660 int high_thresh = data->thresh_data[chan->address].high_thresh;
664 if (ads1015_event_channel_enabled(data)) {
665 if (data->event_channel != chan->address ||
666 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
667 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
673 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
674 low_thresh = max(-1 << (chan->scan_type.realbits - 1),
677 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
678 low_thresh << chan->scan_type.shift);
682 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
683 high_thresh << chan->scan_type.shift);
687 ret = ads1015_set_power_state(data, true);
691 ads1015_event_channel_enable(data, chan->address, comp_mode);
693 ret = ads1015_get_adc_result(data, chan->address, &val);
695 ads1015_event_channel_disable(data, chan->address);
696 ads1015_set_power_state(data, false);
702 static int ads1015_disable_event_config(struct ads1015_data *data,
703 const struct iio_chan_spec *chan, int comp_mode)
707 if (!ads1015_event_channel_enabled(data))
710 if (data->event_channel != chan->address)
713 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
714 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
717 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
718 ADS1015_CFG_COMP_QUE_MASK,
719 ADS1015_CFG_COMP_DISABLE <<
720 ADS1015_CFG_COMP_QUE_SHIFT);
724 ads1015_event_channel_disable(data, chan->address);
726 return ads1015_set_power_state(data, false);
729 static int ads1015_write_event_config(struct iio_dev *indio_dev,
730 const struct iio_chan_spec *chan, enum iio_event_type type,
731 enum iio_event_direction dir, int state)
733 struct ads1015_data *data = iio_priv(indio_dev);
735 int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
736 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
738 mutex_lock(&data->lock);
740 /* Prevent from enabling both buffer and event at a time */
741 ret = iio_device_claim_direct_mode(indio_dev);
743 mutex_unlock(&data->lock);
748 ret = ads1015_enable_event_config(data, chan, comp_mode);
750 ret = ads1015_disable_event_config(data, chan, comp_mode);
752 iio_device_release_direct_mode(indio_dev);
753 mutex_unlock(&data->lock);
758 static irqreturn_t ads1015_event_handler(int irq, void *priv)
760 struct iio_dev *indio_dev = priv;
761 struct ads1015_data *data = iio_priv(indio_dev);
765 /* Clear the latched ALERT/RDY pin */
766 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
770 if (ads1015_event_channel_enabled(data)) {
771 enum iio_event_direction dir;
774 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
775 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
776 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
777 IIO_EV_TYPE_THRESH, dir);
778 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
784 static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
786 struct ads1015_data *data = iio_priv(indio_dev);
788 /* Prevent from enabling both buffer and event at a time */
789 if (ads1015_event_channel_enabled(data))
792 return ads1015_set_power_state(iio_priv(indio_dev), true);
795 static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
797 return ads1015_set_power_state(iio_priv(indio_dev), false);
800 static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
801 .preenable = ads1015_buffer_preenable,
802 .postenable = iio_triggered_buffer_postenable,
803 .predisable = iio_triggered_buffer_predisable,
804 .postdisable = ads1015_buffer_postdisable,
805 .validate_scan_mask = &iio_validate_scan_mask_onehot,
808 static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
809 "3 2 1 0.5 0.25 0.125");
810 static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
811 "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
813 static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
814 sampling_frequency_available, "128 250 490 920 1600 2400 3300");
815 static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
816 sampling_frequency_available, "8 16 32 64 128 250 475 860");
818 static struct attribute *ads1015_attributes[] = {
819 &iio_const_attr_ads1015_scale_available.dev_attr.attr,
820 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
824 static const struct attribute_group ads1015_attribute_group = {
825 .attrs = ads1015_attributes,
828 static struct attribute *ads1115_attributes[] = {
829 &iio_const_attr_ads1115_scale_available.dev_attr.attr,
830 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
834 static const struct attribute_group ads1115_attribute_group = {
835 .attrs = ads1115_attributes,
838 static const struct iio_info ads1015_info = {
839 .driver_module = THIS_MODULE,
840 .read_raw = ads1015_read_raw,
841 .write_raw = ads1015_write_raw,
842 .read_event_value = ads1015_read_event,
843 .write_event_value = ads1015_write_event,
844 .read_event_config = ads1015_read_event_config,
845 .write_event_config = ads1015_write_event_config,
846 .attrs = &ads1015_attribute_group,
849 static const struct iio_info ads1115_info = {
850 .driver_module = THIS_MODULE,
851 .read_raw = ads1015_read_raw,
852 .write_raw = ads1015_write_raw,
853 .read_event_value = ads1015_read_event,
854 .write_event_value = ads1015_write_event,
855 .read_event_config = ads1015_read_event_config,
856 .write_event_config = ads1015_write_event_config,
857 .attrs = &ads1115_attribute_group,
861 static int ads1015_get_channels_config_of(struct i2c_client *client)
863 struct iio_dev *indio_dev = i2c_get_clientdata(client);
864 struct ads1015_data *data = iio_priv(indio_dev);
865 struct device_node *node;
867 if (!client->dev.of_node ||
868 !of_get_next_child(client->dev.of_node, NULL))
871 for_each_child_of_node(client->dev.of_node, node) {
873 unsigned int channel;
874 unsigned int pga = ADS1015_DEFAULT_PGA;
875 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
877 if (of_property_read_u32(node, "reg", &pval)) {
878 dev_err(&client->dev, "invalid reg on %pOF\n",
884 if (channel >= ADS1015_CHANNELS) {
885 dev_err(&client->dev,
886 "invalid channel index %d on %pOF\n",
891 if (!of_property_read_u32(node, "ti,gain", &pval)) {
894 dev_err(&client->dev, "invalid gain on %pOF\n",
901 if (!of_property_read_u32(node, "ti,datarate", &pval)) {
904 dev_err(&client->dev,
905 "invalid data_rate on %pOF\n",
912 data->channel_data[channel].pga = pga;
913 data->channel_data[channel].data_rate = data_rate;
920 static void ads1015_get_channels_config(struct i2c_client *client)
924 struct iio_dev *indio_dev = i2c_get_clientdata(client);
925 struct ads1015_data *data = iio_priv(indio_dev);
926 struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
928 /* prefer platform data */
930 memcpy(data->channel_data, pdata->channel_data,
931 sizeof(data->channel_data));
936 if (!ads1015_get_channels_config_of(client))
939 /* fallback on default configuration */
940 for (k = 0; k < ADS1015_CHANNELS; ++k) {
941 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
942 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
946 static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
948 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
949 ADS1015_CFG_MOD_MASK,
950 mode << ADS1015_CFG_MOD_SHIFT);
953 static int ads1015_probe(struct i2c_client *client,
954 const struct i2c_device_id *id)
956 struct iio_dev *indio_dev;
957 struct ads1015_data *data;
962 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
966 data = iio_priv(indio_dev);
967 i2c_set_clientdata(client, indio_dev);
969 mutex_init(&data->lock);
971 indio_dev->dev.parent = &client->dev;
972 indio_dev->dev.of_node = client->dev.of_node;
973 indio_dev->name = ADS1015_DRV_NAME;
974 indio_dev->modes = INDIO_DIRECT_MODE;
976 if (client->dev.of_node)
977 chip = (enum chip_ids)of_device_get_match_data(&client->dev);
979 chip = id->driver_data;
982 indio_dev->channels = ads1015_channels;
983 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
984 indio_dev->info = &ads1015_info;
985 data->data_rate = (unsigned int *) &ads1015_data_rate;
988 indio_dev->channels = ads1115_channels;
989 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
990 indio_dev->info = &ads1115_info;
991 data->data_rate = (unsigned int *) &ads1115_data_rate;
995 data->event_channel = ADS1015_CHANNELS;
997 * Set default lower and upper threshold to min and max value
1000 for (i = 0; i < ADS1015_CHANNELS; i++) {
1001 int realbits = indio_dev->channels[i].scan_type.realbits;
1003 data->thresh_data[i].low_thresh = -1 << (realbits - 1);
1004 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
1007 /* we need to keep this ABI the same as used by hwmon ADS1015 driver */
1008 ads1015_get_channels_config(client);
1010 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
1011 if (IS_ERR(data->regmap)) {
1012 dev_err(&client->dev, "Failed to allocate register map\n");
1013 return PTR_ERR(data->regmap);
1016 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1017 ads1015_trigger_handler,
1018 &ads1015_buffer_setup_ops);
1020 dev_err(&client->dev, "iio triggered buffer setup failed\n");
1025 unsigned long irq_trig =
1026 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1027 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
1028 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
1029 unsigned int cfg_comp =
1030 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1031 1 << ADS1015_CFG_COMP_LAT_SHIFT;
1034 case IRQF_TRIGGER_LOW:
1035 cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1036 ADS1015_CFG_COMP_POL_SHIFT;
1038 case IRQF_TRIGGER_HIGH:
1039 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1040 ADS1015_CFG_COMP_POL_SHIFT;
1046 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1047 cfg_comp_mask, cfg_comp);
1051 ret = devm_request_threaded_irq(&client->dev, client->irq,
1052 NULL, ads1015_event_handler,
1053 irq_trig | IRQF_ONESHOT,
1054 client->name, indio_dev);
1059 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1063 data->conv_invalid = true;
1065 ret = pm_runtime_set_active(&client->dev);
1068 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1069 pm_runtime_use_autosuspend(&client->dev);
1070 pm_runtime_enable(&client->dev);
1072 ret = iio_device_register(indio_dev);
1074 dev_err(&client->dev, "Failed to register IIO device\n");
1081 static int ads1015_remove(struct i2c_client *client)
1083 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1084 struct ads1015_data *data = iio_priv(indio_dev);
1086 iio_device_unregister(indio_dev);
1088 pm_runtime_disable(&client->dev);
1089 pm_runtime_set_suspended(&client->dev);
1090 pm_runtime_put_noidle(&client->dev);
1092 /* power down single shot mode */
1093 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1097 static int ads1015_runtime_suspend(struct device *dev)
1099 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1100 struct ads1015_data *data = iio_priv(indio_dev);
1102 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1105 static int ads1015_runtime_resume(struct device *dev)
1107 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1108 struct ads1015_data *data = iio_priv(indio_dev);
1111 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1113 data->conv_invalid = true;
1119 static const struct dev_pm_ops ads1015_pm_ops = {
1120 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1121 ads1015_runtime_resume, NULL)
1124 static const struct i2c_device_id ads1015_id[] = {
1125 {"ads1015", ADS1015},
1126 {"ads1115", ADS1115},
1129 MODULE_DEVICE_TABLE(i2c, ads1015_id);
1131 static const struct of_device_id ads1015_of_match[] = {
1133 .compatible = "ti,ads1015",
1134 .data = (void *)ADS1015
1137 .compatible = "ti,ads1115",
1138 .data = (void *)ADS1115
1142 MODULE_DEVICE_TABLE(of, ads1015_of_match);
1144 static struct i2c_driver ads1015_driver = {
1146 .name = ADS1015_DRV_NAME,
1147 .of_match_table = ads1015_of_match,
1148 .pm = &ads1015_pm_ops,
1150 .probe = ads1015_probe,
1151 .remove = ads1015_remove,
1152 .id_table = ads1015_id,
1155 module_i2c_driver(ads1015_driver);
1157 MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1158 MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1159 MODULE_LICENSE("GPL v2");