1 // SPDX-License-Identifier: GPL-2.0
3 * This file is the ADC part of the STM32 DFSDM driver
5 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved
6 * Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
9 #include <linux/dmaengine.h>
10 #include <linux/dma-mapping.h>
11 #include <linux/iio/adc/stm32-dfsdm-adc.h>
12 #include <linux/iio/buffer.h>
13 #include <linux/iio/hw-consumer.h>
14 #include <linux/iio/sysfs.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
17 #include <linux/iio/trigger.h>
18 #include <linux/iio/trigger_consumer.h>
19 #include <linux/iio/triggered_buffer.h>
20 #include <linux/interrupt.h>
21 #include <linux/module.h>
22 #include <linux/of_device.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25 #include <linux/slab.h>
27 #include "stm32-dfsdm.h"
29 #define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
31 /* Conversion timeout */
32 #define DFSDM_TIMEOUT_US 100000
33 #define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
35 /* Oversampling attribute default */
36 #define DFSDM_DEFAULT_OVERSAMPLING 100
38 /* Oversampling max values */
39 #define DFSDM_MAX_INT_OVERSAMPLING 256
40 #define DFSDM_MAX_FL_OVERSAMPLING 1024
42 /* Limit filter output resolution to 31 bits. (i.e. sample range is +/-2^30) */
43 #define DFSDM_DATA_MAX BIT(30)
45 * Data are output as two's complement data in a 24 bit field.
46 * Data from filters are in the range +/-2^(n-1)
47 * 2^(n-1) maximum positive value cannot be coded in 2's complement n bits
48 * An extra bit is required to avoid wrap-around of the binary code for 2^(n-1)
49 * So, the resolution of samples from filter is actually limited to 23 bits
51 #define DFSDM_DATA_RES 24
53 /* Filter configuration */
54 #define DFSDM_CR1_CFG_MASK (DFSDM_CR1_RCH_MASK | DFSDM_CR1_RCONT_MASK | \
55 DFSDM_CR1_RSYNC_MASK | DFSDM_CR1_JSYNC_MASK | \
58 enum sd_converter_type {
63 struct stm32_dfsdm_dev_data {
65 int (*init)(struct device *dev, struct iio_dev *indio_dev);
66 unsigned int num_channels;
67 const struct regmap_config *regmap_cfg;
70 struct stm32_dfsdm_adc {
71 struct stm32_dfsdm *dfsdm;
72 const struct stm32_dfsdm_dev_data *dev_data;
78 unsigned int oversamp;
79 struct iio_hw_consumer *hwc;
80 struct completion completion;
84 unsigned int spi_freq; /* SPI bus clock frequency */
85 unsigned int sample_freq; /* Sample frequency after filter decimation */
86 int (*cb)(const void *data, size_t size, void *cb_priv);
91 unsigned int bufi; /* Buffer current position */
92 unsigned int buf_sz; /* Buffer size */
93 struct dma_chan *dma_chan;
97 struct stm32_dfsdm_str2field {
102 /* DFSDM channel serial interface type */
103 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
104 { "SPI_R", 0 }, /* SPI with data on rising edge */
105 { "SPI_F", 1 }, /* SPI with data on falling edge */
106 { "MANCH_R", 2 }, /* Manchester codec, rising edge = logic 0 */
107 { "MANCH_F", 3 }, /* Manchester codec, falling edge = logic 1 */
111 /* DFSDM channel clock source */
112 static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
113 /* External SPI clock (CLKIN x) */
114 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
115 /* Internal SPI clock (CLKOUT) */
116 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
117 /* Internal SPI clock divided by 2 (falling edge) */
118 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
119 /* Internal SPI clock divided by 2 (falling edge) */
120 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
124 static int stm32_dfsdm_str2val(const char *str,
125 const struct stm32_dfsdm_str2field *list)
127 const struct stm32_dfsdm_str2field *p = list;
129 for (p = list; p && p->name; p++)
130 if (!strcmp(p->name, str))
137 * struct stm32_dfsdm_trig_info - DFSDM trigger info
138 * @name: name of the trigger, corresponding to its source
139 * @jextsel: trigger signal selection
141 struct stm32_dfsdm_trig_info {
143 unsigned int jextsel;
146 /* hardware injected trigger enable, edge selection */
147 enum stm32_dfsdm_jexten {
148 STM32_DFSDM_JEXTEN_DISABLED,
149 STM32_DFSDM_JEXTEN_RISING_EDGE,
150 STM32_DFSDM_JEXTEN_FALLING_EDGE,
151 STM32_DFSDM_EXTEN_BOTH_EDGES,
154 static const struct stm32_dfsdm_trig_info stm32_dfsdm_trigs[] = {
170 static int stm32_dfsdm_get_jextsel(struct iio_dev *indio_dev,
171 struct iio_trigger *trig)
175 /* lookup triggers registered by stm32 timer trigger driver */
176 for (i = 0; stm32_dfsdm_trigs[i].name; i++) {
178 * Checking both stm32 timer trigger type and trig name
179 * should be safe against arbitrary trigger names.
181 if ((is_stm32_timer_trigger(trig) ||
182 is_stm32_lptim_trigger(trig)) &&
183 !strcmp(stm32_dfsdm_trigs[i].name, trig->name)) {
184 return stm32_dfsdm_trigs[i].jextsel;
191 static int stm32_dfsdm_compute_osrs(struct stm32_dfsdm_filter *fl,
192 unsigned int fast, unsigned int oversamp)
194 unsigned int i, d, fosr, iosr;
197 unsigned int m = 1; /* multiplication factor */
198 unsigned int p = fl->ford; /* filter order (ford) */
199 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fast];
201 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
203 * This function tries to compute filter oversampling and integrator
204 * oversampling, base on oversampling ratio requested by user.
206 * Decimation d depends on the filter order and the oversampling ratios.
208 * fosr: filter over sampling ratio
209 * iosr: integrator over sampling ratio
211 if (fl->ford == DFSDM_FASTSINC_ORDER) {
217 * Look for filter and integrator oversampling ratios which allows
218 * to maximize data output resolution.
220 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
221 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
224 else if (fl->ford == DFSDM_FASTSINC_ORDER)
225 d = fosr * (iosr + 3) + 2;
227 d = fosr * (iosr - 1 + p) + p;
231 else if (d != oversamp)
234 * Check resolution (limited to signed 32 bits)
237 * res = m * fosr^p x iosr (with m=1, p=ford)
239 * res = m * fosr^p x iosr (with m=2, p=2)
242 for (i = p - 1; i > 0; i--) {
243 res = res * (u64)fosr;
244 if (res > DFSDM_DATA_MAX)
247 if (res > DFSDM_DATA_MAX)
250 res = res * (u64)m * (u64)iosr;
251 if (res > DFSDM_DATA_MAX)
254 if (res >= flo->res) {
259 bits = fls(flo->res);
260 /* 8 LBSs in data register contain chan info */
263 /* if resolution is not a power of two */
264 if (flo->res > BIT(bits - 1))
269 shift = DFSDM_DATA_RES - bits;
271 * Compute right/left shift
272 * Right shift is performed by hardware
273 * when transferring samples to data register.
274 * Left shift is done by software on buffer
277 /* Resolution is lower than 24 bits */
282 * If resolution is 24 bits or more,
283 * max positive value may be ambiguous
284 * (equal to max negative value as sign
286 * Reduce resolution to 23 bits (rshift)
287 * to keep the sign on bit 23 and treat
288 * saturation before rescaling on 24
291 flo->rshift = 1 - shift;
298 pr_debug("%s: fast %d, fosr %d, iosr %d, res 0x%llx/%d bits, rshift %d, lshift %d\n",
299 __func__, fast, flo->fosr, flo->iosr,
300 flo->res, bits, flo->rshift,
312 static int stm32_dfsdm_compute_all_osrs(struct iio_dev *indio_dev,
313 unsigned int oversamp)
315 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
316 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
319 memset(&fl->flo[0], 0, sizeof(fl->flo[0]));
320 memset(&fl->flo[1], 0, sizeof(fl->flo[1]));
322 ret0 = stm32_dfsdm_compute_osrs(fl, 0, oversamp);
323 ret1 = stm32_dfsdm_compute_osrs(fl, 1, oversamp);
324 if (ret0 < 0 && ret1 < 0) {
325 dev_err(&indio_dev->dev,
326 "Filter parameters not found: errors %d/%d\n",
334 static int stm32_dfsdm_start_channel(struct iio_dev *indio_dev)
336 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
337 struct regmap *regmap = adc->dfsdm->regmap;
338 const struct iio_chan_spec *chan;
342 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
343 chan = indio_dev->channels + bit;
344 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
345 DFSDM_CHCFGR1_CHEN_MASK,
346 DFSDM_CHCFGR1_CHEN(1));
354 static void stm32_dfsdm_stop_channel(struct iio_dev *indio_dev)
356 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
357 struct regmap *regmap = adc->dfsdm->regmap;
358 const struct iio_chan_spec *chan;
361 for_each_set_bit(bit, &adc->smask, sizeof(adc->smask) * BITS_PER_BYTE) {
362 chan = indio_dev->channels + bit;
363 regmap_update_bits(regmap, DFSDM_CHCFGR1(chan->channel),
364 DFSDM_CHCFGR1_CHEN_MASK,
365 DFSDM_CHCFGR1_CHEN(0));
369 static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
370 struct stm32_dfsdm_channel *ch)
372 unsigned int id = ch->id;
373 struct regmap *regmap = dfsdm->regmap;
376 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
377 DFSDM_CHCFGR1_SITP_MASK,
378 DFSDM_CHCFGR1_SITP(ch->type));
381 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
382 DFSDM_CHCFGR1_SPICKSEL_MASK,
383 DFSDM_CHCFGR1_SPICKSEL(ch->src));
386 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
387 DFSDM_CHCFGR1_CHINSEL_MASK,
388 DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
391 static int stm32_dfsdm_start_filter(struct stm32_dfsdm_adc *adc,
393 struct iio_trigger *trig)
395 struct stm32_dfsdm *dfsdm = adc->dfsdm;
399 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
400 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
404 /* Nothing more to do for injected (scan mode/triggered) conversions */
405 if (adc->nconv > 1 || trig)
408 /* Software start (single or continuous) regular conversion */
409 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
410 DFSDM_CR1_RSWSTART_MASK,
411 DFSDM_CR1_RSWSTART(1));
414 static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm,
417 /* Disable conversion */
418 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
419 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
422 static int stm32_dfsdm_filter_set_trig(struct iio_dev *indio_dev,
424 struct iio_trigger *trig)
426 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
427 struct regmap *regmap = adc->dfsdm->regmap;
428 u32 jextsel = 0, jexten = STM32_DFSDM_JEXTEN_DISABLED;
432 ret = stm32_dfsdm_get_jextsel(indio_dev, trig);
436 /* set trigger source and polarity (default to rising edge) */
438 jexten = STM32_DFSDM_JEXTEN_RISING_EDGE;
441 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
442 DFSDM_CR1_JEXTSEL_MASK | DFSDM_CR1_JEXTEN_MASK,
443 DFSDM_CR1_JEXTSEL(jextsel) |
444 DFSDM_CR1_JEXTEN(jexten));
451 static int stm32_dfsdm_channels_configure(struct iio_dev *indio_dev,
453 struct iio_trigger *trig)
455 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
456 struct regmap *regmap = adc->dfsdm->regmap;
457 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
458 struct stm32_dfsdm_filter_osr *flo = &fl->flo[0];
459 const struct iio_chan_spec *chan;
466 * In continuous mode, use fast mode configuration,
467 * if it provides a better resolution.
469 if (adc->nconv == 1 && !trig &&
470 (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)) {
471 if (fl->flo[1].res >= fl->flo[0].res) {
480 dev_dbg(&indio_dev->dev, "Samples actual resolution: %d bits",
481 min(flo->bits, (u32)DFSDM_DATA_RES - 1));
483 for_each_set_bit(bit, &adc->smask,
484 sizeof(adc->smask) * BITS_PER_BYTE) {
485 chan = indio_dev->channels + bit;
487 ret = regmap_update_bits(regmap,
488 DFSDM_CHCFGR2(chan->channel),
489 DFSDM_CHCFGR2_DTRBS_MASK,
490 DFSDM_CHCFGR2_DTRBS(flo->rshift));
498 static int stm32_dfsdm_filter_configure(struct iio_dev *indio_dev,
500 struct iio_trigger *trig)
502 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
503 struct regmap *regmap = adc->dfsdm->regmap;
504 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[fl_id];
505 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
507 const struct iio_chan_spec *chan;
508 unsigned int bit, jchg = 0;
511 /* Average integrator oversampling */
512 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
513 DFSDM_FCR_IOSR(flo->iosr - 1));
517 /* Filter order and Oversampling */
518 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
519 DFSDM_FCR_FOSR(flo->fosr - 1));
523 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
524 DFSDM_FCR_FORD(fl->ford));
528 ret = stm32_dfsdm_filter_set_trig(indio_dev, fl_id, trig);
532 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id),
534 DFSDM_CR1_FAST(fl->fast));
539 * DFSDM modes configuration W.R.T audio/iio type modes
540 * ----------------------------------------------------------------
541 * Modes | regular | regular | injected | injected |
542 * | | continuous | | + scan |
543 * --------------|---------|--------------|----------|------------|
544 * single conv | x | | | |
546 * --------------|---------|--------------|----------|------------|
547 * 1 Audio chan | | sample freq | | |
548 * | | or sync_mode | | |
549 * --------------|---------|--------------|----------|------------|
550 * 1 IIO chan | | sample freq | trigger | |
551 * | | or sync_mode | | |
552 * --------------|---------|--------------|----------|------------|
553 * 2+ IIO chans | | | | trigger or |
554 * | | | | sync_mode |
555 * ----------------------------------------------------------------
557 if (adc->nconv == 1 && !trig) {
558 bit = __ffs(adc->smask);
559 chan = indio_dev->channels + bit;
561 /* Use regular conversion for single channel without trigger */
562 cr1 = DFSDM_CR1_RCH(chan->channel);
564 /* Continuous conversions triggered by SPI clk in buffer mode */
565 if (indio_dev->currentmode & INDIO_BUFFER_SOFTWARE)
566 cr1 |= DFSDM_CR1_RCONT(1);
568 cr1 |= DFSDM_CR1_RSYNC(fl->sync_mode);
570 /* Use injected conversion for multiple channels */
571 for_each_set_bit(bit, &adc->smask,
572 sizeof(adc->smask) * BITS_PER_BYTE) {
573 chan = indio_dev->channels + bit;
574 jchg |= BIT(chan->channel);
576 ret = regmap_write(regmap, DFSDM_JCHGR(fl_id), jchg);
580 /* Use scan mode for multiple channels */
581 cr1 = DFSDM_CR1_JSCAN((adc->nconv > 1) ? 1 : 0);
584 * Continuous conversions not supported in injected mode,
586 * - conversions in sync with filter 0
587 * - triggered conversions
589 if (!fl->sync_mode && !trig)
591 cr1 |= DFSDM_CR1_JSYNC(fl->sync_mode);
594 return regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_CFG_MASK,
598 static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
599 struct iio_dev *indio_dev,
600 struct iio_chan_spec *ch)
602 struct stm32_dfsdm_channel *df_ch;
604 int chan_idx = ch->scan_index;
607 ret = of_property_read_u32_index(indio_dev->dev.of_node,
608 "st,adc-channels", chan_idx,
611 dev_err(&indio_dev->dev,
612 " Error parsing 'st,adc-channels' for idx %d\n",
616 if (ch->channel >= dfsdm->num_chs) {
617 dev_err(&indio_dev->dev,
618 " Error bad channel number %d (max = %d)\n",
619 ch->channel, dfsdm->num_chs);
623 ret = of_property_read_string_index(indio_dev->dev.of_node,
624 "st,adc-channel-names", chan_idx,
625 &ch->datasheet_name);
627 dev_err(&indio_dev->dev,
628 " Error parsing 'st,adc-channel-names' for idx %d\n",
633 df_ch = &dfsdm->ch_list[ch->channel];
634 df_ch->id = ch->channel;
636 ret = of_property_read_string_index(indio_dev->dev.of_node,
637 "st,adc-channel-types", chan_idx,
640 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
648 ret = of_property_read_string_index(indio_dev->dev.of_node,
649 "st,adc-channel-clk-src", chan_idx,
652 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
660 ret = of_property_read_u32_index(indio_dev->dev.of_node,
661 "st,adc-alt-channel", chan_idx,
669 static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
671 const struct iio_chan_spec *chan,
674 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
676 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
679 static int dfsdm_adc_set_samp_freq(struct iio_dev *indio_dev,
680 unsigned int sample_freq,
681 unsigned int spi_freq)
683 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
684 unsigned int oversamp;
687 oversamp = DIV_ROUND_CLOSEST(spi_freq, sample_freq);
688 if (spi_freq % sample_freq)
689 dev_dbg(&indio_dev->dev,
690 "Rate not accurate. requested (%u), actual (%u)\n",
691 sample_freq, spi_freq / oversamp);
693 ret = stm32_dfsdm_compute_all_osrs(indio_dev, oversamp);
697 adc->sample_freq = spi_freq / oversamp;
698 adc->oversamp = oversamp;
703 static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
705 const struct iio_chan_spec *chan,
706 const char *buf, size_t len)
708 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
709 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
710 unsigned int sample_freq = adc->sample_freq;
711 unsigned int spi_freq;
714 dev_err(&indio_dev->dev, "enter %s\n", __func__);
715 /* If DFSDM is master on SPI, SPI freq can not be updated */
716 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
719 ret = kstrtoint(buf, 0, &spi_freq);
727 ret = dfsdm_adc_set_samp_freq(indio_dev, sample_freq, spi_freq);
731 adc->spi_freq = spi_freq;
736 static int stm32_dfsdm_start_conv(struct iio_dev *indio_dev,
737 struct iio_trigger *trig)
739 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
740 struct regmap *regmap = adc->dfsdm->regmap;
743 ret = stm32_dfsdm_channels_configure(indio_dev, adc->fl_id, trig);
747 ret = stm32_dfsdm_start_channel(indio_dev);
751 ret = stm32_dfsdm_filter_configure(indio_dev, adc->fl_id, trig);
755 ret = stm32_dfsdm_start_filter(adc, adc->fl_id, trig);
757 goto filter_unconfigure;
762 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
763 DFSDM_CR1_CFG_MASK, 0);
765 stm32_dfsdm_stop_channel(indio_dev);
770 static void stm32_dfsdm_stop_conv(struct iio_dev *indio_dev)
772 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
773 struct regmap *regmap = adc->dfsdm->regmap;
775 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
777 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
778 DFSDM_CR1_CFG_MASK, 0);
780 stm32_dfsdm_stop_channel(indio_dev);
783 static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
786 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
787 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
788 unsigned int rx_buf_sz = DFSDM_DMA_BUFFER_SIZE;
791 * DMA cyclic transfers are used, buffer is split into two periods.
793 * - always one buffer (period) DMA is working on
794 * - one buffer (period) driver pushed to ASoC side.
796 watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
797 adc->buf_sz = min(rx_buf_sz, watermark * 2 * adc->nconv);
802 static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
804 struct dma_tx_state state;
805 enum dma_status status;
807 status = dmaengine_tx_status(adc->dma_chan,
808 adc->dma_chan->cookie,
810 if (status == DMA_IN_PROGRESS) {
811 /* Residue is size in bytes from end of buffer */
812 unsigned int i = adc->buf_sz - state.residue;
815 /* Return available bytes */
817 size = i - adc->bufi;
819 size = adc->buf_sz + i - adc->bufi;
827 static inline void stm32_dfsdm_process_data(struct stm32_dfsdm_adc *adc,
830 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
831 struct stm32_dfsdm_filter_osr *flo = &fl->flo[fl->fast];
832 unsigned int i = adc->nconv;
836 /* Mask 8 LSB that contains the channel ID */
838 /* Convert 2^(n-1) sample to 2^(n-1)-1 to avoid wrap-around */
842 * Samples from filter are retrieved with 23 bits resolution
843 * or less. Shift left to align MSB on 24 bits.
845 *ptr <<= flo->lshift;
851 static void stm32_dfsdm_dma_buffer_done(void *data)
853 struct iio_dev *indio_dev = data;
854 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
855 int available = stm32_dfsdm_adc_dma_residue(adc);
859 * FIXME: In Kernel interface does not support cyclic DMA buffer,and
860 * offers only an interface to push data samples per samples.
861 * For this reason IIO buffer interface is not used and interface is
862 * bypassed using a private callback registered by ASoC.
863 * This should be a temporary solution waiting a cyclic DMA engine
867 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
868 adc->bufi, available);
871 while (available >= indio_dev->scan_bytes) {
872 s32 *buffer = (s32 *)&adc->rx_buf[adc->bufi];
874 stm32_dfsdm_process_data(adc, buffer);
876 available -= indio_dev->scan_bytes;
877 adc->bufi += indio_dev->scan_bytes;
878 if (adc->bufi >= adc->buf_sz) {
880 adc->cb(&adc->rx_buf[old_pos],
881 adc->buf_sz - old_pos, adc->cb_priv);
886 * In DMA mode the trigger services of IIO are not used
887 * (e.g. no call to iio_trigger_poll).
888 * Calling irq handler associated to the hardware trigger is not
889 * relevant as the conversions have already been done. Data
890 * transfers are performed directly in DMA callback instead.
891 * This implementation avoids to call trigger irq handler that
892 * may sleep, in an atomic context (DMA irq handler context).
894 if (adc->dev_data->type == DFSDM_IIO)
895 iio_push_to_buffers(indio_dev, buffer);
898 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
902 static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
904 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
906 * The DFSDM supports half-word transfers. However, for 16 bits record,
907 * 4 bytes buswidth is kept, to avoid losing samples LSBs when left
910 struct dma_slave_config config = {
911 .src_addr = (dma_addr_t)adc->dfsdm->phys_base,
912 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
914 struct dma_async_tx_descriptor *desc;
921 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
922 adc->buf_sz, adc->buf_sz / 2);
924 if (adc->nconv == 1 && !indio_dev->trig)
925 config.src_addr += DFSDM_RDATAR(adc->fl_id);
927 config.src_addr += DFSDM_JDATAR(adc->fl_id);
928 ret = dmaengine_slave_config(adc->dma_chan, &config);
932 /* Prepare a DMA cyclic transaction */
933 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
935 adc->buf_sz, adc->buf_sz / 2,
941 desc->callback = stm32_dfsdm_dma_buffer_done;
942 desc->callback_param = indio_dev;
944 cookie = dmaengine_submit(desc);
945 ret = dma_submit_error(cookie);
949 /* Issue pending DMA requests */
950 dma_async_issue_pending(adc->dma_chan);
952 if (adc->nconv == 1 && !indio_dev->trig) {
953 /* Enable regular DMA transfer*/
954 ret = regmap_update_bits(adc->dfsdm->regmap,
955 DFSDM_CR1(adc->fl_id),
956 DFSDM_CR1_RDMAEN_MASK,
957 DFSDM_CR1_RDMAEN_MASK);
959 /* Enable injected DMA transfer*/
960 ret = regmap_update_bits(adc->dfsdm->regmap,
961 DFSDM_CR1(adc->fl_id),
962 DFSDM_CR1_JDMAEN_MASK,
963 DFSDM_CR1_JDMAEN_MASK);
972 dmaengine_terminate_all(adc->dma_chan);
977 static void stm32_dfsdm_adc_dma_stop(struct iio_dev *indio_dev)
979 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
984 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR1(adc->fl_id),
985 DFSDM_CR1_RDMAEN_MASK | DFSDM_CR1_JDMAEN_MASK, 0);
986 dmaengine_terminate_all(adc->dma_chan);
989 static int stm32_dfsdm_update_scan_mode(struct iio_dev *indio_dev,
990 const unsigned long *scan_mask)
992 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
994 adc->nconv = bitmap_weight(scan_mask, indio_dev->masklength);
995 adc->smask = *scan_mask;
997 dev_dbg(&indio_dev->dev, "nconv=%d mask=%lx\n", adc->nconv, *scan_mask);
1002 static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
1004 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1007 /* Reset adc buffer index */
1011 ret = iio_hw_consumer_enable(adc->hwc);
1016 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1020 ret = stm32_dfsdm_adc_dma_start(indio_dev);
1022 dev_err(&indio_dev->dev, "Can't start DMA\n");
1026 ret = stm32_dfsdm_start_conv(indio_dev, indio_dev->trig);
1028 dev_err(&indio_dev->dev, "Can't start conversion\n");
1035 stm32_dfsdm_adc_dma_stop(indio_dev);
1037 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1040 iio_hw_consumer_disable(adc->hwc);
1045 static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
1047 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1049 stm32_dfsdm_stop_conv(indio_dev);
1051 stm32_dfsdm_adc_dma_stop(indio_dev);
1053 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1056 iio_hw_consumer_disable(adc->hwc);
1061 static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
1062 .postenable = &stm32_dfsdm_postenable,
1063 .predisable = &stm32_dfsdm_predisable,
1067 * stm32_dfsdm_get_buff_cb() - register a callback that will be called when
1068 * DMA transfer period is achieved.
1070 * @iio_dev: Handle to IIO device.
1071 * @cb: Pointer to callback function:
1072 * - data: pointer to data buffer
1073 * - size: size in byte of the data buffer
1074 * - private: pointer to consumer private structure.
1075 * @private: Pointer to consumer private structure.
1077 int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
1078 int (*cb)(const void *data, size_t size,
1082 struct stm32_dfsdm_adc *adc;
1086 adc = iio_priv(iio_dev);
1089 adc->cb_priv = private;
1093 EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
1096 * stm32_dfsdm_release_buff_cb - unregister buffer callback
1098 * @iio_dev: Handle to IIO device.
1100 int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
1102 struct stm32_dfsdm_adc *adc;
1106 adc = iio_priv(iio_dev);
1109 adc->cb_priv = NULL;
1113 EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
1115 static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
1116 const struct iio_chan_spec *chan, int *res)
1118 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1122 reinit_completion(&adc->completion);
1126 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
1130 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1131 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
1136 adc->smask = BIT(chan->scan_index);
1137 ret = stm32_dfsdm_start_conv(indio_dev, NULL);
1139 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1140 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1144 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
1147 /* Mask IRQ for regular conversion achievement*/
1148 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
1149 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
1153 else if (timeout < 0)
1158 stm32_dfsdm_stop_conv(indio_dev);
1160 stm32_dfsdm_process_data(adc, res);
1163 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
1168 static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
1169 struct iio_chan_spec const *chan,
1170 int val, int val2, long mask)
1172 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1173 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
1174 unsigned int spi_freq;
1178 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
1179 spi_freq = adc->dfsdm->spi_master_freq;
1181 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
1182 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
1183 spi_freq = adc->dfsdm->spi_master_freq / 2;
1186 spi_freq = adc->spi_freq;
1190 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1191 ret = iio_device_claim_direct_mode(indio_dev);
1195 ret = stm32_dfsdm_compute_all_osrs(indio_dev, val);
1197 dev_dbg(&indio_dev->dev,
1198 "Sampling rate changed from (%u) to (%u)\n",
1199 adc->sample_freq, spi_freq / val);
1200 adc->oversamp = val;
1201 adc->sample_freq = spi_freq / val;
1203 iio_device_release_direct_mode(indio_dev);
1206 case IIO_CHAN_INFO_SAMP_FREQ:
1210 ret = iio_device_claim_direct_mode(indio_dev);
1214 ret = dfsdm_adc_set_samp_freq(indio_dev, val, spi_freq);
1215 iio_device_release_direct_mode(indio_dev);
1222 static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
1223 struct iio_chan_spec const *chan, int *val,
1224 int *val2, long mask)
1226 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1230 case IIO_CHAN_INFO_RAW:
1231 ret = iio_device_claim_direct_mode(indio_dev);
1234 ret = iio_hw_consumer_enable(adc->hwc);
1236 dev_err(&indio_dev->dev,
1237 "%s: IIO enable failed (channel %d)\n",
1238 __func__, chan->channel);
1239 iio_device_release_direct_mode(indio_dev);
1242 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
1243 iio_hw_consumer_disable(adc->hwc);
1245 dev_err(&indio_dev->dev,
1246 "%s: Conversion failed (channel %d)\n",
1247 __func__, chan->channel);
1248 iio_device_release_direct_mode(indio_dev);
1251 iio_device_release_direct_mode(indio_dev);
1254 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
1255 *val = adc->oversamp;
1259 case IIO_CHAN_INFO_SAMP_FREQ:
1260 *val = adc->sample_freq;
1268 static int stm32_dfsdm_validate_trigger(struct iio_dev *indio_dev,
1269 struct iio_trigger *trig)
1271 return stm32_dfsdm_get_jextsel(indio_dev, trig) < 0 ? -EINVAL : 0;
1274 static const struct iio_info stm32_dfsdm_info_audio = {
1275 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1276 .read_raw = stm32_dfsdm_read_raw,
1277 .write_raw = stm32_dfsdm_write_raw,
1278 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1281 static const struct iio_info stm32_dfsdm_info_adc = {
1282 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
1283 .read_raw = stm32_dfsdm_read_raw,
1284 .write_raw = stm32_dfsdm_write_raw,
1285 .update_scan_mode = stm32_dfsdm_update_scan_mode,
1286 .validate_trigger = stm32_dfsdm_validate_trigger,
1289 static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
1291 struct iio_dev *indio_dev = arg;
1292 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1293 struct regmap *regmap = adc->dfsdm->regmap;
1294 unsigned int status, int_en;
1296 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
1297 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
1299 if (status & DFSDM_ISR_REOCF_MASK) {
1300 /* Read the data register clean the IRQ status */
1301 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
1302 complete(&adc->completion);
1305 if (status & DFSDM_ISR_ROVRF_MASK) {
1306 if (int_en & DFSDM_CR2_ROVRIE_MASK)
1307 dev_warn(&indio_dev->dev, "Overrun detected\n");
1308 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
1309 DFSDM_ICR_CLRROVRF_MASK,
1310 DFSDM_ICR_CLRROVRF_MASK);
1317 * Define external info for SPI Frequency and audio sampling rate that can be
1318 * configured by ASoC driver through consumer.h API
1320 static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
1321 /* spi_clk_freq : clock freq on SPI/manchester bus used by channel */
1323 .name = "spi_clk_freq",
1324 .shared = IIO_SHARED_BY_TYPE,
1325 .read = dfsdm_adc_audio_get_spiclk,
1326 .write = dfsdm_adc_audio_set_spiclk,
1331 static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
1333 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1335 if (adc->dma_chan) {
1336 dma_free_coherent(adc->dma_chan->device->dev,
1337 DFSDM_DMA_BUFFER_SIZE,
1338 adc->rx_buf, adc->dma_buf);
1339 dma_release_channel(adc->dma_chan);
1343 static int stm32_dfsdm_dma_request(struct device *dev,
1344 struct iio_dev *indio_dev)
1346 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1348 adc->dma_chan = dma_request_chan(dev, "rx");
1349 if (IS_ERR(adc->dma_chan)) {
1350 int ret = PTR_ERR(adc->dma_chan);
1352 adc->dma_chan = NULL;
1356 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
1357 DFSDM_DMA_BUFFER_SIZE,
1358 &adc->dma_buf, GFP_KERNEL);
1360 dma_release_channel(adc->dma_chan);
1364 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1365 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1370 static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
1371 struct iio_chan_spec *ch)
1373 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1376 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
1380 ch->type = IIO_VOLTAGE;
1384 * IIO_CHAN_INFO_RAW: used to compute regular conversion
1385 * IIO_CHAN_INFO_OVERSAMPLING_RATIO: used to set oversampling
1387 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
1388 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO) |
1389 BIT(IIO_CHAN_INFO_SAMP_FREQ);
1391 if (adc->dev_data->type == DFSDM_AUDIO) {
1392 ch->ext_info = dfsdm_adc_audio_ext_info;
1394 ch->scan_type.shift = 8;
1396 ch->scan_type.sign = 's';
1397 ch->scan_type.realbits = 24;
1398 ch->scan_type.storagebits = 32;
1400 return stm32_dfsdm_chan_configure(adc->dfsdm,
1401 &adc->dfsdm->ch_list[ch->channel]);
1404 static int stm32_dfsdm_audio_init(struct device *dev, struct iio_dev *indio_dev)
1406 struct iio_chan_spec *ch;
1407 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1408 struct stm32_dfsdm_channel *d_ch;
1411 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1417 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1419 dev_err(&indio_dev->dev, "Channels init failed\n");
1422 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1424 d_ch = &adc->dfsdm->ch_list[ch->channel];
1425 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1426 adc->spi_freq = adc->dfsdm->spi_master_freq;
1428 indio_dev->num_channels = 1;
1429 indio_dev->channels = ch;
1431 return stm32_dfsdm_dma_request(dev, indio_dev);
1434 static int stm32_dfsdm_adc_init(struct device *dev, struct iio_dev *indio_dev)
1436 struct iio_chan_spec *ch;
1437 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1441 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1442 ret = stm32_dfsdm_compute_all_osrs(indio_dev, adc->oversamp);
1446 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1448 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1449 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1450 return num_ch < 0 ? num_ch : -EINVAL;
1453 /* Bind to SD modulator IIO device */
1454 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1455 if (IS_ERR(adc->hwc))
1456 return -EPROBE_DEFER;
1458 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1463 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1464 ch[chan_idx].scan_index = chan_idx;
1465 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1467 dev_err(&indio_dev->dev, "Channels init failed\n");
1472 indio_dev->num_channels = num_ch;
1473 indio_dev->channels = ch;
1475 init_completion(&adc->completion);
1477 /* Optionally request DMA */
1478 ret = stm32_dfsdm_dma_request(dev, indio_dev);
1481 return dev_err_probe(dev, ret,
1482 "DMA channel request failed with\n");
1484 dev_dbg(dev, "No DMA support\n");
1488 ret = iio_triggered_buffer_setup(indio_dev,
1489 &iio_pollfunc_store_time, NULL,
1490 &stm32_dfsdm_buffer_setup_ops);
1492 stm32_dfsdm_dma_release(indio_dev);
1493 dev_err(&indio_dev->dev, "buffer setup failed\n");
1497 /* lptimer/timer hardware triggers */
1498 indio_dev->modes |= INDIO_HARDWARE_TRIGGERED;
1503 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1505 .init = stm32_dfsdm_adc_init,
1508 static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1509 .type = DFSDM_AUDIO,
1510 .init = stm32_dfsdm_audio_init,
1513 static const struct of_device_id stm32_dfsdm_adc_match[] = {
1515 .compatible = "st,stm32-dfsdm-adc",
1516 .data = &stm32h7_dfsdm_adc_data,
1519 .compatible = "st,stm32-dfsdm-dmic",
1520 .data = &stm32h7_dfsdm_audio_data,
1525 static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1527 struct device *dev = &pdev->dev;
1528 struct stm32_dfsdm_adc *adc;
1529 struct device_node *np = dev->of_node;
1530 const struct stm32_dfsdm_dev_data *dev_data;
1531 struct iio_dev *iio;
1535 dev_data = of_device_get_match_data(dev);
1536 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1538 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1542 adc = iio_priv(iio);
1543 adc->dfsdm = dev_get_drvdata(dev->parent);
1545 iio->dev.of_node = np;
1546 iio->modes = INDIO_DIRECT_MODE;
1548 platform_set_drvdata(pdev, iio);
1550 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1551 if (ret != 0 || adc->fl_id >= adc->dfsdm->num_fls) {
1552 dev_err(dev, "Missing or bad reg property\n");
1556 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1559 if (dev_data->type == DFSDM_AUDIO) {
1560 iio->info = &stm32_dfsdm_info_audio;
1561 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1563 iio->info = &stm32_dfsdm_info_adc;
1564 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1569 * In a first step IRQs generated for channels are not treated.
1570 * So IRQ associated to filter instance 0 is dedicated to the Filter 0.
1572 irq = platform_get_irq(pdev, 0);
1576 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1577 0, pdev->name, iio);
1579 dev_err(dev, "Failed to request IRQ\n");
1583 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1585 dev_err(dev, "Failed to set filter order\n");
1589 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1591 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1593 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1595 adc->dev_data = dev_data;
1596 ret = dev_data->init(dev, iio);
1600 ret = iio_device_register(iio);
1604 if (dev_data->type == DFSDM_AUDIO) {
1605 ret = of_platform_populate(np, NULL, NULL, dev);
1607 dev_err(dev, "Failed to find an audio DAI\n");
1608 goto err_unregister;
1615 iio_device_unregister(iio);
1617 stm32_dfsdm_dma_release(iio);
1622 static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1624 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1625 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1627 if (adc->dev_data->type == DFSDM_AUDIO)
1628 of_platform_depopulate(&pdev->dev);
1629 iio_device_unregister(indio_dev);
1630 stm32_dfsdm_dma_release(indio_dev);
1635 static int __maybe_unused stm32_dfsdm_adc_suspend(struct device *dev)
1637 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1639 if (iio_buffer_enabled(indio_dev))
1640 stm32_dfsdm_predisable(indio_dev);
1645 static int __maybe_unused stm32_dfsdm_adc_resume(struct device *dev)
1647 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1648 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1649 const struct iio_chan_spec *chan;
1650 struct stm32_dfsdm_channel *ch;
1653 /* restore channels configuration */
1654 for (i = 0; i < indio_dev->num_channels; i++) {
1655 chan = indio_dev->channels + i;
1656 ch = &adc->dfsdm->ch_list[chan->channel];
1657 ret = stm32_dfsdm_chan_configure(adc->dfsdm, ch);
1662 if (iio_buffer_enabled(indio_dev))
1663 stm32_dfsdm_postenable(indio_dev);
1668 static SIMPLE_DEV_PM_OPS(stm32_dfsdm_adc_pm_ops,
1669 stm32_dfsdm_adc_suspend, stm32_dfsdm_adc_resume);
1671 static struct platform_driver stm32_dfsdm_adc_driver = {
1673 .name = "stm32-dfsdm-adc",
1674 .of_match_table = stm32_dfsdm_adc_match,
1675 .pm = &stm32_dfsdm_adc_pm_ops,
1677 .probe = stm32_dfsdm_adc_probe,
1678 .remove = stm32_dfsdm_adc_remove,
1680 module_platform_driver(stm32_dfsdm_adc_driver);
1682 MODULE_DESCRIPTION("STM32 sigma delta ADC");
1683 MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1684 MODULE_LICENSE("GPL v2");