2 * Freescale MXS LRADC ADC driver
4 * Copyright (c) 2012 DENX Software Engineering, GmbH.
5 * Copyright (c) 2017 Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
8 * Marek Vasut <marex@denx.de>
9 * Ksenija Stanojevic <ksenija.stanojevic@gmail.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or
14 * (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
22 #include <linux/completion.h>
23 #include <linux/device.h>
24 #include <linux/err.h>
25 #include <linux/interrupt.h>
26 #include <linux/mfd/core.h>
27 #include <linux/mfd/mxs-lradc.h>
28 #include <linux/module.h>
29 #include <linux/of_irq.h>
30 #include <linux/platform_device.h>
31 #include <linux/sysfs.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/iio.h>
35 #include <linux/iio/trigger.h>
36 #include <linux/iio/trigger_consumer.h>
37 #include <linux/iio/triggered_buffer.h>
38 #include <linux/iio/sysfs.h>
41 * Make this runtime configurable if necessary. Currently, if the buffered mode
42 * is enabled, the LRADC takes LRADC_DELAY_TIMER_LOOP samples of data before
43 * triggering IRQ. The sampling happens every (LRADC_DELAY_TIMER_PER / 2000)
44 * seconds. The result is that the samples arrive every 500mS.
46 #define LRADC_DELAY_TIMER_PER 200
47 #define LRADC_DELAY_TIMER_LOOP 5
49 #define VREF_MV_BASE 1850
51 static const char *mx23_lradc_adc_irq_names[] = {
60 static const char *mx28_lradc_adc_irq_names[] = {
73 static const u32 mxs_lradc_adc_vref_mv[][LRADC_MAX_TOTAL_CHANS] = {
75 VREF_MV_BASE, /* CH0 */
76 VREF_MV_BASE, /* CH1 */
77 VREF_MV_BASE, /* CH2 */
78 VREF_MV_BASE, /* CH3 */
79 VREF_MV_BASE, /* CH4 */
80 VREF_MV_BASE, /* CH5 */
81 VREF_MV_BASE * 2, /* CH6 VDDIO */
82 VREF_MV_BASE * 4, /* CH7 VBATT */
83 VREF_MV_BASE, /* CH8 Temp sense 0 */
84 VREF_MV_BASE, /* CH9 Temp sense 1 */
85 VREF_MV_BASE, /* CH10 */
86 VREF_MV_BASE, /* CH11 */
87 VREF_MV_BASE, /* CH12 USB_DP */
88 VREF_MV_BASE, /* CH13 USB_DN */
89 VREF_MV_BASE, /* CH14 VBG */
90 VREF_MV_BASE * 4, /* CH15 VDD5V */
93 VREF_MV_BASE, /* CH0 */
94 VREF_MV_BASE, /* CH1 */
95 VREF_MV_BASE, /* CH2 */
96 VREF_MV_BASE, /* CH3 */
97 VREF_MV_BASE, /* CH4 */
98 VREF_MV_BASE, /* CH5 */
99 VREF_MV_BASE, /* CH6 */
100 VREF_MV_BASE * 4, /* CH7 VBATT */
101 VREF_MV_BASE, /* CH8 Temp sense 0 */
102 VREF_MV_BASE, /* CH9 Temp sense 1 */
103 VREF_MV_BASE * 2, /* CH10 VDDIO */
104 VREF_MV_BASE, /* CH11 VTH */
105 VREF_MV_BASE * 2, /* CH12 VDDA */
106 VREF_MV_BASE, /* CH13 VDDD */
107 VREF_MV_BASE, /* CH14 VBG */
108 VREF_MV_BASE * 4, /* CH15 VDD5V */
112 enum mxs_lradc_divbytwo {
113 MXS_LRADC_DIV_DISABLED = 0,
114 MXS_LRADC_DIV_ENABLED,
117 struct mxs_lradc_scale {
118 unsigned int integer;
122 struct mxs_lradc_adc {
123 struct mxs_lradc *lradc;
127 /* Maximum of 8 channels + 8 byte ts */
128 u32 buffer[10] __aligned(8);
129 struct iio_trigger *trig;
130 struct completion completion;
134 struct mxs_lradc_scale scale_avail[LRADC_MAX_TOTAL_CHANS][2];
135 unsigned long is_divided;
139 /* Raw I/O operations */
140 static int mxs_lradc_adc_read_single(struct iio_dev *iio_dev, int chan,
143 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
144 struct mxs_lradc *lradc = adc->lradc;
148 * See if there is no buffered operation in progress. If there is simply
149 * bail out. This can be improved to support both buffered and raw IO at
150 * the same time, yet the code becomes horribly complicated. Therefore I
151 * applied KISS principle here.
153 ret = iio_device_claim_direct_mode(iio_dev);
157 reinit_completion(&adc->completion);
160 * No buffered operation in progress, map the channel and trigger it.
161 * Virtual channel 0 is always used here as the others are always not
162 * used if doing raw sampling.
164 if (lradc->soc == IMX28_LRADC)
165 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
166 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
167 writel(0x1, adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
169 /* Enable / disable the divider per requirement */
170 if (test_bit(chan, &adc->is_divided))
171 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
172 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_SET);
174 writel(1 << LRADC_CTRL2_DIVIDE_BY_TWO_OFFSET,
175 adc->base + LRADC_CTRL2 + STMP_OFFSET_REG_CLR);
177 /* Clean the slot's previous content, then set new one. */
178 writel(LRADC_CTRL4_LRADCSELECT_MASK(0),
179 adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
180 writel(chan, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
182 writel(0, adc->base + LRADC_CH(0));
184 /* Enable the IRQ and start sampling the channel. */
185 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
186 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
187 writel(BIT(0), adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_SET);
189 /* Wait for completion on the channel, 1 second max. */
190 ret = wait_for_completion_killable_timeout(&adc->completion, HZ);
197 *val = readl(adc->base + LRADC_CH(0)) & LRADC_CH_VALUE_MASK;
201 writel(LRADC_CTRL1_LRADC_IRQ_EN(0),
202 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
204 iio_device_release_direct_mode(iio_dev);
209 static int mxs_lradc_adc_read_temp(struct iio_dev *iio_dev, int *val)
213 ret = mxs_lradc_adc_read_single(iio_dev, 8, &min);
214 if (ret != IIO_VAL_INT)
217 ret = mxs_lradc_adc_read_single(iio_dev, 9, &max);
218 if (ret != IIO_VAL_INT)
226 static int mxs_lradc_adc_read_raw(struct iio_dev *iio_dev,
227 const struct iio_chan_spec *chan,
228 int *val, int *val2, long m)
230 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
233 case IIO_CHAN_INFO_RAW:
234 if (chan->type == IIO_TEMP)
235 return mxs_lradc_adc_read_temp(iio_dev, val);
237 return mxs_lradc_adc_read_single(iio_dev, chan->channel, val);
239 case IIO_CHAN_INFO_SCALE:
240 if (chan->type == IIO_TEMP) {
242 * From the datasheet, we have to multiply by 1.012 and
247 return IIO_VAL_INT_PLUS_MICRO;
250 *val = adc->vref_mv[chan->channel];
251 *val2 = chan->scan_type.realbits -
252 test_bit(chan->channel, &adc->is_divided);
253 return IIO_VAL_FRACTIONAL_LOG2;
255 case IIO_CHAN_INFO_OFFSET:
256 if (chan->type == IIO_TEMP) {
258 * The calculated value from the ADC is in Kelvin, we
259 * want Celsius for hwmon so the offset is -273.15
260 * The offset is applied before scaling so it is
261 * actually -213.15 * 4 / 1.012 = -1079.644268
266 return IIO_VAL_INT_PLUS_MICRO;
278 static int mxs_lradc_adc_write_raw(struct iio_dev *iio_dev,
279 const struct iio_chan_spec *chan,
280 int val, int val2, long m)
282 struct mxs_lradc_adc *adc = iio_priv(iio_dev);
283 struct mxs_lradc_scale *scale_avail =
284 adc->scale_avail[chan->channel];
287 ret = iio_device_claim_direct_mode(iio_dev);
292 case IIO_CHAN_INFO_SCALE:
294 if (val == scale_avail[MXS_LRADC_DIV_DISABLED].integer &&
295 val2 == scale_avail[MXS_LRADC_DIV_DISABLED].nano) {
296 /* divider by two disabled */
297 clear_bit(chan->channel, &adc->is_divided);
299 } else if (val == scale_avail[MXS_LRADC_DIV_ENABLED].integer &&
300 val2 == scale_avail[MXS_LRADC_DIV_ENABLED].nano) {
301 /* divider by two enabled */
302 set_bit(chan->channel, &adc->is_divided);
312 iio_device_release_direct_mode(iio_dev);
317 static int mxs_lradc_adc_write_raw_get_fmt(struct iio_dev *iio_dev,
318 const struct iio_chan_spec *chan,
321 return IIO_VAL_INT_PLUS_NANO;
324 static ssize_t mxs_lradc_adc_show_scale_avail(struct device *dev,
325 struct device_attribute *attr,
328 struct iio_dev *iio = dev_to_iio_dev(dev);
329 struct mxs_lradc_adc *adc = iio_priv(iio);
330 struct iio_dev_attr *iio_attr = to_iio_dev_attr(attr);
333 ch = iio_attr->address;
334 for (i = 0; i < ARRAY_SIZE(adc->scale_avail[ch]); i++)
335 len += sprintf(buf + len, "%u.%09u ",
336 adc->scale_avail[ch][i].integer,
337 adc->scale_avail[ch][i].nano);
339 len += sprintf(buf + len, "\n");
344 #define SHOW_SCALE_AVAILABLE_ATTR(ch)\
345 IIO_DEVICE_ATTR(in_voltage##ch##_scale_available, 0444,\
346 mxs_lradc_adc_show_scale_avail, NULL, ch)
348 static SHOW_SCALE_AVAILABLE_ATTR(0);
349 static SHOW_SCALE_AVAILABLE_ATTR(1);
350 static SHOW_SCALE_AVAILABLE_ATTR(2);
351 static SHOW_SCALE_AVAILABLE_ATTR(3);
352 static SHOW_SCALE_AVAILABLE_ATTR(4);
353 static SHOW_SCALE_AVAILABLE_ATTR(5);
354 static SHOW_SCALE_AVAILABLE_ATTR(6);
355 static SHOW_SCALE_AVAILABLE_ATTR(7);
356 static SHOW_SCALE_AVAILABLE_ATTR(10);
357 static SHOW_SCALE_AVAILABLE_ATTR(11);
358 static SHOW_SCALE_AVAILABLE_ATTR(12);
359 static SHOW_SCALE_AVAILABLE_ATTR(13);
360 static SHOW_SCALE_AVAILABLE_ATTR(14);
361 static SHOW_SCALE_AVAILABLE_ATTR(15);
363 static struct attribute *mxs_lradc_adc_attributes[] = {
364 &iio_dev_attr_in_voltage0_scale_available.dev_attr.attr,
365 &iio_dev_attr_in_voltage1_scale_available.dev_attr.attr,
366 &iio_dev_attr_in_voltage2_scale_available.dev_attr.attr,
367 &iio_dev_attr_in_voltage3_scale_available.dev_attr.attr,
368 &iio_dev_attr_in_voltage4_scale_available.dev_attr.attr,
369 &iio_dev_attr_in_voltage5_scale_available.dev_attr.attr,
370 &iio_dev_attr_in_voltage6_scale_available.dev_attr.attr,
371 &iio_dev_attr_in_voltage7_scale_available.dev_attr.attr,
372 &iio_dev_attr_in_voltage10_scale_available.dev_attr.attr,
373 &iio_dev_attr_in_voltage11_scale_available.dev_attr.attr,
374 &iio_dev_attr_in_voltage12_scale_available.dev_attr.attr,
375 &iio_dev_attr_in_voltage13_scale_available.dev_attr.attr,
376 &iio_dev_attr_in_voltage14_scale_available.dev_attr.attr,
377 &iio_dev_attr_in_voltage15_scale_available.dev_attr.attr,
381 static const struct attribute_group mxs_lradc_adc_attribute_group = {
382 .attrs = mxs_lradc_adc_attributes,
385 static const struct iio_info mxs_lradc_adc_iio_info = {
386 .driver_module = THIS_MODULE,
387 .read_raw = mxs_lradc_adc_read_raw,
388 .write_raw = mxs_lradc_adc_write_raw,
389 .write_raw_get_fmt = mxs_lradc_adc_write_raw_get_fmt,
390 .attrs = &mxs_lradc_adc_attribute_group,
394 static irqreturn_t mxs_lradc_adc_handle_irq(int irq, void *data)
396 struct iio_dev *iio = data;
397 struct mxs_lradc_adc *adc = iio_priv(iio);
398 struct mxs_lradc *lradc = adc->lradc;
399 unsigned long reg = readl(adc->base + LRADC_CTRL1);
402 if (!(reg & mxs_lradc_irq_mask(lradc)))
405 if (iio_buffer_enabled(iio)) {
406 if (reg & lradc->buffer_vchans) {
407 spin_lock_irqsave(&adc->lock, flags);
408 iio_trigger_poll(iio->trig);
409 spin_unlock_irqrestore(&adc->lock, flags);
411 } else if (reg & LRADC_CTRL1_LRADC_IRQ(0)) {
412 complete(&adc->completion);
415 writel(reg & mxs_lradc_irq_mask(lradc),
416 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
422 /* Trigger handling */
423 static irqreturn_t mxs_lradc_adc_trigger_handler(int irq, void *p)
425 struct iio_poll_func *pf = p;
426 struct iio_dev *iio = pf->indio_dev;
427 struct mxs_lradc_adc *adc = iio_priv(iio);
428 const u32 chan_value = LRADC_CH_ACCUMULATE |
429 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
430 unsigned int i, j = 0;
432 for_each_set_bit(i, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
433 adc->buffer[j] = readl(adc->base + LRADC_CH(j));
434 writel(chan_value, adc->base + LRADC_CH(j));
435 adc->buffer[j] &= LRADC_CH_VALUE_MASK;
436 adc->buffer[j] /= LRADC_DELAY_TIMER_LOOP;
440 iio_push_to_buffers_with_timestamp(iio, adc->buffer, pf->timestamp);
442 iio_trigger_notify_done(iio->trig);
447 static int mxs_lradc_adc_configure_trigger(struct iio_trigger *trig, bool state)
449 struct iio_dev *iio = iio_trigger_get_drvdata(trig);
450 struct mxs_lradc_adc *adc = iio_priv(iio);
451 const u32 st = state ? STMP_OFFSET_REG_SET : STMP_OFFSET_REG_CLR;
453 writel(LRADC_DELAY_KICK, adc->base + (LRADC_DELAY(0) + st));
458 static const struct iio_trigger_ops mxs_lradc_adc_trigger_ops = {
459 .owner = THIS_MODULE,
460 .set_trigger_state = &mxs_lradc_adc_configure_trigger,
463 static int mxs_lradc_adc_trigger_init(struct iio_dev *iio)
466 struct iio_trigger *trig;
467 struct mxs_lradc_adc *adc = iio_priv(iio);
469 trig = devm_iio_trigger_alloc(&iio->dev, "%s-dev%i", iio->name,
472 trig->dev.parent = adc->dev;
473 iio_trigger_set_drvdata(trig, iio);
474 trig->ops = &mxs_lradc_adc_trigger_ops;
476 ret = iio_trigger_register(trig);
485 static void mxs_lradc_adc_trigger_remove(struct iio_dev *iio)
487 struct mxs_lradc_adc *adc = iio_priv(iio);
489 iio_trigger_unregister(adc->trig);
492 static int mxs_lradc_adc_buffer_preenable(struct iio_dev *iio)
494 struct mxs_lradc_adc *adc = iio_priv(iio);
495 struct mxs_lradc *lradc = adc->lradc;
497 unsigned long enable = 0;
501 const u32 chan_value = LRADC_CH_ACCUMULATE |
502 ((LRADC_DELAY_TIMER_LOOP - 1) << LRADC_CH_NUM_SAMPLES_OFFSET);
504 if (lradc->soc == IMX28_LRADC)
505 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
506 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
507 writel(lradc->buffer_vchans,
508 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
510 for_each_set_bit(chan, iio->active_scan_mask, LRADC_MAX_TOTAL_CHANS) {
511 ctrl4_set |= chan << LRADC_CTRL4_LRADCSELECT_OFFSET(ofs);
512 ctrl4_clr |= LRADC_CTRL4_LRADCSELECT_MASK(ofs);
513 ctrl1_irq |= LRADC_CTRL1_LRADC_IRQ_EN(ofs);
514 writel(chan_value, adc->base + LRADC_CH(ofs));
515 bitmap_set(&enable, ofs, 1);
519 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
520 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
521 writel(ctrl4_clr, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_CLR);
522 writel(ctrl4_set, adc->base + LRADC_CTRL4 + STMP_OFFSET_REG_SET);
523 writel(ctrl1_irq, adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_SET);
524 writel(enable << LRADC_DELAY_TRIGGER_LRADCS_OFFSET,
525 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_SET);
530 static int mxs_lradc_adc_buffer_postdisable(struct iio_dev *iio)
532 struct mxs_lradc_adc *adc = iio_priv(iio);
533 struct mxs_lradc *lradc = adc->lradc;
535 writel(LRADC_DELAY_TRIGGER_LRADCS_MASK | LRADC_DELAY_KICK,
536 adc->base + LRADC_DELAY(0) + STMP_OFFSET_REG_CLR);
538 writel(lradc->buffer_vchans,
539 adc->base + LRADC_CTRL0 + STMP_OFFSET_REG_CLR);
540 if (lradc->soc == IMX28_LRADC)
541 writel(lradc->buffer_vchans << LRADC_CTRL1_LRADC_IRQ_EN_OFFSET,
542 adc->base + LRADC_CTRL1 + STMP_OFFSET_REG_CLR);
547 static bool mxs_lradc_adc_validate_scan_mask(struct iio_dev *iio,
548 const unsigned long *mask)
550 struct mxs_lradc_adc *adc = iio_priv(iio);
551 struct mxs_lradc *lradc = adc->lradc;
552 const int map_chans = bitmap_weight(mask, LRADC_MAX_TOTAL_CHANS);
554 unsigned long rsvd_mask = 0;
556 if (lradc->use_touchbutton)
557 rsvd_mask |= CHAN_MASK_TOUCHBUTTON;
558 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_4WIRE)
559 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_4WIRE;
560 if (lradc->touchscreen_wire == MXS_LRADC_TOUCHSCREEN_5WIRE)
561 rsvd_mask |= CHAN_MASK_TOUCHSCREEN_5WIRE;
563 if (lradc->use_touchbutton)
565 if (lradc->touchscreen_wire)
568 /* Test for attempts to map channels with special mode of operation. */
569 if (bitmap_intersects(mask, &rsvd_mask, LRADC_MAX_TOTAL_CHANS))
572 /* Test for attempts to map more channels then available slots. */
573 if (map_chans + rsvd_chans > LRADC_MAX_MAPPED_CHANS)
579 static const struct iio_buffer_setup_ops mxs_lradc_adc_buffer_ops = {
580 .preenable = &mxs_lradc_adc_buffer_preenable,
581 .postenable = &iio_triggered_buffer_postenable,
582 .predisable = &iio_triggered_buffer_predisable,
583 .postdisable = &mxs_lradc_adc_buffer_postdisable,
584 .validate_scan_mask = &mxs_lradc_adc_validate_scan_mask,
587 /* Driver initialization */
588 #define MXS_ADC_CHAN(idx, chan_type, name) { \
589 .type = (chan_type), \
591 .scan_index = (idx), \
592 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
593 BIT(IIO_CHAN_INFO_SCALE), \
598 .realbits = LRADC_RESOLUTION, \
601 .datasheet_name = (name), \
604 static const struct iio_chan_spec mx23_lradc_chan_spec[] = {
605 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
606 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
607 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
608 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
609 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
610 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
611 MXS_ADC_CHAN(6, IIO_VOLTAGE, "VDDIO"),
612 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
613 /* Combined Temperature sensors */
618 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
619 BIT(IIO_CHAN_INFO_OFFSET) |
620 BIT(IIO_CHAN_INFO_SCALE),
622 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
623 .datasheet_name = "TEMP_DIE",
625 /* Hidden channel to keep indexes */
632 MXS_ADC_CHAN(10, IIO_VOLTAGE, NULL),
633 MXS_ADC_CHAN(11, IIO_VOLTAGE, NULL),
634 MXS_ADC_CHAN(12, IIO_VOLTAGE, "USB_DP"),
635 MXS_ADC_CHAN(13, IIO_VOLTAGE, "USB_DN"),
636 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
637 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
640 static const struct iio_chan_spec mx28_lradc_chan_spec[] = {
641 MXS_ADC_CHAN(0, IIO_VOLTAGE, "LRADC0"),
642 MXS_ADC_CHAN(1, IIO_VOLTAGE, "LRADC1"),
643 MXS_ADC_CHAN(2, IIO_VOLTAGE, "LRADC2"),
644 MXS_ADC_CHAN(3, IIO_VOLTAGE, "LRADC3"),
645 MXS_ADC_CHAN(4, IIO_VOLTAGE, "LRADC4"),
646 MXS_ADC_CHAN(5, IIO_VOLTAGE, "LRADC5"),
647 MXS_ADC_CHAN(6, IIO_VOLTAGE, "LRADC6"),
648 MXS_ADC_CHAN(7, IIO_VOLTAGE, "VBATT"),
649 /* Combined Temperature sensors */
654 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
655 BIT(IIO_CHAN_INFO_OFFSET) |
656 BIT(IIO_CHAN_INFO_SCALE),
658 .scan_type = {.sign = 'u', .realbits = 18, .storagebits = 32,},
659 .datasheet_name = "TEMP_DIE",
661 /* Hidden channel to keep indexes */
668 MXS_ADC_CHAN(10, IIO_VOLTAGE, "VDDIO"),
669 MXS_ADC_CHAN(11, IIO_VOLTAGE, "VTH"),
670 MXS_ADC_CHAN(12, IIO_VOLTAGE, "VDDA"),
671 MXS_ADC_CHAN(13, IIO_VOLTAGE, "VDDD"),
672 MXS_ADC_CHAN(14, IIO_VOLTAGE, "VBG"),
673 MXS_ADC_CHAN(15, IIO_VOLTAGE, "VDD5V"),
676 static void mxs_lradc_adc_hw_init(struct mxs_lradc_adc *adc)
678 /* The ADC always uses DELAY CHANNEL 0. */
680 (1 << (LRADC_DELAY_TRIGGER_DELAYS_OFFSET + 0)) |
681 (LRADC_DELAY_TIMER_PER << LRADC_DELAY_DELAY_OFFSET);
683 /* Configure DELAY CHANNEL 0 for generic ADC sampling. */
684 writel(adc_cfg, adc->base + LRADC_DELAY(0));
687 * Start internal temperature sensing by clearing bit
688 * HW_LRADC_CTRL2_TEMPSENSE_PWD. This bit can be left cleared
691 writel(0, adc->base + LRADC_CTRL2);
694 static void mxs_lradc_adc_hw_stop(struct mxs_lradc_adc *adc)
696 writel(0, adc->base + LRADC_DELAY(0));
699 static int mxs_lradc_adc_probe(struct platform_device *pdev)
701 struct device *dev = &pdev->dev;
702 struct mxs_lradc *lradc = dev_get_drvdata(dev->parent);
703 struct mxs_lradc_adc *adc;
705 struct resource *iores;
706 int ret, irq, virq, i, s, n;
708 const char **irq_name;
710 /* Allocate the IIO device. */
711 iio = devm_iio_device_alloc(dev, sizeof(*adc));
713 dev_err(dev, "Failed to allocate IIO device\n");
721 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
725 adc->base = devm_ioremap(dev, iores->start, resource_size(iores));
729 init_completion(&adc->completion);
730 spin_lock_init(&adc->lock);
732 platform_set_drvdata(pdev, iio);
734 iio->name = pdev->name;
735 iio->dev.parent = dev;
736 iio->dev.of_node = dev->parent->of_node;
737 iio->info = &mxs_lradc_adc_iio_info;
738 iio->modes = INDIO_DIRECT_MODE;
739 iio->masklength = LRADC_MAX_TOTAL_CHANS;
741 if (lradc->soc == IMX23_LRADC) {
742 iio->channels = mx23_lradc_chan_spec;
743 iio->num_channels = ARRAY_SIZE(mx23_lradc_chan_spec);
744 irq_name = mx23_lradc_adc_irq_names;
745 n = ARRAY_SIZE(mx23_lradc_adc_irq_names);
747 iio->channels = mx28_lradc_chan_spec;
748 iio->num_channels = ARRAY_SIZE(mx28_lradc_chan_spec);
749 irq_name = mx28_lradc_adc_irq_names;
750 n = ARRAY_SIZE(mx28_lradc_adc_irq_names);
753 ret = stmp_reset_block(adc->base);
757 for (i = 0; i < n; i++) {
758 irq = platform_get_irq_byname(pdev, irq_name[i]);
762 virq = irq_of_parse_and_map(dev->parent->of_node, irq);
764 ret = devm_request_irq(dev, virq, mxs_lradc_adc_handle_irq,
765 0, irq_name[i], iio);
770 ret = mxs_lradc_adc_trigger_init(iio);
774 ret = iio_triggered_buffer_setup(iio, &iio_pollfunc_store_time,
775 &mxs_lradc_adc_trigger_handler,
776 &mxs_lradc_adc_buffer_ops);
780 adc->vref_mv = mxs_lradc_adc_vref_mv[lradc->soc];
782 /* Populate available ADC input ranges */
783 for (i = 0; i < LRADC_MAX_TOTAL_CHANS; i++) {
784 for (s = 0; s < ARRAY_SIZE(adc->scale_avail[i]); s++) {
786 * [s=0] = optional divider by two disabled (default)
787 * [s=1] = optional divider by two enabled
789 * The scale is calculated by doing:
790 * Vref >> (realbits - s)
791 * which multiplies by two on the second component
794 scale_uv = ((u64)adc->vref_mv[i] * 100000000) >>
795 (LRADC_RESOLUTION - s);
796 adc->scale_avail[i][s].nano =
797 do_div(scale_uv, 100000000) * 10;
798 adc->scale_avail[i][s].integer = scale_uv;
802 /* Configure the hardware. */
803 mxs_lradc_adc_hw_init(adc);
805 /* Register IIO device. */
806 ret = iio_device_register(iio);
808 dev_err(dev, "Failed to register IIO device\n");
815 mxs_lradc_adc_hw_stop(adc);
816 mxs_lradc_adc_trigger_remove(iio);
818 iio_triggered_buffer_cleanup(iio);
822 static int mxs_lradc_adc_remove(struct platform_device *pdev)
824 struct iio_dev *iio = platform_get_drvdata(pdev);
825 struct mxs_lradc_adc *adc = iio_priv(iio);
827 iio_device_unregister(iio);
828 mxs_lradc_adc_hw_stop(adc);
829 mxs_lradc_adc_trigger_remove(iio);
830 iio_triggered_buffer_cleanup(iio);
835 static struct platform_driver mxs_lradc_adc_driver = {
837 .name = "mxs-lradc-adc",
839 .probe = mxs_lradc_adc_probe,
840 .remove = mxs_lradc_adc_remove,
842 module_platform_driver(mxs_lradc_adc_driver);
844 MODULE_AUTHOR("Marek Vasut <marex@denx.de>");
845 MODULE_DESCRIPTION("Freescale MXS LRADC driver general purpose ADC driver");
846 MODULE_LICENSE("GPL");
847 MODULE_ALIAS("platform:mxs-lradc-adc");