2 * Copyright (c) 2016 MediaTek Inc.
3 * Author: Zhiyong Tao <zhiyong.tao@mediatek.com>
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
15 #include <linux/clk.h>
16 #include <linux/delay.h>
17 #include <linux/err.h>
18 #include <linux/kernel.h>
19 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/platform_device.h>
23 #include <linux/iopoll.h>
25 #include <linux/iio/iio.h>
27 /* Register definitions */
28 #define MT6577_AUXADC_CON0 0x00
29 #define MT6577_AUXADC_CON1 0x04
30 #define MT6577_AUXADC_CON2 0x10
31 #define MT6577_AUXADC_STA BIT(0)
33 #define MT6577_AUXADC_DAT0 0x14
34 #define MT6577_AUXADC_RDY0 BIT(12)
36 #define MT6577_AUXADC_MISC 0x94
37 #define MT6577_AUXADC_PDN_EN BIT(14)
39 #define MT6577_AUXADC_DAT_MASK 0xfff
40 #define MT6577_AUXADC_SLEEP_US 1000
41 #define MT6577_AUXADC_TIMEOUT_US 10000
42 #define MT6577_AUXADC_POWER_READY_MS 1
43 #define MT6577_AUXADC_SAMPLE_READY_US 25
45 struct mt6577_auxadc_device {
46 void __iomem *reg_base;
51 #define MT6577_AUXADC_CHANNEL(idx) { \
52 .type = IIO_VOLTAGE, \
55 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), \
58 static const struct iio_chan_spec mt6577_auxadc_iio_channels[] = {
59 MT6577_AUXADC_CHANNEL(0),
60 MT6577_AUXADC_CHANNEL(1),
61 MT6577_AUXADC_CHANNEL(2),
62 MT6577_AUXADC_CHANNEL(3),
63 MT6577_AUXADC_CHANNEL(4),
64 MT6577_AUXADC_CHANNEL(5),
65 MT6577_AUXADC_CHANNEL(6),
66 MT6577_AUXADC_CHANNEL(7),
67 MT6577_AUXADC_CHANNEL(8),
68 MT6577_AUXADC_CHANNEL(9),
69 MT6577_AUXADC_CHANNEL(10),
70 MT6577_AUXADC_CHANNEL(11),
71 MT6577_AUXADC_CHANNEL(12),
72 MT6577_AUXADC_CHANNEL(13),
73 MT6577_AUXADC_CHANNEL(14),
74 MT6577_AUXADC_CHANNEL(15),
77 static inline void mt6577_auxadc_mod_reg(void __iomem *reg,
78 u32 or_mask, u32 and_mask)
88 static int mt6577_auxadc_read(struct iio_dev *indio_dev,
89 struct iio_chan_spec const *chan)
92 void __iomem *reg_channel;
94 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
96 reg_channel = adc_dev->reg_base + MT6577_AUXADC_DAT0 +
99 mutex_lock(&adc_dev->lock);
101 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1,
102 0, 1 << chan->channel);
104 /* read channel and make sure old ready bit == 0 */
105 ret = readl_poll_timeout(reg_channel, val,
106 ((val & MT6577_AUXADC_RDY0) == 0),
107 MT6577_AUXADC_SLEEP_US,
108 MT6577_AUXADC_TIMEOUT_US);
110 dev_err(indio_dev->dev.parent,
111 "wait for channel[%d] ready bit clear time out\n",
116 /* set bit to trigger sample */
117 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_CON1,
118 1 << chan->channel, 0);
120 /* we must delay here for hardware sample channel data */
121 udelay(MT6577_AUXADC_SAMPLE_READY_US);
123 /* check MTK_AUXADC_CON2 if auxadc is idle */
124 ret = readl_poll_timeout(adc_dev->reg_base + MT6577_AUXADC_CON2, val,
125 ((val & MT6577_AUXADC_STA) == 0),
126 MT6577_AUXADC_SLEEP_US,
127 MT6577_AUXADC_TIMEOUT_US);
129 dev_err(indio_dev->dev.parent,
130 "wait for auxadc idle time out\n");
134 /* read channel and make sure ready bit == 1 */
135 ret = readl_poll_timeout(reg_channel, val,
136 ((val & MT6577_AUXADC_RDY0) != 0),
137 MT6577_AUXADC_SLEEP_US,
138 MT6577_AUXADC_TIMEOUT_US);
140 dev_err(indio_dev->dev.parent,
141 "wait for channel[%d] data ready time out\n",
147 val = readl(reg_channel) & MT6577_AUXADC_DAT_MASK;
149 mutex_unlock(&adc_dev->lock);
155 mutex_unlock(&adc_dev->lock);
160 static int mt6577_auxadc_read_raw(struct iio_dev *indio_dev,
161 struct iio_chan_spec const *chan,
167 case IIO_CHAN_INFO_PROCESSED:
168 *val = mt6577_auxadc_read(indio_dev, chan);
170 dev_err(indio_dev->dev.parent,
171 "failed to sample data on channel[%d]\n",
182 static const struct iio_info mt6577_auxadc_info = {
183 .driver_module = THIS_MODULE,
184 .read_raw = &mt6577_auxadc_read_raw,
187 static int __maybe_unused mt6577_auxadc_resume(struct device *dev)
189 struct iio_dev *indio_dev = dev_get_drvdata(dev);
190 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
193 ret = clk_prepare_enable(adc_dev->adc_clk);
195 pr_err("failed to enable auxadc clock\n");
199 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
200 MT6577_AUXADC_PDN_EN, 0);
201 mdelay(MT6577_AUXADC_POWER_READY_MS);
206 static int __maybe_unused mt6577_auxadc_suspend(struct device *dev)
208 struct iio_dev *indio_dev = dev_get_drvdata(dev);
209 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
211 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
212 0, MT6577_AUXADC_PDN_EN);
213 clk_disable_unprepare(adc_dev->adc_clk);
218 static int mt6577_auxadc_probe(struct platform_device *pdev)
220 struct mt6577_auxadc_device *adc_dev;
221 unsigned long adc_clk_rate;
222 struct resource *res;
223 struct iio_dev *indio_dev;
226 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc_dev));
230 adc_dev = iio_priv(indio_dev);
231 indio_dev->dev.parent = &pdev->dev;
232 indio_dev->name = dev_name(&pdev->dev);
233 indio_dev->info = &mt6577_auxadc_info;
234 indio_dev->modes = INDIO_DIRECT_MODE;
235 indio_dev->channels = mt6577_auxadc_iio_channels;
236 indio_dev->num_channels = ARRAY_SIZE(mt6577_auxadc_iio_channels);
238 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
239 adc_dev->reg_base = devm_ioremap_resource(&pdev->dev, res);
240 if (IS_ERR(adc_dev->reg_base)) {
241 dev_err(&pdev->dev, "failed to get auxadc base address\n");
242 return PTR_ERR(adc_dev->reg_base);
245 adc_dev->adc_clk = devm_clk_get(&pdev->dev, "main");
246 if (IS_ERR(adc_dev->adc_clk)) {
247 dev_err(&pdev->dev, "failed to get auxadc clock\n");
248 return PTR_ERR(adc_dev->adc_clk);
251 ret = clk_prepare_enable(adc_dev->adc_clk);
253 dev_err(&pdev->dev, "failed to enable auxadc clock\n");
257 adc_clk_rate = clk_get_rate(adc_dev->adc_clk);
260 dev_err(&pdev->dev, "null clock rate\n");
261 goto err_disable_clk;
264 mutex_init(&adc_dev->lock);
266 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
267 MT6577_AUXADC_PDN_EN, 0);
268 mdelay(MT6577_AUXADC_POWER_READY_MS);
270 platform_set_drvdata(pdev, indio_dev);
272 ret = iio_device_register(indio_dev);
274 dev_err(&pdev->dev, "failed to register iio device\n");
281 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
282 0, MT6577_AUXADC_PDN_EN);
284 clk_disable_unprepare(adc_dev->adc_clk);
288 static int mt6577_auxadc_remove(struct platform_device *pdev)
290 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
291 struct mt6577_auxadc_device *adc_dev = iio_priv(indio_dev);
293 iio_device_unregister(indio_dev);
295 mt6577_auxadc_mod_reg(adc_dev->reg_base + MT6577_AUXADC_MISC,
296 0, MT6577_AUXADC_PDN_EN);
298 clk_disable_unprepare(adc_dev->adc_clk);
303 static SIMPLE_DEV_PM_OPS(mt6577_auxadc_pm_ops,
304 mt6577_auxadc_suspend,
305 mt6577_auxadc_resume);
307 static const struct of_device_id mt6577_auxadc_of_match[] = {
308 { .compatible = "mediatek,mt2701-auxadc", },
309 { .compatible = "mediatek,mt7622-auxadc", },
310 { .compatible = "mediatek,mt8173-auxadc", },
313 MODULE_DEVICE_TABLE(of, mt6577_auxadc_of_match);
315 static struct platform_driver mt6577_auxadc_driver = {
317 .name = "mt6577-auxadc",
318 .of_match_table = mt6577_auxadc_of_match,
319 .pm = &mt6577_auxadc_pm_ops,
321 .probe = mt6577_auxadc_probe,
322 .remove = mt6577_auxadc_remove,
324 module_platform_driver(mt6577_auxadc_driver);
326 MODULE_AUTHOR("Zhiyong Tao <zhiyong.tao@mediatek.com>");
327 MODULE_DESCRIPTION("MTK AUXADC Device Driver");
328 MODULE_LICENSE("GPL v2");