drivers/iio/adc/meson_saradc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
   4  *
   5  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/iio/iio.h>
  14 #include <linux/module.h>
  15 #include <linux/nvmem-consumer.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/of.h>
  18 #include <linux/of_irq.h>
  19 #include <linux/of_device.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/mfd/syscon.h>
  24
  25 #define MESON_SAR_ADC_REG0                                      0x00
  26         #define MESON_SAR_ADC_REG0_PANEL_DETECT                 BIT(31)
  27         #define MESON_SAR_ADC_REG0_BUSY_MASK                    GENMASK(30, 28)
  28         #define MESON_SAR_ADC_REG0_DELTA_BUSY                   BIT(30)
  29         #define MESON_SAR_ADC_REG0_AVG_BUSY                     BIT(29)
  30         #define MESON_SAR_ADC_REG0_SAMPLE_BUSY                  BIT(28)
  31         #define MESON_SAR_ADC_REG0_FIFO_FULL                    BIT(27)
  32         #define MESON_SAR_ADC_REG0_FIFO_EMPTY                   BIT(26)
  33         #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK              GENMASK(25, 21)
  34         #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK           GENMASK(20, 19)
  35         #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK            GENMASK(18, 16)
  36         #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL             BIT(15)
  37         #define MESON_SAR_ADC_REG0_SAMPLING_STOP                BIT(14)
  38         #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK           GENMASK(13, 12)
  39         #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL               BIT(10)
  40         #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN                BIT(9)
  41         #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK            GENMASK(8, 4)
  42         #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN                  BIT(3)
  43         #define MESON_SAR_ADC_REG0_SAMPLING_START               BIT(2)
  44         #define MESON_SAR_ADC_REG0_CONTINUOUS_EN                BIT(1)
  45         #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE         BIT(0)
  46
  47 #define MESON_SAR_ADC_CHAN_LIST                                 0x04
  48         #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK          GENMASK(26, 24)
  49         #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan)       \
  50                                         (GENMASK(2, 0) << ((_chan) * 3))
  51
  52 #define MESON_SAR_ADC_AVG_CNTL                                  0x08
  53         #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan)    \
  54                                         (16 + ((_chan) * 2))
  55         #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan)     \
  56                                         (GENMASK(17, 16) << ((_chan) * 2))
  57         #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
  58                                         (0 + ((_chan) * 2))
  59         #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan)  \
  60                                         (GENMASK(1, 0) << ((_chan) * 2))
  61
  62 #define MESON_SAR_ADC_REG3                                      0x0c
  63         #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY              BIT(31)
  64         #define MESON_SAR_ADC_REG3_CLK_EN                       BIT(30)
  65         #define MESON_SAR_ADC_REG3_BL30_INITIALIZED             BIT(28)
  66         #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN    BIT(27)
  67         #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE    BIT(26)
  68         #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK      GENMASK(25, 23)
  69         #define MESON_SAR_ADC_REG3_DETECT_EN                    BIT(22)
  70         #define MESON_SAR_ADC_REG3_ADC_EN                       BIT(21)
  71         #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK      GENMASK(20, 18)
  72         #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK  GENMASK(17, 16)
  73         #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT            10
  74         #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH            5
  75         #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK           GENMASK(9, 8)
  76         #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK               GENMASK(7, 0)
  77
  78 #define MESON_SAR_ADC_DELAY                                     0x10
  79         #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK          GENMASK(25, 24)
  80         #define MESON_SAR_ADC_DELAY_BL30_BUSY                   BIT(15)
  81         #define MESON_SAR_ADC_DELAY_KERNEL_BUSY                 BIT(14)
  82         #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK          GENMASK(23, 16)
  83         #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK         GENMASK(9, 8)
  84         #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK         GENMASK(7, 0)
  85
  86 #define MESON_SAR_ADC_LAST_RD                                   0x14
  87         #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK        GENMASK(23, 16)
  88         #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK        GENMASK(9, 0)
  89
  90 #define MESON_SAR_ADC_FIFO_RD                                   0x18
  91         #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK              GENMASK(14, 12)
  92         #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK         GENMASK(11, 0)
  93
  94 #define MESON_SAR_ADC_AUX_SW                                    0x1c
  95         #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan)  \
  96                                         (8 + (((_chan) - 2) * 3))
  97         #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX                 BIT(6)
  98         #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX                 BIT(5)
  99         #define MESON_SAR_ADC_AUX_SW_MODE_SEL                   BIT(4)
 100         #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW                BIT(3)
 101         #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW                BIT(2)
 102         #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW                BIT(1)
 103         #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW                BIT(0)
 104
 105 #define MESON_SAR_ADC_CHAN_10_SW                                0x20
 106         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK     GENMASK(25, 23)
 107         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX       BIT(22)
 108         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX       BIT(21)
 109         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL         BIT(20)
 110         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW      BIT(19)
 111         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW      BIT(18)
 112         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW      BIT(17)
 113         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW      BIT(16)
 114         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK     GENMASK(9, 7)
 115         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX       BIT(6)
 116         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX       BIT(5)
 117         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL         BIT(4)
 118         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW      BIT(3)
 119         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW      BIT(2)
 120         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW      BIT(1)
 121         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW      BIT(0)
 122
 123 #define MESON_SAR_ADC_DETECT_IDLE_SW                            0x24
 124         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN       BIT(26)
 125         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK    GENMASK(25, 23)
 126         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX  BIT(22)
 127         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX  BIT(21)
 128         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL    BIT(20)
 129         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
 130         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
 131         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
 132         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
 133         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK  GENMASK(9, 7)
 134         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX    BIT(6)
 135         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX    BIT(5)
 136         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL      BIT(4)
 137         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW   BIT(3)
 138         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW   BIT(2)
 139         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW   BIT(1)
 140         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW   BIT(0)
 141
 142 #define MESON_SAR_ADC_DELTA_10                                  0x28
 143         #define MESON_SAR_ADC_DELTA_10_TEMP_SEL                 BIT(27)
 144         #define MESON_SAR_ADC_DELTA_10_TS_REVE1                 BIT(26)
 145         #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK   GENMASK(25, 16)
 146         #define MESON_SAR_ADC_DELTA_10_TS_REVE0                 BIT(15)
 147         #define MESON_SAR_ADC_DELTA_10_TS_C_MASK                GENMASK(14, 11)
 148         #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN                BIT(10)
 149         #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK   GENMASK(9, 0)
 150
 151 /*
 152  * NOTE: registers from here are undocumented (the vendor Linux kernel driver
 153  * and u-boot source served as reference). These only seem to be relevant on
 154  * GXBB and newer.
 155  */
 156 #define MESON_SAR_ADC_REG11                                     0x2c
 157         #define MESON_SAR_ADC_REG11_BANDGAP_EN                  BIT(13)
 158
 159 #define MESON_SAR_ADC_REG13                                     0x34
 160         #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK      GENMASK(13, 8)
 161
 162 #define MESON_SAR_ADC_MAX_FIFO_SIZE                             32
 163 #define MESON_SAR_ADC_TIMEOUT                                   100 /* ms */
 164 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL                  6
 165 #define MESON_SAR_ADC_TEMP_OFFSET                               27
 166
 167 /* temperature sensor calibration information in eFuse */
 168 #define MESON_SAR_ADC_EFUSE_BYTES                               4
 169 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL                 GENMASK(6, 0)
 170 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED                 BIT(7)
 171
 172 #define MESON_HHI_DPLL_TOP_0                                    0x318
 173 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4                           BIT(9)
 174
 175 /* for use with IIO_VAL_INT_PLUS_MICRO */
 176 #define MILLION                                                 1000000
 177
 178 #define MESON_SAR_ADC_CHAN(_chan) {                                     \
 179         .type = IIO_VOLTAGE,                                            \
 180         .indexed = 1,                                                   \
 181         .channel = _chan,                                               \
 182         .address = _chan,                                               \
 183         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 184                                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
 185         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),           \
 186         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) |       \
 187                                 BIT(IIO_CHAN_INFO_CALIBSCALE),          \
 188         .datasheet_name = "SAR_ADC_CH"#_chan,                           \
 189 }
 190
 191 #define MESON_SAR_ADC_TEMP_CHAN(_chan) {                                \
 192         .type = IIO_TEMP,                                               \
 193         .channel = _chan,                                               \
 194         .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL,              \
 195         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 196                                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
 197         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |         \
 198                                         BIT(IIO_CHAN_INFO_SCALE),       \
 199         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) |       \
 200                                 BIT(IIO_CHAN_INFO_CALIBSCALE),          \
 201         .datasheet_name = "TEMP_SENSOR",                                \
 202 }
 203
 204 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
 205         MESON_SAR_ADC_CHAN(0),
 206         MESON_SAR_ADC_CHAN(1),
 207         MESON_SAR_ADC_CHAN(2),
 208         MESON_SAR_ADC_CHAN(3),
 209         MESON_SAR_ADC_CHAN(4),
 210         MESON_SAR_ADC_CHAN(5),
 211         MESON_SAR_ADC_CHAN(6),
 212         MESON_SAR_ADC_CHAN(7),
 213         IIO_CHAN_SOFT_TIMESTAMP(8),
 214 };
 215
 216 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
 217         MESON_SAR_ADC_CHAN(0),
 218         MESON_SAR_ADC_CHAN(1),
 219         MESON_SAR_ADC_CHAN(2),
 220         MESON_SAR_ADC_CHAN(3),
 221         MESON_SAR_ADC_CHAN(4),
 222         MESON_SAR_ADC_CHAN(5),
 223         MESON_SAR_ADC_CHAN(6),
 224         MESON_SAR_ADC_CHAN(7),
 225         MESON_SAR_ADC_TEMP_CHAN(8),
 226         IIO_CHAN_SOFT_TIMESTAMP(9),
 227 };
 228
 229 enum meson_sar_adc_avg_mode {
 230         NO_AVERAGING = 0x0,
 231         MEAN_AVERAGING = 0x1,
 232         MEDIAN_AVERAGING = 0x2,
 233 };
 234
 235 enum meson_sar_adc_num_samples {
 236         ONE_SAMPLE = 0x0,
 237         TWO_SAMPLES = 0x1,
 238         FOUR_SAMPLES = 0x2,
 239         EIGHT_SAMPLES = 0x3,
 240 };
 241
 242 enum meson_sar_adc_chan7_mux_sel {
 243         CHAN7_MUX_VSS = 0x0,
 244         CHAN7_MUX_VDD_DIV4 = 0x1,
 245         CHAN7_MUX_VDD_DIV2 = 0x2,
 246         CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
 247         CHAN7_MUX_VDD = 0x4,
 248         CHAN7_MUX_CH7_INPUT = 0x7,
 249 };
 250
 251 struct meson_sar_adc_param {
 252         bool                                    has_bl30_integration;
 253         unsigned long                           clock_rate;
 254         u32                                     bandgap_reg;
 255         unsigned int                            resolution;
 256         const struct regmap_config              *regmap_config;
 257         u8                                      temperature_trimming_bits;
 258         unsigned int                            temperature_multiplier;
 259         unsigned int                            temperature_divider;
 260 };
 261
 262 struct meson_sar_adc_data {
 263         const struct meson_sar_adc_param        *param;
 264         const char                              *name;
 265 };
 266
 267 struct meson_sar_adc_priv {
 268         struct regmap                           *regmap;
 269         struct regulator                        *vref;
 270         const struct meson_sar_adc_param        *param;
 271         struct clk                              *clkin;
 272         struct clk                              *core_clk;
 273         struct clk                              *adc_sel_clk;
 274         struct clk                              *adc_clk;
 275         struct clk_gate                         clk_gate;
 276         struct clk                              *adc_div_clk;
 277         struct clk_divider                      clk_div;
 278         struct completion                       done;
 279         int                                     calibbias;
 280         int                                     calibscale;
 281         struct regmap                           *tsc_regmap;
 282         bool                                    temperature_sensor_calibrated;
 283         u8                                      temperature_sensor_coefficient;
 284         u16                                     temperature_sensor_adc_val;
 285 };
 286
 287 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
 288         .reg_bits = 8,
 289         .val_bits = 32,
 290         .reg_stride = 4,
 291         .max_register = MESON_SAR_ADC_REG13,
 292 };
 293
 294 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
 295         .reg_bits = 8,
 296         .val_bits = 32,
 297         .reg_stride = 4,
 298         .max_register = MESON_SAR_ADC_DELTA_10,
 299 };
 300
 301 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
 302 {
 303         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 304         u32 regval;
 305
 306         regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 307
 308         return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
 309 }
 310
 311 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
 312 {
 313         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 314         int tmp;
 315
 316         /* use val_calib = scale * val_raw + offset calibration function */
 317         tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
 318
 319         return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
 320 }
 321
 322 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
 323 {
 324         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 325         int regval, timeout = 10000;
 326
 327         /*
 328          * NOTE: we need a small delay before reading the status, otherwise
 329          * the sample engine may not have started internally (which would
 330          * seem to us that sampling is already finished).
 331          */
 332         do {
 333                 udelay(1);
 334                 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 335         } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
 336
 337         if (timeout < 0)
 338                 return -ETIMEDOUT;
 339
 340         return 0;
 341 }
 342
 343 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
 344                                          const struct iio_chan_spec *chan,
 345                                          int *val)
 346 {
 347         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 348         int regval, fifo_chan, fifo_val, count;
 349
 350         if(!wait_for_completion_timeout(&priv->done,
 351                                 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
 352                 return -ETIMEDOUT;
 353
 354         count = meson_sar_adc_get_fifo_count(indio_dev);
 355         if (count != 1) {
 356                 dev_err(&indio_dev->dev,
 357                         "ADC FIFO has %d element(s) instead of one\n", count);
 358                 return -EINVAL;
 359         }
 360
 361         regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
 362         fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
 363         if (fifo_chan != chan->address) {
 364                 dev_err(&indio_dev->dev,
 365                         "ADC FIFO entry belongs to channel %d instead of %lu\n",
 366                         fifo_chan, chan->address);
 367                 return -EINVAL;
 368         }
 369
 370         fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
 371         fifo_val &= GENMASK(priv->param->resolution - 1, 0);
 372         *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
 373
 374         return 0;
 375 }
 376
 377 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
 378                                         const struct iio_chan_spec *chan,
 379                                         enum meson_sar_adc_avg_mode mode,
 380                                         enum meson_sar_adc_num_samples samples)
 381 {
 382         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 383         int val, address = chan->address;
 384
 385         val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
 386         regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
 387                            MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
 388                            val);
 389
 390         val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
 391         regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
 392                            MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
 393 }
 394
 395 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
 396                                         const struct iio_chan_spec *chan)
 397 {
 398         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 399         u32 regval;
 400
 401         /*
 402          * the SAR ADC engine allows sampling multiple channels at the same
 403          * time. to keep it simple we're only working with one *internal*
 404          * channel, which starts counting at index 0 (which means: count = 1).
 405          */
 406         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
 407         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
 408                            MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
 409
 410         /* map channel index 0 to the channel which we want to read */
 411         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
 412                             chan->address);
 413         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
 414                            MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
 415
 416         regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
 417                             chan->address);
 418         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
 419                            MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
 420                            regval);
 421
 422         regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
 423                             chan->address);
 424         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
 425                            MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
 426                            regval);
 427
 428         if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
 429                 if (chan->type == IIO_TEMP)
 430                         regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
 431                 else
 432                         regval = 0;
 433
 434                 regmap_update_bits(priv->regmap,
 435                                    MESON_SAR_ADC_DELTA_10,
 436                                    MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
 437         }
 438 }
 439
 440 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
 441                                         enum meson_sar_adc_chan7_mux_sel sel)
 442 {
 443         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 444         u32 regval;
 445
 446         regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
 447         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 448                            MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
 449
 450         usleep_range(10, 20);
 451 }
 452
 453 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
 454 {
 455         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 456
 457         reinit_completion(&priv->done);
 458
 459         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 460                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
 461                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
 462
 463         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 464                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
 465                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
 466
 467         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 468                            MESON_SAR_ADC_REG0_SAMPLING_START,
 469                            MESON_SAR_ADC_REG0_SAMPLING_START);
 470 }
 471
 472 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
 473 {
 474         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 475
 476         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 477                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
 478
 479         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 480                            MESON_SAR_ADC_REG0_SAMPLING_STOP,
 481                            MESON_SAR_ADC_REG0_SAMPLING_STOP);
 482
 483         /* wait until all modules are stopped */
 484         meson_sar_adc_wait_busy_clear(indio_dev);
 485
 486         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 487                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
 488 }
 489
 490 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
 491 {
 492         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 493         int val, timeout = 10000;
 494
 495         mutex_lock(&indio_dev->mlock);
 496
 497         if (priv->param->has_bl30_integration) {
 498                 /* prevent BL30 from using the SAR ADC while we are using it */
 499                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 500                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
 501                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
 502
 503                 /*
 504                  * wait until BL30 releases it's lock (so we can use the SAR
 505                  * ADC)
 506                  */
 507                 do {
 508                         udelay(1);
 509                         regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
 510                 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
 511
 512                 if (timeout < 0) {
 513                         mutex_unlock(&indio_dev->mlock);
 514                         return -ETIMEDOUT;
 515                 }
 516         }
 517
 518         return 0;
 519 }
 520
 521 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
 522 {
 523         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 524
 525         if (priv->param->has_bl30_integration)
 526                 /* allow BL30 to use the SAR ADC again */
 527                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 528                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
 529
 530         mutex_unlock(&indio_dev->mlock);
 531 }
 532
 533 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
 534 {
 535         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 536         unsigned int count, tmp;
 537
 538         for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
 539                 if (!meson_sar_adc_get_fifo_count(indio_dev))
 540                         break;
 541
 542                 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
 543         }
 544 }
 545
 546 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
 547                                     const struct iio_chan_spec *chan,
 548                                     enum meson_sar_adc_avg_mode avg_mode,
 549                                     enum meson_sar_adc_num_samples avg_samples,
 550                                     int *val)
 551 {
 552         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 553         int ret;
 554
 555         if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
 556                 return -ENOTSUPP;
 557
 558         ret = meson_sar_adc_lock(indio_dev);
 559         if (ret)
 560                 return ret;
 561
 562         /* clear the FIFO to make sure we're not reading old values */
 563         meson_sar_adc_clear_fifo(indio_dev);
 564
 565         meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
 566
 567         meson_sar_adc_enable_channel(indio_dev, chan);
 568
 569         meson_sar_adc_start_sample_engine(indio_dev);
 570         ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
 571         meson_sar_adc_stop_sample_engine(indio_dev);
 572
 573         meson_sar_adc_unlock(indio_dev);
 574
 575         if (ret) {
 576                 dev_warn(indio_dev->dev.parent,
 577                          "failed to read sample for channel %lu: %d\n",
 578                          chan->address, ret);
 579                 return ret;
 580         }
 581
 582         return IIO_VAL_INT;
 583 }
 584
 585 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
 586                                            const struct iio_chan_spec *chan,
 587                                            int *val, int *val2, long mask)
 588 {
 589         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 590         int ret;
 591
 592         switch (mask) {
 593         case IIO_CHAN_INFO_RAW:
 594                 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
 595                                                 ONE_SAMPLE, val);
 596                 break;
 597
 598         case IIO_CHAN_INFO_AVERAGE_RAW:
 599                 return meson_sar_adc_get_sample(indio_dev, chan,
 600                                                 MEAN_AVERAGING, EIGHT_SAMPLES,
 601                                                 val);
 602                 break;
 603
 604         case IIO_CHAN_INFO_SCALE:
 605                 if (chan->type == IIO_VOLTAGE) {
 606                         ret = regulator_get_voltage(priv->vref);
 607                         if (ret < 0) {
 608                                 dev_err(indio_dev->dev.parent,
 609                                         "failed to get vref voltage: %d\n",
 610                                         ret);
 611                                 return ret;
 612                         }
 613
 614                         *val = ret / 1000;
 615                         *val2 = priv->param->resolution;
 616                         return IIO_VAL_FRACTIONAL_LOG2;
 617                 } else if (chan->type == IIO_TEMP) {
 618                         /* SoC specific multiplier and divider */
 619                         *val = priv->param->temperature_multiplier;
 620                         *val2 = priv->param->temperature_divider;
 621
 622                         /* celsius to millicelsius */
 623                         *val *= 1000;
 624
 625                         return IIO_VAL_FRACTIONAL;
 626                 } else {
 627                         return -EINVAL;
 628                 }
 629
 630         case IIO_CHAN_INFO_CALIBBIAS:
 631                 *val = priv->calibbias;
 632                 return IIO_VAL_INT;
 633
 634         case IIO_CHAN_INFO_CALIBSCALE:
 635                 *val = priv->calibscale / MILLION;
 636                 *val2 = priv->calibscale % MILLION;
 637                 return IIO_VAL_INT_PLUS_MICRO;
 638
 639         case IIO_CHAN_INFO_OFFSET:
 640                 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
 641                                          priv->param->temperature_divider,
 642                                          priv->param->temperature_multiplier);
 643                 *val -= priv->temperature_sensor_adc_val;
 644                 return IIO_VAL_INT;
 645
 646         default:
 647                 return -EINVAL;
 648         }
 649 }
 650
 651 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
 652                                   void __iomem *base)
 653 {
 654         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 655         struct clk_init_data init;
 656         const char *clk_parents[1];
 657
 658         init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
 659                                    dev_name(indio_dev->dev.parent));
 660         if (!init.name)
 661                 return -ENOMEM;
 662
 663         init.flags = 0;
 664         init.ops = &clk_divider_ops;
 665         clk_parents[0] = __clk_get_name(priv->clkin);
 666         init.parent_names = clk_parents;
 667         init.num_parents = 1;
 668
 669         priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
 670         priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
 671         priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
 672         priv->clk_div.hw.init = &init;
 673         priv->clk_div.flags = 0;
 674
 675         priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
 676                                               &priv->clk_div.hw);
 677         if (WARN_ON(IS_ERR(priv->adc_div_clk)))
 678                 return PTR_ERR(priv->adc_div_clk);
 679
 680         init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
 681                                    dev_name(indio_dev->dev.parent));
 682         if (!init.name)
 683                 return -ENOMEM;
 684
 685         init.flags = CLK_SET_RATE_PARENT;
 686         init.ops = &clk_gate_ops;
 687         clk_parents[0] = __clk_get_name(priv->adc_div_clk);
 688         init.parent_names = clk_parents;
 689         init.num_parents = 1;
 690
 691         priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
 692         priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
 693         priv->clk_gate.hw.init = &init;
 694
 695         priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
 696         if (WARN_ON(IS_ERR(priv->adc_clk)))
 697                 return PTR_ERR(priv->adc_clk);
 698
 699         return 0;
 700 }
 701
 702 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
 703 {
 704         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 705         u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
 706         struct nvmem_cell *temperature_calib;
 707         size_t read_len;
 708         int ret;
 709
 710         temperature_calib = devm_nvmem_cell_get(indio_dev->dev.parent,
 711                                                 "temperature_calib");
 712         if (IS_ERR(temperature_calib)) {
 713                 ret = PTR_ERR(temperature_calib);
 714
 715                 /*
 716                  * leave the temperature sensor disabled if no calibration data
 717                  * was passed via nvmem-cells.
 718                  */
 719                 if (ret == -ENODEV)
 720                         return 0;
 721
 722                 return dev_err_probe(indio_dev->dev.parent, ret,
 723                                      "failed to get temperature_calib cell\n");
 724         }
 725
 726         priv->tsc_regmap =
 727                 syscon_regmap_lookup_by_phandle(indio_dev->dev.parent->of_node,
 728                                                 "amlogic,hhi-sysctrl");
 729         if (IS_ERR(priv->tsc_regmap)) {
 730                 dev_err(indio_dev->dev.parent,
 731                         "failed to get amlogic,hhi-sysctrl regmap\n");
 732                 return PTR_ERR(priv->tsc_regmap);
 733         }
 734
 735         read_len = MESON_SAR_ADC_EFUSE_BYTES;
 736         buf = nvmem_cell_read(temperature_calib, &read_len);
 737         if (IS_ERR(buf)) {
 738                 dev_err(indio_dev->dev.parent,
 739                         "failed to read temperature_calib cell\n");
 740                 return PTR_ERR(buf);
 741         } else if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
 742                 kfree(buf);
 743                 dev_err(indio_dev->dev.parent,
 744                         "invalid read size of temperature_calib cell\n");
 745                 return -EINVAL;
 746         }
 747
 748         trimming_bits = priv->param->temperature_trimming_bits;
 749         trimming_mask = BIT(trimming_bits) - 1;
 750
 751         priv->temperature_sensor_calibrated =
 752                 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
 753         priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
 754
 755         upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
 756                                   buf[3]);
 757
 758         priv->temperature_sensor_adc_val = buf[2];
 759         priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
 760         priv->temperature_sensor_adc_val >>= trimming_bits;
 761
 762         kfree(buf);
 763
 764         return 0;
 765 }
 766
 767 static int meson_sar_adc_init(struct iio_dev *indio_dev)
 768 {
 769         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 770         int regval, i, ret;
 771
 772         /*
 773          * make sure we start at CH7 input since the other muxes are only used
 774          * for internal calibration.
 775          */
 776         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
 777
 778         if (priv->param->has_bl30_integration) {
 779                 /*
 780                  * leave sampling delay and the input clocks as configured by
 781                  * BL30 to make sure BL30 gets the values it expects when
 782                  * reading the temperature sensor.
 783                  */
 784                 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
 785                 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
 786                         return 0;
 787         }
 788
 789         meson_sar_adc_stop_sample_engine(indio_dev);
 790
 791         /*
 792          * disable this bit as seems to be only relevant for Meson6 (based
 793          * on the vendor driver), which we don't support at the moment.
 794          */
 795         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 796                         MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
 797
 798         /* disable all channels by default */
 799         regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
 800
 801         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 802                            MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
 803         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 804                            MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
 805                            MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
 806
 807         /* delay between two samples = (10+1) * 1uS */
 808         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 809                            MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 810                            FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
 811                                       10));
 812         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 813                            MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
 814                            FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
 815                                       0));
 816
 817         /* delay between two samples = (10+1) * 1uS */
 818         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 819                            MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 820                            FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 821                                       10));
 822         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 823                            MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
 824                            FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
 825                                       1));
 826
 827         /*
 828          * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
 829          * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
 830          */
 831         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
 832         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 833                            MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
 834                            regval);
 835         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
 836         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 837                            MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
 838                            regval);
 839
 840         /*
 841          * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
 842          * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
 843          * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
 844          * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
 845          */
 846         regval = 0;
 847         for (i = 2; i <= 7; i++)
 848                 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
 849         regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
 850         regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
 851         regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
 852
 853         if (priv->temperature_sensor_calibrated) {
 854                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 855                                    MESON_SAR_ADC_DELTA_10_TS_REVE1,
 856                                    MESON_SAR_ADC_DELTA_10_TS_REVE1);
 857                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 858                                    MESON_SAR_ADC_DELTA_10_TS_REVE0,
 859                                    MESON_SAR_ADC_DELTA_10_TS_REVE0);
 860
 861                 /*
 862                  * set bits [3:0] of the TSC (temperature sensor coefficient)
 863                  * to get the correct values when reading the temperature.
 864                  */
 865                 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
 866                                     priv->temperature_sensor_coefficient);
 867                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 868                                    MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
 869
 870                 if (priv->param->temperature_trimming_bits == 5) {
 871                         if (priv->temperature_sensor_coefficient & BIT(4))
 872                                 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
 873                         else
 874                                 regval = 0;
 875
 876                         /*
 877                          * bit [4] (the 5th bit when starting to count at 1)
 878                          * of the TSC is located in the HHI register area.
 879                          */
 880                         regmap_update_bits(priv->tsc_regmap,
 881                                            MESON_HHI_DPLL_TOP_0,
 882                                            MESON_HHI_DPLL_TOP_0_TSC_BIT4,
 883                                            regval);
 884                 }
 885         } else {
 886                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 887                                    MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
 888                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 889                                    MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
 890         }
 891
 892         ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
 893         if (ret) {
 894                 dev_err(indio_dev->dev.parent,
 895                         "failed to set adc parent to clkin\n");
 896                 return ret;
 897         }
 898
 899         ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
 900         if (ret) {
 901                 dev_err(indio_dev->dev.parent,
 902                         "failed to set adc clock rate\n");
 903                 return ret;
 904         }
 905
 906         return 0;
 907 }
 908
 909 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
 910 {
 911         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 912         const struct meson_sar_adc_param *param = priv->param;
 913         u32 enable_mask;
 914
 915         if (param->bandgap_reg == MESON_SAR_ADC_REG11)
 916                 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
 917         else
 918                 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
 919
 920         regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
 921                            on_off ? enable_mask : 0);
 922 }
 923
 924 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
 925 {
 926         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 927         int ret;
 928         u32 regval;
 929
 930         ret = meson_sar_adc_lock(indio_dev);
 931         if (ret)
 932                 goto err_lock;
 933
 934         ret = regulator_enable(priv->vref);
 935         if (ret < 0) {
 936                 dev_err(indio_dev->dev.parent,
 937                         "failed to enable vref regulator\n");
 938                 goto err_vref;
 939         }
 940
 941         ret = clk_prepare_enable(priv->core_clk);
 942         if (ret) {
 943                 dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
 944                 goto err_core_clk;
 945         }
 946
 947         regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
 948         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 949                            MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
 950
 951         meson_sar_adc_set_bandgap(indio_dev, true);
 952
 953         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 954                            MESON_SAR_ADC_REG3_ADC_EN,
 955                            MESON_SAR_ADC_REG3_ADC_EN);
 956
 957         udelay(5);
 958
 959         ret = clk_prepare_enable(priv->adc_clk);
 960         if (ret) {
 961                 dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
 962                 goto err_adc_clk;
 963         }
 964
 965         meson_sar_adc_unlock(indio_dev);
 966
 967         return 0;
 968
 969 err_adc_clk:
 970         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 971                            MESON_SAR_ADC_REG3_ADC_EN, 0);
 972         meson_sar_adc_set_bandgap(indio_dev, false);
 973         clk_disable_unprepare(priv->core_clk);
 974 err_core_clk:
 975         regulator_disable(priv->vref);
 976 err_vref:
 977         meson_sar_adc_unlock(indio_dev);
 978 err_lock:
 979         return ret;
 980 }
 981
 982 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
 983 {
 984         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 985         int ret;
 986
 987         ret = meson_sar_adc_lock(indio_dev);
 988         if (ret)
 989                 return ret;
 990
 991         clk_disable_unprepare(priv->adc_clk);
 992
 993         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 994                            MESON_SAR_ADC_REG3_ADC_EN, 0);
 995
 996         meson_sar_adc_set_bandgap(indio_dev, false);
 997
 998         clk_disable_unprepare(priv->core_clk);
 999
1000         regulator_disable(priv->vref);
1001
1002         meson_sar_adc_unlock(indio_dev);
1003
1004         return 0;
1005 }
1006
1007 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
1008 {
1009         struct iio_dev *indio_dev = data;
1010         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1011         unsigned int cnt, threshold;
1012         u32 regval;
1013
1014         regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
1015         cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
1016         threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
1017
1018         if (cnt < threshold)
1019                 return IRQ_NONE;
1020
1021         complete(&priv->done);
1022
1023         return IRQ_HANDLED;
1024 }
1025
1026 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
1027 {
1028         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1029         int ret, nominal0, nominal1, value0, value1;
1030
1031         /* use points 25% and 75% for calibration */
1032         nominal0 = (1 << priv->param->resolution) / 4;
1033         nominal1 = (1 << priv->param->resolution) * 3 / 4;
1034
1035         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
1036         usleep_range(10, 20);
1037         ret = meson_sar_adc_get_sample(indio_dev,
1038                                        &indio_dev->channels[7],
1039                                        MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
1040         if (ret < 0)
1041                 goto out;
1042
1043         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
1044         usleep_range(10, 20);
1045         ret = meson_sar_adc_get_sample(indio_dev,
1046                                        &indio_dev->channels[7],
1047                                        MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
1048         if (ret < 0)
1049                 goto out;
1050
1051         if (value1 <= value0) {
1052                 ret = -EINVAL;
1053                 goto out;
1054         }
1055
1056         priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
1057                                    value1 - value0);
1058         priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
1059                                              MILLION);
1060         ret = 0;
1061 out:
1062         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
1063
1064         return ret;
1065 }
1066
1067 static const struct iio_info meson_sar_adc_iio_info = {
1068         .read_raw = meson_sar_adc_iio_info_read_raw,
1069 };
1070
1071 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
1072         .has_bl30_integration = false,
1073         .clock_rate = 1150000,
1074         .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1075         .regmap_config = &meson_sar_adc_regmap_config_meson8,
1076         .resolution = 10,
1077         .temperature_trimming_bits = 4,
1078         .temperature_multiplier = 18 * 10000,
1079         .temperature_divider = 1024 * 10 * 85,
1080 };
1081
1082 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
1083         .has_bl30_integration = false,
1084         .clock_rate = 1150000,
1085         .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1086         .regmap_config = &meson_sar_adc_regmap_config_meson8,
1087         .resolution = 10,
1088         .temperature_trimming_bits = 5,
1089         .temperature_multiplier = 10,
1090         .temperature_divider = 32,
1091 };
1092
1093 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
1094         .has_bl30_integration = true,
1095         .clock_rate = 1200000,
1096         .bandgap_reg = MESON_SAR_ADC_REG11,
1097         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1098         .resolution = 10,
1099 };
1100
1101 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
1102         .has_bl30_integration = true,
1103         .clock_rate = 1200000,
1104         .bandgap_reg = MESON_SAR_ADC_REG11,
1105         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1106         .resolution = 12,
1107 };
1108
1109 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
1110         .param = &meson_sar_adc_meson8_param,
1111         .name = "meson-meson8-saradc",
1112 };
1113
1114 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
1115         .param = &meson_sar_adc_meson8b_param,
1116         .name = "meson-meson8b-saradc",
1117 };
1118
1119 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
1120         .param = &meson_sar_adc_meson8b_param,
1121         .name = "meson-meson8m2-saradc",
1122 };
1123
1124 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
1125         .param = &meson_sar_adc_gxbb_param,
1126         .name = "meson-gxbb-saradc",
1127 };
1128
1129 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
1130         .param = &meson_sar_adc_gxl_param,
1131         .name = "meson-gxl-saradc",
1132 };
1133
1134 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
1135         .param = &meson_sar_adc_gxl_param,
1136         .name = "meson-gxm-saradc",
1137 };
1138
1139 static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
1140         .param = &meson_sar_adc_gxl_param,
1141         .name = "meson-axg-saradc",
1142 };
1143
1144 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
1145         .param = &meson_sar_adc_gxl_param,
1146         .name = "meson-g12a-saradc",
1147 };
1148
1149 static const struct of_device_id meson_sar_adc_of_match[] = {
1150         {
1151                 .compatible = "amlogic,meson8-saradc",
1152                 .data = &meson_sar_adc_meson8_data,
1153         }, {
1154                 .compatible = "amlogic,meson8b-saradc",
1155                 .data = &meson_sar_adc_meson8b_data,
1156         }, {
1157                 .compatible = "amlogic,meson8m2-saradc",
1158                 .data = &meson_sar_adc_meson8m2_data,
1159         }, {
1160                 .compatible = "amlogic,meson-gxbb-saradc",
1161                 .data = &meson_sar_adc_gxbb_data,
1162         }, {
1163                 .compatible = "amlogic,meson-gxl-saradc",
1164                 .data = &meson_sar_adc_gxl_data,
1165         }, {
1166                 .compatible = "amlogic,meson-gxm-saradc",
1167                 .data = &meson_sar_adc_gxm_data,
1168         }, {
1169                 .compatible = "amlogic,meson-axg-saradc",
1170                 .data = &meson_sar_adc_axg_data,
1171         }, {
1172                 .compatible = "amlogic,meson-g12a-saradc",
1173                 .data = &meson_sar_adc_g12a_data,
1174         },
1175         { /* sentinel */ }
1176 };
1177 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
1178
1179 static int meson_sar_adc_probe(struct platform_device *pdev)
1180 {
1181         const struct meson_sar_adc_data *match_data;
1182         struct meson_sar_adc_priv *priv;
1183         struct iio_dev *indio_dev;
1184         void __iomem *base;
1185         int irq, ret;
1186
1187         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
1188         if (!indio_dev) {
1189                 dev_err(&pdev->dev, "failed allocating iio device\n");
1190                 return -ENOMEM;
1191         }
1192
1193         priv = iio_priv(indio_dev);
1194         init_completion(&priv->done);
1195
1196         match_data = of_device_get_match_data(&pdev->dev);
1197         if (!match_data) {
1198                 dev_err(&pdev->dev, "failed to get match data\n");
1199                 return -ENODEV;
1200         }
1201
1202         priv->param = match_data->param;
1203
1204         indio_dev->name = match_data->name;
1205         indio_dev->modes = INDIO_DIRECT_MODE;
1206         indio_dev->info = &meson_sar_adc_iio_info;
1207
1208         base = devm_platform_ioremap_resource(pdev, 0);
1209         if (IS_ERR(base))
1210                 return PTR_ERR(base);
1211
1212         priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
1213                                              priv->param->regmap_config);
1214         if (IS_ERR(priv->regmap))
1215                 return PTR_ERR(priv->regmap);
1216
1217         irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1218         if (!irq)
1219                 return -EINVAL;
1220
1221         ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED,
1222                                dev_name(&pdev->dev), indio_dev);
1223         if (ret)
1224                 return ret;
1225
1226         priv->clkin = devm_clk_get(&pdev->dev, "clkin");
1227         if (IS_ERR(priv->clkin)) {
1228                 dev_err(&pdev->dev, "failed to get clkin\n");
1229                 return PTR_ERR(priv->clkin);
1230         }
1231
1232         priv->core_clk = devm_clk_get(&pdev->dev, "core");
1233         if (IS_ERR(priv->core_clk)) {
1234                 dev_err(&pdev->dev, "failed to get core clk\n");
1235                 return PTR_ERR(priv->core_clk);
1236         }
1237
1238         priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
1239         if (IS_ERR(priv->adc_clk)) {
1240                 if (PTR_ERR(priv->adc_clk) == -ENOENT) {
1241                         priv->adc_clk = NULL;
1242                 } else {
1243                         dev_err(&pdev->dev, "failed to get adc clk\n");
1244                         return PTR_ERR(priv->adc_clk);
1245                 }
1246         }
1247
1248         priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
1249         if (IS_ERR(priv->adc_sel_clk)) {
1250                 if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
1251                         priv->adc_sel_clk = NULL;
1252                 } else {
1253                         dev_err(&pdev->dev, "failed to get adc_sel clk\n");
1254                         return PTR_ERR(priv->adc_sel_clk);
1255                 }
1256         }
1257
1258         /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1259         if (!priv->adc_clk) {
1260                 ret = meson_sar_adc_clk_init(indio_dev, base);
1261                 if (ret)
1262                         return ret;
1263         }
1264
1265         priv->vref = devm_regulator_get(&pdev->dev, "vref");
1266         if (IS_ERR(priv->vref)) {
1267                 dev_err(&pdev->dev, "failed to get vref regulator\n");
1268                 return PTR_ERR(priv->vref);
1269         }
1270
1271         priv->calibscale = MILLION;
1272
1273         if (priv->param->temperature_trimming_bits) {
1274                 ret = meson_sar_adc_temp_sensor_init(indio_dev);
1275                 if (ret)
1276                         return ret;
1277         }
1278
1279         if (priv->temperature_sensor_calibrated) {
1280                 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
1281                 indio_dev->num_channels =
1282                         ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
1283         } else {
1284                 indio_dev->channels = meson_sar_adc_iio_channels;
1285                 indio_dev->num_channels =
1286                         ARRAY_SIZE(meson_sar_adc_iio_channels);
1287         }
1288
1289         ret = meson_sar_adc_init(indio_dev);
1290         if (ret)
1291                 goto err;
1292
1293         ret = meson_sar_adc_hw_enable(indio_dev);
1294         if (ret)
1295                 goto err;
1296
1297         ret = meson_sar_adc_calib(indio_dev);
1298         if (ret)
1299                 dev_warn(&pdev->dev, "calibration failed\n");
1300
1301         platform_set_drvdata(pdev, indio_dev);
1302
1303         ret = iio_device_register(indio_dev);
1304         if (ret)
1305                 goto err_hw;
1306
1307         return 0;
1308
1309 err_hw:
1310         meson_sar_adc_hw_disable(indio_dev);
1311 err:
1312         return ret;
1313 }
1314
1315 static int meson_sar_adc_remove(struct platform_device *pdev)
1316 {
1317         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1318
1319         iio_device_unregister(indio_dev);
1320
1321         return meson_sar_adc_hw_disable(indio_dev);
1322 }
1323
1324 static int __maybe_unused meson_sar_adc_suspend(struct device *dev)
1325 {
1326         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1327
1328         return meson_sar_adc_hw_disable(indio_dev);
1329 }
1330
1331 static int __maybe_unused meson_sar_adc_resume(struct device *dev)
1332 {
1333         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1334
1335         return meson_sar_adc_hw_enable(indio_dev);
1336 }
1337
1338 static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1339                          meson_sar_adc_suspend, meson_sar_adc_resume);
1340
1341 static struct platform_driver meson_sar_adc_driver = {
1342         .probe          = meson_sar_adc_probe,
1343         .remove         = meson_sar_adc_remove,
1344         .driver         = {
1345                 .name   = "meson-saradc",
1346                 .of_match_table = meson_sar_adc_of_match,
1347                 .pm = &meson_sar_adc_pm_ops,
1348         },
1349 };
1350
1351 module_platform_driver(meson_sar_adc_driver);
1352
1353 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1354 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1355 MODULE_LICENSE("GPL v2");