drivers/iio/adc/meson_saradc.c

   1 /*
   2  * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
   3  *
   4  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * You should have received a copy of the GNU General Public License
  11  * along with this program. If not, see <http://www.gnu.org/licenses/>.
  12  */
  13
  14 #include <linux/bitfield.h>
  15 #include <linux/clk.h>
  16 #include <linux/clk-provider.h>
  17 #include <linux/delay.h>
  18 #include <linux/io.h>
  19 #include <linux/iio/iio.h>
  20 #include <linux/module.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/of.h>
  23 #include <linux/of_irq.h>
  24 #include <linux/of_device.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/regmap.h>
  27 #include <linux/regulator/consumer.h>
  28
  29 #define MESON_SAR_ADC_REG0                                      0x00
  30         #define MESON_SAR_ADC_REG0_PANEL_DETECT                 BIT(31)
  31         #define MESON_SAR_ADC_REG0_BUSY_MASK                    GENMASK(30, 28)
  32         #define MESON_SAR_ADC_REG0_DELTA_BUSY                   BIT(30)
  33         #define MESON_SAR_ADC_REG0_AVG_BUSY                     BIT(29)
  34         #define MESON_SAR_ADC_REG0_SAMPLE_BUSY                  BIT(28)
  35         #define MESON_SAR_ADC_REG0_FIFO_FULL                    BIT(27)
  36         #define MESON_SAR_ADC_REG0_FIFO_EMPTY                   BIT(26)
  37         #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK              GENMASK(25, 21)
  38         #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK           GENMASK(20, 19)
  39         #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK            GENMASK(18, 16)
  40         #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL             BIT(15)
  41         #define MESON_SAR_ADC_REG0_SAMPLING_STOP                BIT(14)
  42         #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK           GENMASK(13, 12)
  43         #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL               BIT(10)
  44         #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN                BIT(9)
  45         #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK            GENMASK(8, 4)
  46         #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN                  BIT(3)
  47         #define MESON_SAR_ADC_REG0_SAMPLING_START               BIT(2)
  48         #define MESON_SAR_ADC_REG0_CONTINUOUS_EN                BIT(1)
  49         #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE         BIT(0)
  50
  51 #define MESON_SAR_ADC_CHAN_LIST                                 0x04
  52         #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK          GENMASK(26, 24)
  53         #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan)       \
  54                                         (GENMASK(2, 0) << ((_chan) * 3))
  55
  56 #define MESON_SAR_ADC_AVG_CNTL                                  0x08
  57         #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan)    \
  58                                         (16 + ((_chan) * 2))
  59         #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan)     \
  60                                         (GENMASK(17, 16) << ((_chan) * 2))
  61         #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
  62                                         (0 + ((_chan) * 2))
  63         #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan)  \
  64                                         (GENMASK(1, 0) << ((_chan) * 2))
  65
  66 #define MESON_SAR_ADC_REG3                                      0x0c
  67         #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY              BIT(31)
  68         #define MESON_SAR_ADC_REG3_CLK_EN                       BIT(30)
  69         #define MESON_SAR_ADC_REG3_BL30_INITIALIZED             BIT(28)
  70         #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN    BIT(27)
  71         #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE    BIT(26)
  72         #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK      GENMASK(25, 23)
  73         #define MESON_SAR_ADC_REG3_DETECT_EN                    BIT(22)
  74         #define MESON_SAR_ADC_REG3_ADC_EN                       BIT(21)
  75         #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK      GENMASK(20, 18)
  76         #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK  GENMASK(17, 16)
  77         #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT            10
  78         #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH            5
  79         #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK           GENMASK(9, 8)
  80         #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK               GENMASK(7, 0)
  81
  82 #define MESON_SAR_ADC_DELAY                                     0x10
  83         #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK          GENMASK(25, 24)
  84         #define MESON_SAR_ADC_DELAY_BL30_BUSY                   BIT(15)
  85         #define MESON_SAR_ADC_DELAY_KERNEL_BUSY                 BIT(14)
  86         #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK          GENMASK(23, 16)
  87         #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK         GENMASK(9, 8)
  88         #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK         GENMASK(7, 0)
  89
  90 #define MESON_SAR_ADC_LAST_RD                                   0x14
  91         #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK        GENMASK(23, 16)
  92         #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK        GENMASK(9, 0)
  93
  94 #define MESON_SAR_ADC_FIFO_RD                                   0x18
  95         #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK              GENMASK(14, 12)
  96         #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK         GENMASK(11, 0)
  97
  98 #define MESON_SAR_ADC_AUX_SW                                    0x1c
  99         #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan)   \
 100                                         (GENMASK(10, 8) << (((_chan) - 2) * 2))
 101         #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX                 BIT(6)
 102         #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX                 BIT(5)
 103         #define MESON_SAR_ADC_AUX_SW_MODE_SEL                   BIT(4)
 104         #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW                BIT(3)
 105         #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW                BIT(2)
 106         #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW                BIT(1)
 107         #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW                BIT(0)
 108
 109 #define MESON_SAR_ADC_CHAN_10_SW                                0x20
 110         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK     GENMASK(25, 23)
 111         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX       BIT(22)
 112         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX       BIT(21)
 113         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL         BIT(20)
 114         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW      BIT(19)
 115         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW      BIT(18)
 116         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW      BIT(17)
 117         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW      BIT(16)
 118         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK     GENMASK(9, 7)
 119         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX       BIT(6)
 120         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX       BIT(5)
 121         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL         BIT(4)
 122         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW      BIT(3)
 123         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW      BIT(2)
 124         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW      BIT(1)
 125         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW      BIT(0)
 126
 127 #define MESON_SAR_ADC_DETECT_IDLE_SW                            0x24
 128         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN       BIT(26)
 129         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK    GENMASK(25, 23)
 130         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX  BIT(22)
 131         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX  BIT(21)
 132         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL    BIT(20)
 133         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
 134         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
 135         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
 136         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
 137         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK  GENMASK(9, 7)
 138         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX    BIT(6)
 139         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX    BIT(5)
 140         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL      BIT(4)
 141         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW   BIT(3)
 142         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW   BIT(2)
 143         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW   BIT(1)
 144         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW   BIT(0)
 145
 146 #define MESON_SAR_ADC_DELTA_10                                  0x28
 147         #define MESON_SAR_ADC_DELTA_10_TEMP_SEL                 BIT(27)
 148         #define MESON_SAR_ADC_DELTA_10_TS_REVE1                 BIT(26)
 149         #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK   GENMASK(25, 16)
 150         #define MESON_SAR_ADC_DELTA_10_TS_REVE0                 BIT(15)
 151         #define MESON_SAR_ADC_DELTA_10_TS_C_SHIFT               11
 152         #define MESON_SAR_ADC_DELTA_10_TS_C_MASK                GENMASK(14, 11)
 153         #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN                BIT(10)
 154         #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK   GENMASK(9, 0)
 155
 156 /*
 157  * NOTE: registers from here are undocumented (the vendor Linux kernel driver
 158  * and u-boot source served as reference). These only seem to be relevant on
 159  * GXBB and newer.
 160  */
 161 #define MESON_SAR_ADC_REG11                                     0x2c
 162         #define MESON_SAR_ADC_REG11_BANDGAP_EN                  BIT(13)
 163
 164 #define MESON_SAR_ADC_REG13                                     0x34
 165         #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK      GENMASK(13, 8)
 166
 167 #define MESON_SAR_ADC_MAX_FIFO_SIZE                             32
 168 #define MESON_SAR_ADC_TIMEOUT                                   100 /* ms */
 169 /* for use with IIO_VAL_INT_PLUS_MICRO */
 170 #define MILLION                                                 1000000
 171
 172 #define MESON_SAR_ADC_CHAN(_chan) {                                     \
 173         .type = IIO_VOLTAGE,                                            \
 174         .indexed = 1,                                                   \
 175         .channel = _chan,                                               \
 176         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 177                                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
 178         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
 179                                 BIT(IIO_CHAN_INFO_CALIBBIAS) |          \
 180                                 BIT(IIO_CHAN_INFO_CALIBSCALE),          \
 181         .datasheet_name = "SAR_ADC_CH"#_chan,                           \
 182 }
 183
 184 /*
 185  * TODO: the hardware supports IIO_TEMP for channel 6 as well which is
 186  * currently not supported by this driver.
 187  */
 188 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
 189         MESON_SAR_ADC_CHAN(0),
 190         MESON_SAR_ADC_CHAN(1),
 191         MESON_SAR_ADC_CHAN(2),
 192         MESON_SAR_ADC_CHAN(3),
 193         MESON_SAR_ADC_CHAN(4),
 194         MESON_SAR_ADC_CHAN(5),
 195         MESON_SAR_ADC_CHAN(6),
 196         MESON_SAR_ADC_CHAN(7),
 197         IIO_CHAN_SOFT_TIMESTAMP(8),
 198 };
 199
 200 enum meson_sar_adc_avg_mode {
 201         NO_AVERAGING = 0x0,
 202         MEAN_AVERAGING = 0x1,
 203         MEDIAN_AVERAGING = 0x2,
 204 };
 205
 206 enum meson_sar_adc_num_samples {
 207         ONE_SAMPLE = 0x0,
 208         TWO_SAMPLES = 0x1,
 209         FOUR_SAMPLES = 0x2,
 210         EIGHT_SAMPLES = 0x3,
 211 };
 212
 213 enum meson_sar_adc_chan7_mux_sel {
 214         CHAN7_MUX_VSS = 0x0,
 215         CHAN7_MUX_VDD_DIV4 = 0x1,
 216         CHAN7_MUX_VDD_DIV2 = 0x2,
 217         CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
 218         CHAN7_MUX_VDD = 0x4,
 219         CHAN7_MUX_CH7_INPUT = 0x7,
 220 };
 221
 222 struct meson_sar_adc_data {
 223         bool                                    has_bl30_integration;
 224         u32                                     bandgap_reg;
 225         unsigned int                            resolution;
 226         const char                              *name;
 227         const struct regmap_config              *regmap_config;
 228 };
 229
 230 struct meson_sar_adc_priv {
 231         struct regmap                           *regmap;
 232         struct regulator                        *vref;
 233         const struct meson_sar_adc_data         *data;
 234         struct clk                              *clkin;
 235         struct clk                              *core_clk;
 236         struct clk                              *sana_clk;
 237         struct clk                              *adc_sel_clk;
 238         struct clk                              *adc_clk;
 239         struct clk_gate                         clk_gate;
 240         struct clk                              *adc_div_clk;
 241         struct clk_divider                      clk_div;
 242         struct completion                       done;
 243         int                                     calibbias;
 244         int                                     calibscale;
 245 };
 246
 247 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
 248         .reg_bits = 8,
 249         .val_bits = 32,
 250         .reg_stride = 4,
 251         .max_register = MESON_SAR_ADC_REG13,
 252 };
 253
 254 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
 255         .reg_bits = 8,
 256         .val_bits = 32,
 257         .reg_stride = 4,
 258         .max_register = MESON_SAR_ADC_DELTA_10,
 259 };
 260
 261 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
 262 {
 263         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 264         u32 regval;
 265
 266         regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 267
 268         return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
 269 }
 270
 271 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
 272 {
 273         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 274         int tmp;
 275
 276         /* use val_calib = scale * val_raw + offset calibration function */
 277         tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
 278
 279         return clamp(tmp, 0, (1 << priv->data->resolution) - 1);
 280 }
 281
 282 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
 283 {
 284         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 285         int regval, timeout = 10000;
 286
 287         /*
 288          * NOTE: we need a small delay before reading the status, otherwise
 289          * the sample engine may not have started internally (which would
 290          * seem to us that sampling is already finished).
 291          */
 292         do {
 293                 udelay(1);
 294                 regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 295         } while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);
 296
 297         if (timeout < 0)
 298                 return -ETIMEDOUT;
 299
 300         return 0;
 301 }
 302
 303 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
 304                                          const struct iio_chan_spec *chan,
 305                                          int *val)
 306 {
 307         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 308         int regval, fifo_chan, fifo_val, count;
 309
 310         if(!wait_for_completion_timeout(&priv->done,
 311                                 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
 312                 return -ETIMEDOUT;
 313
 314         count = meson_sar_adc_get_fifo_count(indio_dev);
 315         if (count != 1) {
 316                 dev_err(&indio_dev->dev,
 317                         "ADC FIFO has %d element(s) instead of one\n", count);
 318                 return -EINVAL;
 319         }
 320
 321         regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
 322         fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
 323         if (fifo_chan != chan->channel) {
 324                 dev_err(&indio_dev->dev,
 325                         "ADC FIFO entry belongs to channel %d instead of %d\n",
 326                         fifo_chan, chan->channel);
 327                 return -EINVAL;
 328         }
 329
 330         fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
 331         fifo_val &= GENMASK(priv->data->resolution - 1, 0);
 332         *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
 333
 334         return 0;
 335 }
 336
 337 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
 338                                         const struct iio_chan_spec *chan,
 339                                         enum meson_sar_adc_avg_mode mode,
 340                                         enum meson_sar_adc_num_samples samples)
 341 {
 342         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 343         int val, channel = chan->channel;
 344
 345         val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(channel);
 346         regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
 347                            MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(channel),
 348                            val);
 349
 350         val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(channel);
 351         regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
 352                            MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(channel), val);
 353 }
 354
 355 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
 356                                         const struct iio_chan_spec *chan)
 357 {
 358         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 359         u32 regval;
 360
 361         /*
 362          * the SAR ADC engine allows sampling multiple channels at the same
 363          * time. to keep it simple we're only working with one *internal*
 364          * channel, which starts counting at index 0 (which means: count = 1).
 365          */
 366         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
 367         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
 368                            MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
 369
 370         /* map channel index 0 to the channel which we want to read */
 371         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
 372                             chan->channel);
 373         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
 374                            MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
 375
 376         regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
 377                             chan->channel);
 378         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
 379                            MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
 380                            regval);
 381
 382         regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
 383                             chan->channel);
 384         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
 385                            MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
 386                            regval);
 387
 388         if (chan->channel == 6)
 389                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 390                                    MESON_SAR_ADC_DELTA_10_TEMP_SEL, 0);
 391 }
 392
 393 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
 394                                         enum meson_sar_adc_chan7_mux_sel sel)
 395 {
 396         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 397         u32 regval;
 398
 399         regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
 400         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 401                            MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
 402
 403         usleep_range(10, 20);
 404 }
 405
 406 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
 407 {
 408         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 409
 410         reinit_completion(&priv->done);
 411
 412         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 413                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
 414                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
 415
 416         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 417                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
 418                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
 419
 420         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 421                            MESON_SAR_ADC_REG0_SAMPLING_START,
 422                            MESON_SAR_ADC_REG0_SAMPLING_START);
 423 }
 424
 425 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
 426 {
 427         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 428
 429         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 430                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
 431
 432         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 433                            MESON_SAR_ADC_REG0_SAMPLING_STOP,
 434                            MESON_SAR_ADC_REG0_SAMPLING_STOP);
 435
 436         /* wait until all modules are stopped */
 437         meson_sar_adc_wait_busy_clear(indio_dev);
 438
 439         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 440                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
 441 }
 442
 443 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
 444 {
 445         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 446         int val, timeout = 10000;
 447
 448         mutex_lock(&indio_dev->mlock);
 449
 450         if (priv->data->has_bl30_integration) {
 451                 /* prevent BL30 from using the SAR ADC while we are using it */
 452                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 453                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY,
 454                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY);
 455
 456                 /*
 457                  * wait until BL30 releases it's lock (so we can use the SAR
 458                  * ADC)
 459                  */
 460                 do {
 461                         udelay(1);
 462                         regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);
 463                 } while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);
 464
 465                 if (timeout < 0) {
 466                         mutex_unlock(&indio_dev->mlock);
 467                         return -ETIMEDOUT;
 468                 }
 469         }
 470
 471         return 0;
 472 }
 473
 474 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
 475 {
 476         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 477
 478         if (priv->data->has_bl30_integration)
 479                 /* allow BL30 to use the SAR ADC again */
 480                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 481                                 MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
 482
 483         mutex_unlock(&indio_dev->mlock);
 484 }
 485
 486 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
 487 {
 488         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 489         unsigned int count, tmp;
 490
 491         for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
 492                 if (!meson_sar_adc_get_fifo_count(indio_dev))
 493                         break;
 494
 495                 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
 496         }
 497 }
 498
 499 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
 500                                     const struct iio_chan_spec *chan,
 501                                     enum meson_sar_adc_avg_mode avg_mode,
 502                                     enum meson_sar_adc_num_samples avg_samples,
 503                                     int *val)
 504 {
 505         int ret;
 506
 507         ret = meson_sar_adc_lock(indio_dev);
 508         if (ret)
 509                 return ret;
 510
 511         /* clear the FIFO to make sure we're not reading old values */
 512         meson_sar_adc_clear_fifo(indio_dev);
 513
 514         meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
 515
 516         meson_sar_adc_enable_channel(indio_dev, chan);
 517
 518         meson_sar_adc_start_sample_engine(indio_dev);
 519         ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
 520         meson_sar_adc_stop_sample_engine(indio_dev);
 521
 522         meson_sar_adc_unlock(indio_dev);
 523
 524         if (ret) {
 525                 dev_warn(indio_dev->dev.parent,
 526                          "failed to read sample for channel %d: %d\n",
 527                          chan->channel, ret);
 528                 return ret;
 529         }
 530
 531         return IIO_VAL_INT;
 532 }
 533
 534 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
 535                                            const struct iio_chan_spec *chan,
 536                                            int *val, int *val2, long mask)
 537 {
 538         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 539         int ret;
 540
 541         switch (mask) {
 542         case IIO_CHAN_INFO_RAW:
 543                 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
 544                                                 ONE_SAMPLE, val);
 545                 break;
 546
 547         case IIO_CHAN_INFO_AVERAGE_RAW:
 548                 return meson_sar_adc_get_sample(indio_dev, chan,
 549                                                 MEAN_AVERAGING, EIGHT_SAMPLES,
 550                                                 val);
 551                 break;
 552
 553         case IIO_CHAN_INFO_SCALE:
 554                 ret = regulator_get_voltage(priv->vref);
 555                 if (ret < 0) {
 556                         dev_err(indio_dev->dev.parent,
 557                                 "failed to get vref voltage: %d\n", ret);
 558                         return ret;
 559                 }
 560
 561                 *val = ret / 1000;
 562                 *val2 = priv->data->resolution;
 563                 return IIO_VAL_FRACTIONAL_LOG2;
 564
 565         case IIO_CHAN_INFO_CALIBBIAS:
 566                 *val = priv->calibbias;
 567                 return IIO_VAL_INT;
 568
 569         case IIO_CHAN_INFO_CALIBSCALE:
 570                 *val = priv->calibscale / MILLION;
 571                 *val2 = priv->calibscale % MILLION;
 572                 return IIO_VAL_INT_PLUS_MICRO;
 573
 574         default:
 575                 return -EINVAL;
 576         }
 577 }
 578
 579 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
 580                                   void __iomem *base)
 581 {
 582         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 583         struct clk_init_data init;
 584         const char *clk_parents[1];
 585
 586         init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",
 587                                    dev_name(indio_dev->dev.parent));
 588         if (!init.name)
 589                 return -ENOMEM;
 590
 591         init.flags = 0;
 592         init.ops = &clk_divider_ops;
 593         clk_parents[0] = __clk_get_name(priv->clkin);
 594         init.parent_names = clk_parents;
 595         init.num_parents = 1;
 596
 597         priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
 598         priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
 599         priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
 600         priv->clk_div.hw.init = &init;
 601         priv->clk_div.flags = 0;
 602
 603         priv->adc_div_clk = devm_clk_register(&indio_dev->dev,
 604                                               &priv->clk_div.hw);
 605         if (WARN_ON(IS_ERR(priv->adc_div_clk)))
 606                 return PTR_ERR(priv->adc_div_clk);
 607
 608         init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",
 609                                    dev_name(indio_dev->dev.parent));
 610         if (!init.name)
 611                 return -ENOMEM;
 612
 613         init.flags = CLK_SET_RATE_PARENT;
 614         init.ops = &clk_gate_ops;
 615         clk_parents[0] = __clk_get_name(priv->adc_div_clk);
 616         init.parent_names = clk_parents;
 617         init.num_parents = 1;
 618
 619         priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
 620         priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
 621         priv->clk_gate.hw.init = &init;
 622
 623         priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);
 624         if (WARN_ON(IS_ERR(priv->adc_clk)))
 625                 return PTR_ERR(priv->adc_clk);
 626
 627         return 0;
 628 }
 629
 630 static int meson_sar_adc_init(struct iio_dev *indio_dev)
 631 {
 632         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 633         int regval, ret;
 634
 635         /*
 636          * make sure we start at CH7 input since the other muxes are only used
 637          * for internal calibration.
 638          */
 639         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
 640
 641         if (priv->data->has_bl30_integration) {
 642                 /*
 643                  * leave sampling delay and the input clocks as configured by
 644                  * BL30 to make sure BL30 gets the values it expects when
 645                  * reading the temperature sensor.
 646                  */
 647                 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
 648                 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
 649                         return 0;
 650         }
 651
 652         meson_sar_adc_stop_sample_engine(indio_dev);
 653
 654         /* update the channel 6 MUX to select the temperature sensor */
 655         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 656                         MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL,
 657                         MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL);
 658
 659         /* disable all channels by default */
 660         regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
 661
 662         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 663                            MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
 664         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 665                            MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
 666                            MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
 667
 668         /* delay between two samples = (10+1) * 1uS */
 669         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 670                            MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 671                            FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
 672                                       10));
 673         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 674                            MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
 675                            FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
 676                                       0));
 677
 678         /* delay between two samples = (10+1) * 1uS */
 679         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 680                            MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 681                            FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 682                                       10));
 683         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 684                            MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
 685                            FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
 686                                       1));
 687
 688         ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
 689         if (ret) {
 690                 dev_err(indio_dev->dev.parent,
 691                         "failed to set adc parent to clkin\n");
 692                 return ret;
 693         }
 694
 695         ret = clk_set_rate(priv->adc_clk, 1200000);
 696         if (ret) {
 697                 dev_err(indio_dev->dev.parent,
 698                         "failed to set adc clock rate\n");
 699                 return ret;
 700         }
 701
 702         return 0;
 703 }
 704
 705 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
 706 {
 707         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 708         u32 enable_mask;
 709
 710         if (priv->data->bandgap_reg == MESON_SAR_ADC_REG11)
 711                 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
 712         else
 713                 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
 714
 715         regmap_update_bits(priv->regmap, priv->data->bandgap_reg, enable_mask,
 716                            on_off ? enable_mask : 0);
 717 }
 718
 719 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
 720 {
 721         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 722         int ret;
 723         u32 regval;
 724
 725         ret = meson_sar_adc_lock(indio_dev);
 726         if (ret)
 727                 goto err_lock;
 728
 729         ret = regulator_enable(priv->vref);
 730         if (ret < 0) {
 731                 dev_err(indio_dev->dev.parent,
 732                         "failed to enable vref regulator\n");
 733                 goto err_vref;
 734         }
 735
 736         ret = clk_prepare_enable(priv->core_clk);
 737         if (ret) {
 738                 dev_err(indio_dev->dev.parent, "failed to enable core clk\n");
 739                 goto err_core_clk;
 740         }
 741
 742         ret = clk_prepare_enable(priv->sana_clk);
 743         if (ret) {
 744                 dev_err(indio_dev->dev.parent, "failed to enable sana clk\n");
 745                 goto err_sana_clk;
 746         }
 747
 748         regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
 749         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 750                            MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
 751
 752         meson_sar_adc_set_bandgap(indio_dev, true);
 753
 754         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 755                            MESON_SAR_ADC_REG3_ADC_EN,
 756                            MESON_SAR_ADC_REG3_ADC_EN);
 757
 758         udelay(5);
 759
 760         ret = clk_prepare_enable(priv->adc_clk);
 761         if (ret) {
 762                 dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");
 763                 goto err_adc_clk;
 764         }
 765
 766         meson_sar_adc_unlock(indio_dev);
 767
 768         return 0;
 769
 770 err_adc_clk:
 771         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 772                            MESON_SAR_ADC_REG3_ADC_EN, 0);
 773         meson_sar_adc_set_bandgap(indio_dev, false);
 774         clk_disable_unprepare(priv->sana_clk);
 775 err_sana_clk:
 776         clk_disable_unprepare(priv->core_clk);
 777 err_core_clk:
 778         regulator_disable(priv->vref);
 779 err_vref:
 780         meson_sar_adc_unlock(indio_dev);
 781 err_lock:
 782         return ret;
 783 }
 784
 785 static int meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
 786 {
 787         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 788         int ret;
 789
 790         ret = meson_sar_adc_lock(indio_dev);
 791         if (ret)
 792                 return ret;
 793
 794         clk_disable_unprepare(priv->adc_clk);
 795
 796         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 797                            MESON_SAR_ADC_REG3_ADC_EN, 0);
 798
 799         meson_sar_adc_set_bandgap(indio_dev, false);
 800
 801         clk_disable_unprepare(priv->sana_clk);
 802         clk_disable_unprepare(priv->core_clk);
 803
 804         regulator_disable(priv->vref);
 805
 806         meson_sar_adc_unlock(indio_dev);
 807
 808         return 0;
 809 }
 810
 811 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
 812 {
 813         struct iio_dev *indio_dev = data;
 814         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 815         unsigned int cnt, threshold;
 816         u32 regval;
 817
 818         regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 819         cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
 820         threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
 821
 822         if (cnt < threshold)
 823                 return IRQ_NONE;
 824
 825         complete(&priv->done);
 826
 827         return IRQ_HANDLED;
 828 }
 829
 830 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
 831 {
 832         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 833         int ret, nominal0, nominal1, value0, value1;
 834
 835         /* use points 25% and 75% for calibration */
 836         nominal0 = (1 << priv->data->resolution) / 4;
 837         nominal1 = (1 << priv->data->resolution) * 3 / 4;
 838
 839         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
 840         usleep_range(10, 20);
 841         ret = meson_sar_adc_get_sample(indio_dev,
 842                                        &meson_sar_adc_iio_channels[7],
 843                                        MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
 844         if (ret < 0)
 845                 goto out;
 846
 847         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
 848         usleep_range(10, 20);
 849         ret = meson_sar_adc_get_sample(indio_dev,
 850                                        &meson_sar_adc_iio_channels[7],
 851                                        MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
 852         if (ret < 0)
 853                 goto out;
 854
 855         if (value1 <= value0) {
 856                 ret = -EINVAL;
 857                 goto out;
 858         }
 859
 860         priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
 861                                    value1 - value0);
 862         priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
 863                                              MILLION);
 864         ret = 0;
 865 out:
 866         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
 867
 868         return ret;
 869 }
 870
 871 static const struct iio_info meson_sar_adc_iio_info = {
 872         .read_raw = meson_sar_adc_iio_info_read_raw,
 873         .driver_module = THIS_MODULE,
 874 };
 875
 876 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
 877         .has_bl30_integration = false,
 878         .bandgap_reg = MESON_SAR_ADC_DELTA_10,
 879         .regmap_config = &meson_sar_adc_regmap_config_meson8,
 880         .resolution = 10,
 881         .name = "meson-meson8-saradc",
 882 };
 883
 884 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
 885         .has_bl30_integration = false,
 886         .bandgap_reg = MESON_SAR_ADC_DELTA_10,
 887         .regmap_config = &meson_sar_adc_regmap_config_meson8,
 888         .resolution = 10,
 889         .name = "meson-meson8b-saradc",
 890 };
 891
 892 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
 893         .has_bl30_integration = true,
 894         .bandgap_reg = MESON_SAR_ADC_REG11,
 895         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
 896         .resolution = 10,
 897         .name = "meson-gxbb-saradc",
 898 };
 899
 900 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
 901         .has_bl30_integration = true,
 902         .bandgap_reg = MESON_SAR_ADC_REG11,
 903         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
 904         .resolution = 12,
 905         .name = "meson-gxl-saradc",
 906 };
 907
 908 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
 909         .has_bl30_integration = true,
 910         .bandgap_reg = MESON_SAR_ADC_REG11,
 911         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
 912         .resolution = 12,
 913         .name = "meson-gxm-saradc",
 914 };
 915
 916 static const struct of_device_id meson_sar_adc_of_match[] = {
 917         {
 918                 .compatible = "amlogic,meson8-saradc",
 919                 .data = &meson_sar_adc_meson8_data,
 920         },
 921         {
 922                 .compatible = "amlogic,meson8b-saradc",
 923                 .data = &meson_sar_adc_meson8b_data,
 924         },
 925         {
 926                 .compatible = "amlogic,meson-gxbb-saradc",
 927                 .data = &meson_sar_adc_gxbb_data,
 928         }, {
 929                 .compatible = "amlogic,meson-gxl-saradc",
 930                 .data = &meson_sar_adc_gxl_data,
 931         }, {
 932                 .compatible = "amlogic,meson-gxm-saradc",
 933                 .data = &meson_sar_adc_gxm_data,
 934         },
 935         {},
 936 };
 937 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
 938
 939 static int meson_sar_adc_probe(struct platform_device *pdev)
 940 {
 941         struct meson_sar_adc_priv *priv;
 942         struct iio_dev *indio_dev;
 943         struct resource *res;
 944         void __iomem *base;
 945         const struct of_device_id *match;
 946         int irq, ret;
 947
 948         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
 949         if (!indio_dev) {
 950                 dev_err(&pdev->dev, "failed allocating iio device\n");
 951                 return -ENOMEM;
 952         }
 953
 954         priv = iio_priv(indio_dev);
 955         init_completion(&priv->done);
 956
 957         match = of_match_device(meson_sar_adc_of_match, &pdev->dev);
 958         if (!match) {
 959                 dev_err(&pdev->dev, "failed to match device\n");
 960                 return -ENODEV;
 961         }
 962
 963         priv->data = match->data;
 964
 965         indio_dev->name = priv->data->name;
 966         indio_dev->dev.parent = &pdev->dev;
 967         indio_dev->dev.of_node = pdev->dev.of_node;
 968         indio_dev->modes = INDIO_DIRECT_MODE;
 969         indio_dev->info = &meson_sar_adc_iio_info;
 970
 971         indio_dev->channels = meson_sar_adc_iio_channels;
 972         indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);
 973
 974         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 975         base = devm_ioremap_resource(&pdev->dev, res);
 976         if (IS_ERR(base))
 977                 return PTR_ERR(base);
 978
 979         priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,
 980                                              priv->data->regmap_config);
 981         if (IS_ERR(priv->regmap))
 982                 return PTR_ERR(priv->regmap);
 983
 984         irq = irq_of_parse_and_map(pdev->dev.of_node, 0);
 985         if (!irq)
 986                 return -EINVAL;
 987
 988         ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED,
 989                                dev_name(&pdev->dev), indio_dev);
 990         if (ret)
 991                 return ret;
 992
 993         priv->clkin = devm_clk_get(&pdev->dev, "clkin");
 994         if (IS_ERR(priv->clkin)) {
 995                 dev_err(&pdev->dev, "failed to get clkin\n");
 996                 return PTR_ERR(priv->clkin);
 997         }
 998
 999         priv->core_clk = devm_clk_get(&pdev->dev, "core");
1000         if (IS_ERR(priv->core_clk)) {
1001                 dev_err(&pdev->dev, "failed to get core clk\n");
1002                 return PTR_ERR(priv->core_clk);
1003         }
1004
1005         priv->sana_clk = devm_clk_get(&pdev->dev, "sana");
1006         if (IS_ERR(priv->sana_clk)) {
1007                 if (PTR_ERR(priv->sana_clk) == -ENOENT) {
1008                         priv->sana_clk = NULL;
1009                 } else {
1010                         dev_err(&pdev->dev, "failed to get sana clk\n");
1011                         return PTR_ERR(priv->sana_clk);
1012                 }
1013         }
1014
1015         priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");
1016         if (IS_ERR(priv->adc_clk)) {
1017                 if (PTR_ERR(priv->adc_clk) == -ENOENT) {
1018                         priv->adc_clk = NULL;
1019                 } else {
1020                         dev_err(&pdev->dev, "failed to get adc clk\n");
1021                         return PTR_ERR(priv->adc_clk);
1022                 }
1023         }
1024
1025         priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");
1026         if (IS_ERR(priv->adc_sel_clk)) {
1027                 if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {
1028                         priv->adc_sel_clk = NULL;
1029                 } else {
1030                         dev_err(&pdev->dev, "failed to get adc_sel clk\n");
1031                         return PTR_ERR(priv->adc_sel_clk);
1032                 }
1033         }
1034
1035         /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1036         if (!priv->adc_clk) {
1037                 ret = meson_sar_adc_clk_init(indio_dev, base);
1038                 if (ret)
1039                         return ret;
1040         }
1041
1042         priv->vref = devm_regulator_get(&pdev->dev, "vref");
1043         if (IS_ERR(priv->vref)) {
1044                 dev_err(&pdev->dev, "failed to get vref regulator\n");
1045                 return PTR_ERR(priv->vref);
1046         }
1047
1048         priv->calibscale = MILLION;
1049
1050         ret = meson_sar_adc_init(indio_dev);
1051         if (ret)
1052                 goto err;
1053
1054         ret = meson_sar_adc_hw_enable(indio_dev);
1055         if (ret)
1056                 goto err;
1057
1058         ret = meson_sar_adc_calib(indio_dev);
1059         if (ret)
1060                 dev_warn(&pdev->dev, "calibration failed\n");
1061
1062         platform_set_drvdata(pdev, indio_dev);
1063
1064         ret = iio_device_register(indio_dev);
1065         if (ret)
1066                 goto err_hw;
1067
1068         return 0;
1069
1070 err_hw:
1071         meson_sar_adc_hw_disable(indio_dev);
1072 err:
1073         return ret;
1074 }
1075
1076 static int meson_sar_adc_remove(struct platform_device *pdev)
1077 {
1078         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1079
1080         iio_device_unregister(indio_dev);
1081
1082         return meson_sar_adc_hw_disable(indio_dev);
1083 }
1084
1085 static int __maybe_unused meson_sar_adc_suspend(struct device *dev)
1086 {
1087         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1088
1089         return meson_sar_adc_hw_disable(indio_dev);
1090 }
1091
1092 static int __maybe_unused meson_sar_adc_resume(struct device *dev)
1093 {
1094         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1095
1096         return meson_sar_adc_hw_enable(indio_dev);
1097 }
1098
1099 static SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1100                          meson_sar_adc_suspend, meson_sar_adc_resume);
1101
1102 static struct platform_driver meson_sar_adc_driver = {
1103         .probe          = meson_sar_adc_probe,
1104         .remove         = meson_sar_adc_remove,
1105         .driver         = {
1106                 .name   = "meson-saradc",
1107                 .of_match_table = meson_sar_adc_of_match,
1108                 .pm = &meson_sar_adc_pm_ops,
1109         },
1110 };
1111
1112 module_platform_driver(meson_sar_adc_driver);
1113
1114 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1115 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1116 MODULE_LICENSE("GPL v2");