drivers/iio/adc/meson_saradc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
   4  *
   5  * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/clk-provider.h>
  11 #include <linux/delay.h>
  12 #include <linux/io.h>
  13 #include <linux/iio/iio.h>
  14 #include <linux/module.h>
  15 #include <linux/mutex.h>
  16 #include <linux/nvmem-consumer.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/of.h>
  19 #include <linux/of_irq.h>
  20 #include <linux/platform_device.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23 #include <linux/mfd/syscon.h>
  24
  25 #define MESON_SAR_ADC_REG0                                      0x00
  26         #define MESON_SAR_ADC_REG0_PANEL_DETECT                 BIT(31)
  27         #define MESON_SAR_ADC_REG0_BUSY_MASK                    GENMASK(30, 28)
  28         #define MESON_SAR_ADC_REG0_DELTA_BUSY                   BIT(30)
  29         #define MESON_SAR_ADC_REG0_AVG_BUSY                     BIT(29)
  30         #define MESON_SAR_ADC_REG0_SAMPLE_BUSY                  BIT(28)
  31         #define MESON_SAR_ADC_REG0_FIFO_FULL                    BIT(27)
  32         #define MESON_SAR_ADC_REG0_FIFO_EMPTY                   BIT(26)
  33         #define MESON_SAR_ADC_REG0_FIFO_COUNT_MASK              GENMASK(25, 21)
  34         #define MESON_SAR_ADC_REG0_ADC_BIAS_CTRL_MASK           GENMASK(20, 19)
  35         #define MESON_SAR_ADC_REG0_CURR_CHAN_ID_MASK            GENMASK(18, 16)
  36         #define MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL             BIT(15)
  37         #define MESON_SAR_ADC_REG0_SAMPLING_STOP                BIT(14)
  38         #define MESON_SAR_ADC_REG0_CHAN_DELTA_EN_MASK           GENMASK(13, 12)
  39         #define MESON_SAR_ADC_REG0_DETECT_IRQ_POL               BIT(10)
  40         #define MESON_SAR_ADC_REG0_DETECT_IRQ_EN                BIT(9)
  41         #define MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK            GENMASK(8, 4)
  42         #define MESON_SAR_ADC_REG0_FIFO_IRQ_EN                  BIT(3)
  43         #define MESON_SAR_ADC_REG0_SAMPLING_START               BIT(2)
  44         #define MESON_SAR_ADC_REG0_CONTINUOUS_EN                BIT(1)
  45         #define MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE         BIT(0)
  46
  47 #define MESON_SAR_ADC_CHAN_LIST                                 0x04
  48         #define MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK          GENMASK(26, 24)
  49         #define MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan)       \
  50                                         (GENMASK(2, 0) << ((_chan) * 3))
  51
  52 #define MESON_SAR_ADC_AVG_CNTL                                  0x08
  53         #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan)    \
  54                                         (16 + ((_chan) * 2))
  55         #define MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan)     \
  56                                         (GENMASK(17, 16) << ((_chan) * 2))
  57         #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
  58                                         (0 + ((_chan) * 2))
  59         #define MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan)  \
  60                                         (GENMASK(1, 0) << ((_chan) * 2))
  61
  62 #define MESON_SAR_ADC_REG3                                      0x0c
  63         #define MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY              BIT(31)
  64         #define MESON_SAR_ADC_REG3_CLK_EN                       BIT(30)
  65         #define MESON_SAR_ADC_REG3_BL30_INITIALIZED             BIT(28)
  66         #define MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN    BIT(27)
  67         #define MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE    BIT(26)
  68         #define MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK      GENMASK(25, 23)
  69         #define MESON_SAR_ADC_REG3_DETECT_EN                    BIT(22)
  70         #define MESON_SAR_ADC_REG3_ADC_EN                       BIT(21)
  71         #define MESON_SAR_ADC_REG3_PANEL_DETECT_COUNT_MASK      GENMASK(20, 18)
  72         #define MESON_SAR_ADC_REG3_PANEL_DETECT_FILTER_TB_MASK  GENMASK(17, 16)
  73         #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT            10
  74         #define MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH            6
  75         #define MESON_SAR_ADC_REG3_BLOCK_DLY_SEL_MASK           GENMASK(9, 8)
  76         #define MESON_SAR_ADC_REG3_BLOCK_DLY_MASK               GENMASK(7, 0)
  77
  78 #define MESON_SAR_ADC_DELAY                                     0x10
  79         #define MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK          GENMASK(25, 24)
  80         #define MESON_SAR_ADC_DELAY_BL30_BUSY                   BIT(15)
  81         #define MESON_SAR_ADC_DELAY_KERNEL_BUSY                 BIT(14)
  82         #define MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK          GENMASK(23, 16)
  83         #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK         GENMASK(9, 8)
  84         #define MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK         GENMASK(7, 0)
  85
  86 #define MESON_SAR_ADC_LAST_RD                                   0x14
  87         #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL1_MASK        GENMASK(23, 16)
  88         #define MESON_SAR_ADC_LAST_RD_LAST_CHANNEL0_MASK        GENMASK(9, 0)
  89
  90 #define MESON_SAR_ADC_FIFO_RD                                   0x18
  91         #define MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK              GENMASK(14, 12)
  92         #define MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK         GENMASK(11, 0)
  93
  94 #define MESON_SAR_ADC_AUX_SW                                    0x1c
  95         #define MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(_chan)  \
  96                                         (8 + (((_chan) - 2) * 3))
  97         #define MESON_SAR_ADC_AUX_SW_VREF_P_MUX                 BIT(6)
  98         #define MESON_SAR_ADC_AUX_SW_VREF_N_MUX                 BIT(5)
  99         #define MESON_SAR_ADC_AUX_SW_MODE_SEL                   BIT(4)
 100         #define MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW                BIT(3)
 101         #define MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW                BIT(2)
 102         #define MESON_SAR_ADC_AUX_SW_YM_DRIVE_SW                BIT(1)
 103         #define MESON_SAR_ADC_AUX_SW_XM_DRIVE_SW                BIT(0)
 104
 105 #define MESON_SAR_ADC_CHAN_10_SW                                0x20
 106         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK     GENMASK(25, 23)
 107         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_P_MUX       BIT(22)
 108         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_VREF_N_MUX       BIT(21)
 109         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_MODE_SEL         BIT(20)
 110         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW      BIT(19)
 111         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW      BIT(18)
 112         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_YM_DRIVE_SW      BIT(17)
 113         #define MESON_SAR_ADC_CHAN_10_SW_CHAN1_XM_DRIVE_SW      BIT(16)
 114         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK     GENMASK(9, 7)
 115         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_P_MUX       BIT(6)
 116         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_VREF_N_MUX       BIT(5)
 117         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_MODE_SEL         BIT(4)
 118         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW      BIT(3)
 119         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW      BIT(2)
 120         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_YM_DRIVE_SW      BIT(1)
 121         #define MESON_SAR_ADC_CHAN_10_SW_CHAN0_XM_DRIVE_SW      BIT(0)
 122
 123 #define MESON_SAR_ADC_DETECT_IDLE_SW                            0x24
 124         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN       BIT(26)
 125         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK    GENMASK(25, 23)
 126         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_P_MUX  BIT(22)
 127         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_VREF_N_MUX  BIT(21)
 128         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MODE_SEL    BIT(20)
 129         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YP_DRIVE_SW BIT(19)
 130         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XP_DRIVE_SW BIT(18)
 131         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_YM_DRIVE_SW BIT(17)
 132         #define MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_XM_DRIVE_SW BIT(16)
 133         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK  GENMASK(9, 7)
 134         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_P_MUX    BIT(6)
 135         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_VREF_N_MUX    BIT(5)
 136         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MODE_SEL      BIT(4)
 137         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YP_DRIVE_SW   BIT(3)
 138         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XP_DRIVE_SW   BIT(2)
 139         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_YM_DRIVE_SW   BIT(1)
 140         #define MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_XM_DRIVE_SW   BIT(0)
 141
 142 #define MESON_SAR_ADC_DELTA_10                                  0x28
 143         #define MESON_SAR_ADC_DELTA_10_TEMP_SEL                 BIT(27)
 144         #define MESON_SAR_ADC_DELTA_10_TS_REVE1                 BIT(26)
 145         #define MESON_SAR_ADC_DELTA_10_CHAN1_DELTA_VALUE_MASK   GENMASK(25, 16)
 146         #define MESON_SAR_ADC_DELTA_10_TS_REVE0                 BIT(15)
 147         #define MESON_SAR_ADC_DELTA_10_TS_C_MASK                GENMASK(14, 11)
 148         #define MESON_SAR_ADC_DELTA_10_TS_VBG_EN                BIT(10)
 149         #define MESON_SAR_ADC_DELTA_10_CHAN0_DELTA_VALUE_MASK   GENMASK(9, 0)
 150
 151 /*
 152  * NOTE: registers from here are undocumented (the vendor Linux kernel driver
 153  * and u-boot source served as reference). These only seem to be relevant on
 154  * GXBB and newer.
 155  */
 156 #define MESON_SAR_ADC_REG11                                     0x2c
 157         #define MESON_SAR_ADC_REG11_BANDGAP_EN                  BIT(13)
 158         #define MESON_SAR_ADC_REG11_CMV_SEL                     BIT(6)
 159         #define MESON_SAR_ADC_REG11_VREF_VOLTAGE                BIT(5)
 160         #define MESON_SAR_ADC_REG11_EOC                         BIT(1)
 161         #define MESON_SAR_ADC_REG11_VREF_SEL                    BIT(0)
 162
 163 #define MESON_SAR_ADC_REG13                                     0x34
 164         #define MESON_SAR_ADC_REG13_12BIT_CALIBRATION_MASK      GENMASK(13, 8)
 165
 166 #define MESON_SAR_ADC_MAX_FIFO_SIZE                             32
 167 #define MESON_SAR_ADC_TIMEOUT                                   100 /* ms */
 168 #define MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL                  6
 169 #define MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL                   7
 170 #define MESON_SAR_ADC_TEMP_OFFSET                               27
 171
 172 /* temperature sensor calibration information in eFuse */
 173 #define MESON_SAR_ADC_EFUSE_BYTES                               4
 174 #define MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL                 GENMASK(6, 0)
 175 #define MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED                 BIT(7)
 176
 177 #define MESON_HHI_DPLL_TOP_0                                    0x318
 178 #define MESON_HHI_DPLL_TOP_0_TSC_BIT4                           BIT(9)
 179
 180 /* for use with IIO_VAL_INT_PLUS_MICRO */
 181 #define MILLION                                                 1000000
 182
 183 #define MESON_SAR_ADC_CHAN(_chan) {                                     \
 184         .type = IIO_VOLTAGE,                                            \
 185         .indexed = 1,                                                   \
 186         .channel = _chan,                                               \
 187         .address = _chan,                                               \
 188         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 189                                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
 190         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),           \
 191         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) |       \
 192                                 BIT(IIO_CHAN_INFO_CALIBSCALE),          \
 193         .datasheet_name = "SAR_ADC_CH"#_chan,                           \
 194 }
 195
 196 #define MESON_SAR_ADC_TEMP_CHAN(_chan) {                                \
 197         .type = IIO_TEMP,                                               \
 198         .channel = _chan,                                               \
 199         .address = MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL,              \
 200         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 201                                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
 202         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_OFFSET) |         \
 203                                         BIT(IIO_CHAN_INFO_SCALE),       \
 204         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) |       \
 205                                 BIT(IIO_CHAN_INFO_CALIBSCALE),          \
 206         .datasheet_name = "TEMP_SENSOR",                                \
 207 }
 208
 209 #define MESON_SAR_ADC_MUX(_chan, _sel) {                                \
 210         .type = IIO_VOLTAGE,                                            \
 211         .channel = _chan,                                               \
 212         .indexed = 1,                                                   \
 213         .address = MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL,               \
 214         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |                  \
 215                                 BIT(IIO_CHAN_INFO_AVERAGE_RAW),         \
 216         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),           \
 217         .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_CALIBBIAS) |       \
 218                                 BIT(IIO_CHAN_INFO_CALIBSCALE),          \
 219         .datasheet_name = "SAR_ADC_MUX_"#_sel,                          \
 220 }
 221
 222 enum meson_sar_adc_vref_sel {
 223         VREF_CALIBATION_VOLTAGE = 0,
 224         VREF_VDDA = 1,
 225 };
 226
 227 enum meson_sar_adc_avg_mode {
 228         NO_AVERAGING = 0x0,
 229         MEAN_AVERAGING = 0x1,
 230         MEDIAN_AVERAGING = 0x2,
 231 };
 232
 233 enum meson_sar_adc_num_samples {
 234         ONE_SAMPLE = 0x0,
 235         TWO_SAMPLES = 0x1,
 236         FOUR_SAMPLES = 0x2,
 237         EIGHT_SAMPLES = 0x3,
 238 };
 239
 240 enum meson_sar_adc_chan7_mux_sel {
 241         CHAN7_MUX_VSS = 0x0,
 242         CHAN7_MUX_VDD_DIV4 = 0x1,
 243         CHAN7_MUX_VDD_DIV2 = 0x2,
 244         CHAN7_MUX_VDD_MUL3_DIV4 = 0x3,
 245         CHAN7_MUX_VDD = 0x4,
 246         CHAN7_MUX_CH7_INPUT = 0x7,
 247 };
 248
 249 enum meson_sar_adc_channel_index {
 250         NUM_CHAN_0,
 251         NUM_CHAN_1,
 252         NUM_CHAN_2,
 253         NUM_CHAN_3,
 254         NUM_CHAN_4,
 255         NUM_CHAN_5,
 256         NUM_CHAN_6,
 257         NUM_CHAN_7,
 258         NUM_CHAN_TEMP,
 259         NUM_MUX_0_VSS,
 260         NUM_MUX_1_VDD_DIV4,
 261         NUM_MUX_2_VDD_DIV2,
 262         NUM_MUX_3_VDD_MUL3_DIV4,
 263         NUM_MUX_4_VDD,
 264 };
 265
 266 static enum meson_sar_adc_chan7_mux_sel chan7_mux_values[] = {
 267         CHAN7_MUX_VSS,
 268         CHAN7_MUX_VDD_DIV4,
 269         CHAN7_MUX_VDD_DIV2,
 270         CHAN7_MUX_VDD_MUL3_DIV4,
 271         CHAN7_MUX_VDD,
 272 };
 273
 274 static const char * const chan7_mux_names[] = {
 275         [CHAN7_MUX_VSS] = "gnd",
 276         [CHAN7_MUX_VDD_DIV4] = "0.25vdd",
 277         [CHAN7_MUX_VDD_DIV2] = "0.5vdd",
 278         [CHAN7_MUX_VDD_MUL3_DIV4] = "0.75vdd",
 279         [CHAN7_MUX_VDD] = "vdd",
 280 };
 281
 282 static const struct iio_chan_spec meson_sar_adc_iio_channels[] = {
 283         MESON_SAR_ADC_CHAN(NUM_CHAN_0),
 284         MESON_SAR_ADC_CHAN(NUM_CHAN_1),
 285         MESON_SAR_ADC_CHAN(NUM_CHAN_2),
 286         MESON_SAR_ADC_CHAN(NUM_CHAN_3),
 287         MESON_SAR_ADC_CHAN(NUM_CHAN_4),
 288         MESON_SAR_ADC_CHAN(NUM_CHAN_5),
 289         MESON_SAR_ADC_CHAN(NUM_CHAN_6),
 290         MESON_SAR_ADC_CHAN(NUM_CHAN_7),
 291         MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0),
 292         MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1),
 293         MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2),
 294         MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3),
 295         MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4),
 296 };
 297
 298 static const struct iio_chan_spec meson_sar_adc_and_temp_iio_channels[] = {
 299         MESON_SAR_ADC_CHAN(NUM_CHAN_0),
 300         MESON_SAR_ADC_CHAN(NUM_CHAN_1),
 301         MESON_SAR_ADC_CHAN(NUM_CHAN_2),
 302         MESON_SAR_ADC_CHAN(NUM_CHAN_3),
 303         MESON_SAR_ADC_CHAN(NUM_CHAN_4),
 304         MESON_SAR_ADC_CHAN(NUM_CHAN_5),
 305         MESON_SAR_ADC_CHAN(NUM_CHAN_6),
 306         MESON_SAR_ADC_CHAN(NUM_CHAN_7),
 307         MESON_SAR_ADC_TEMP_CHAN(NUM_CHAN_TEMP),
 308         MESON_SAR_ADC_MUX(NUM_MUX_0_VSS, 0),
 309         MESON_SAR_ADC_MUX(NUM_MUX_1_VDD_DIV4, 1),
 310         MESON_SAR_ADC_MUX(NUM_MUX_2_VDD_DIV2, 2),
 311         MESON_SAR_ADC_MUX(NUM_MUX_3_VDD_MUL3_DIV4, 3),
 312         MESON_SAR_ADC_MUX(NUM_MUX_4_VDD, 4),
 313 };
 314
 315 struct meson_sar_adc_param {
 316         bool                                    has_bl30_integration;
 317         unsigned long                           clock_rate;
 318         u32                                     bandgap_reg;
 319         unsigned int                            resolution;
 320         const struct regmap_config              *regmap_config;
 321         u8                                      temperature_trimming_bits;
 322         unsigned int                            temperature_multiplier;
 323         unsigned int                            temperature_divider;
 324         u8                                      disable_ring_counter;
 325         bool                                    has_reg11;
 326         bool                                    has_vref_select;
 327         u8                                      vref_select;
 328         u8                                      cmv_select;
 329         u8                                      adc_eoc;
 330         enum meson_sar_adc_vref_sel             vref_volatge;
 331 };
 332
 333 struct meson_sar_adc_data {
 334         const struct meson_sar_adc_param        *param;
 335         const char                              *name;
 336 };
 337
 338 struct meson_sar_adc_priv {
 339         struct regmap                           *regmap;
 340         struct regulator                        *vref;
 341         const struct meson_sar_adc_param        *param;
 342         struct clk                              *clkin;
 343         struct clk                              *core_clk;
 344         struct clk                              *adc_sel_clk;
 345         struct clk                              *adc_clk;
 346         struct clk_gate                         clk_gate;
 347         struct clk                              *adc_div_clk;
 348         struct clk_divider                      clk_div;
 349         struct completion                       done;
 350         /* lock to protect against multiple access to the device */
 351         struct mutex                            lock;
 352         int                                     calibbias;
 353         int                                     calibscale;
 354         struct regmap                           *tsc_regmap;
 355         bool                                    temperature_sensor_calibrated;
 356         u8                                      temperature_sensor_coefficient;
 357         u16                                     temperature_sensor_adc_val;
 358         enum meson_sar_adc_chan7_mux_sel        chan7_mux_sel;
 359 };
 360
 361 static const struct regmap_config meson_sar_adc_regmap_config_gxbb = {
 362         .reg_bits = 8,
 363         .val_bits = 32,
 364         .reg_stride = 4,
 365         .max_register = MESON_SAR_ADC_REG13,
 366 };
 367
 368 static const struct regmap_config meson_sar_adc_regmap_config_meson8 = {
 369         .reg_bits = 8,
 370         .val_bits = 32,
 371         .reg_stride = 4,
 372         .max_register = MESON_SAR_ADC_DELTA_10,
 373 };
 374
 375 static const struct iio_chan_spec *
 376 find_channel_by_num(struct iio_dev *indio_dev, int num)
 377 {
 378         int i;
 379
 380         for (i = 0; i < indio_dev->num_channels; i++)
 381                 if (indio_dev->channels[i].channel == num)
 382                         return &indio_dev->channels[i];
 383         return NULL;
 384 }
 385
 386 static unsigned int meson_sar_adc_get_fifo_count(struct iio_dev *indio_dev)
 387 {
 388         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 389         u32 regval;
 390
 391         regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
 392
 393         return FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
 394 }
 395
 396 static int meson_sar_adc_calib_val(struct iio_dev *indio_dev, int val)
 397 {
 398         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 399         int tmp;
 400
 401         /* use val_calib = scale * val_raw + offset calibration function */
 402         tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;
 403
 404         return clamp(tmp, 0, (1 << priv->param->resolution) - 1);
 405 }
 406
 407 static int meson_sar_adc_wait_busy_clear(struct iio_dev *indio_dev)
 408 {
 409         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 410         int val;
 411
 412         /*
 413          * NOTE: we need a small delay before reading the status, otherwise
 414          * the sample engine may not have started internally (which would
 415          * seem to us that sampling is already finished).
 416          */
 417         udelay(1);
 418         return regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_REG0, val,
 419                                                !FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, val),
 420                                                1, 10000);
 421 }
 422
 423 static void meson_sar_adc_set_chan7_mux(struct iio_dev *indio_dev,
 424                                         enum meson_sar_adc_chan7_mux_sel sel)
 425 {
 426         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 427         u32 regval;
 428
 429         regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, sel);
 430         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 431                            MESON_SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK, regval);
 432
 433         usleep_range(10, 20);
 434
 435         priv->chan7_mux_sel = sel;
 436 }
 437
 438 static int meson_sar_adc_read_raw_sample(struct iio_dev *indio_dev,
 439                                          const struct iio_chan_spec *chan,
 440                                          int *val)
 441 {
 442         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 443         struct device *dev = indio_dev->dev.parent;
 444         int regval, fifo_chan, fifo_val, count;
 445
 446         if (!wait_for_completion_timeout(&priv->done,
 447                                 msecs_to_jiffies(MESON_SAR_ADC_TIMEOUT)))
 448                 return -ETIMEDOUT;
 449
 450         count = meson_sar_adc_get_fifo_count(indio_dev);
 451         if (count != 1) {
 452                 dev_err(dev, "ADC FIFO has %d element(s) instead of one\n", count);
 453                 return -EINVAL;
 454         }
 455
 456         regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);
 457         fifo_chan = FIELD_GET(MESON_SAR_ADC_FIFO_RD_CHAN_ID_MASK, regval);
 458         if (fifo_chan != chan->address) {
 459                 dev_err(dev, "ADC FIFO entry belongs to channel %d instead of %lu\n",
 460                         fifo_chan, chan->address);
 461                 return -EINVAL;
 462         }
 463
 464         fifo_val = FIELD_GET(MESON_SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK, regval);
 465         fifo_val &= GENMASK(priv->param->resolution - 1, 0);
 466         *val = meson_sar_adc_calib_val(indio_dev, fifo_val);
 467
 468         return 0;
 469 }
 470
 471 static void meson_sar_adc_set_averaging(struct iio_dev *indio_dev,
 472                                         const struct iio_chan_spec *chan,
 473                                         enum meson_sar_adc_avg_mode mode,
 474                                         enum meson_sar_adc_num_samples samples)
 475 {
 476         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 477         int val, address = chan->address;
 478
 479         val = samples << MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(address);
 480         regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
 481                            MESON_SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(address),
 482                            val);
 483
 484         val = mode << MESON_SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(address);
 485         regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,
 486                            MESON_SAR_ADC_AVG_CNTL_AVG_MODE_MASK(address), val);
 487 }
 488
 489 static void meson_sar_adc_enable_channel(struct iio_dev *indio_dev,
 490                                         const struct iio_chan_spec *chan)
 491 {
 492         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 493         u32 regval;
 494
 495         /*
 496          * the SAR ADC engine allows sampling multiple channels at the same
 497          * time. to keep it simple we're only working with one *internal*
 498          * channel, which starts counting at index 0 (which means: count = 1).
 499          */
 500         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, 0);
 501         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
 502                            MESON_SAR_ADC_CHAN_LIST_MAX_INDEX_MASK, regval);
 503
 504         /* map channel index 0 to the channel which we want to read */
 505         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0),
 506                             chan->address);
 507         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,
 508                            MESON_SAR_ADC_CHAN_LIST_ENTRY_MASK(0), regval);
 509
 510         regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
 511                             chan->address);
 512         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
 513                            MESON_SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK,
 514                            regval);
 515
 516         regval = FIELD_PREP(MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
 517                             chan->address);
 518         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,
 519                            MESON_SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK,
 520                            regval);
 521
 522         if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_TEMP_CHANNEL) {
 523                 if (chan->type == IIO_TEMP)
 524                         regval = MESON_SAR_ADC_DELTA_10_TEMP_SEL;
 525                 else
 526                         regval = 0;
 527
 528                 regmap_update_bits(priv->regmap,
 529                                    MESON_SAR_ADC_DELTA_10,
 530                                    MESON_SAR_ADC_DELTA_10_TEMP_SEL, regval);
 531         } else if (chan->address == MESON_SAR_ADC_VOLTAGE_AND_MUX_CHANNEL) {
 532                 enum meson_sar_adc_chan7_mux_sel sel;
 533
 534                 if (chan->channel == NUM_CHAN_7)
 535                         sel = CHAN7_MUX_CH7_INPUT;
 536                 else
 537                         sel = chan7_mux_values[chan->channel - NUM_MUX_0_VSS];
 538                 if (sel != priv->chan7_mux_sel)
 539                         meson_sar_adc_set_chan7_mux(indio_dev, sel);
 540         }
 541 }
 542
 543 static void meson_sar_adc_start_sample_engine(struct iio_dev *indio_dev)
 544 {
 545         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 546
 547         reinit_completion(&priv->done);
 548
 549         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 550                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN,
 551                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN);
 552
 553         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 554                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
 555                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
 556
 557         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 558                            MESON_SAR_ADC_REG0_SAMPLING_START,
 559                            MESON_SAR_ADC_REG0_SAMPLING_START);
 560 }
 561
 562 static void meson_sar_adc_stop_sample_engine(struct iio_dev *indio_dev)
 563 {
 564         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 565
 566         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 567                            MESON_SAR_ADC_REG0_FIFO_IRQ_EN, 0);
 568
 569         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 570                            MESON_SAR_ADC_REG0_SAMPLING_STOP,
 571                            MESON_SAR_ADC_REG0_SAMPLING_STOP);
 572
 573         /* wait until all modules are stopped */
 574         meson_sar_adc_wait_busy_clear(indio_dev);
 575
 576         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 577                            MESON_SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
 578 }
 579
 580 static int meson_sar_adc_lock(struct iio_dev *indio_dev)
 581 {
 582         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 583         int val, ret;
 584
 585         mutex_lock(&priv->lock);
 586
 587         if (priv->param->has_bl30_integration) {
 588                 /* prevent BL30 from using the SAR ADC while we are using it */
 589                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 590                                    MESON_SAR_ADC_DELAY_KERNEL_BUSY,
 591                                    MESON_SAR_ADC_DELAY_KERNEL_BUSY);
 592
 593                 udelay(1);
 594
 595                 /*
 596                  * wait until BL30 releases it's lock (so we can use the SAR
 597                  * ADC)
 598                  */
 599                 ret = regmap_read_poll_timeout_atomic(priv->regmap, MESON_SAR_ADC_DELAY, val,
 600                                                       !(val & MESON_SAR_ADC_DELAY_BL30_BUSY),
 601                                                       1, 10000);
 602                 if (ret) {
 603                         mutex_unlock(&priv->lock);
 604                         return ret;
 605                 }
 606         }
 607
 608         return 0;
 609 }
 610
 611 static void meson_sar_adc_unlock(struct iio_dev *indio_dev)
 612 {
 613         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 614
 615         if (priv->param->has_bl30_integration)
 616                 /* allow BL30 to use the SAR ADC again */
 617                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 618                                    MESON_SAR_ADC_DELAY_KERNEL_BUSY, 0);
 619
 620         mutex_unlock(&priv->lock);
 621 }
 622
 623 static void meson_sar_adc_clear_fifo(struct iio_dev *indio_dev)
 624 {
 625         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 626         unsigned int count, tmp;
 627
 628         for (count = 0; count < MESON_SAR_ADC_MAX_FIFO_SIZE; count++) {
 629                 if (!meson_sar_adc_get_fifo_count(indio_dev))
 630                         break;
 631
 632                 regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);
 633         }
 634 }
 635
 636 static int meson_sar_adc_get_sample(struct iio_dev *indio_dev,
 637                                     const struct iio_chan_spec *chan,
 638                                     enum meson_sar_adc_avg_mode avg_mode,
 639                                     enum meson_sar_adc_num_samples avg_samples,
 640                                     int *val)
 641 {
 642         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 643         struct device *dev = indio_dev->dev.parent;
 644         int ret;
 645
 646         if (chan->type == IIO_TEMP && !priv->temperature_sensor_calibrated)
 647                 return -ENOTSUPP;
 648
 649         ret = meson_sar_adc_lock(indio_dev);
 650         if (ret)
 651                 return ret;
 652
 653         /* clear the FIFO to make sure we're not reading old values */
 654         meson_sar_adc_clear_fifo(indio_dev);
 655
 656         meson_sar_adc_set_averaging(indio_dev, chan, avg_mode, avg_samples);
 657
 658         meson_sar_adc_enable_channel(indio_dev, chan);
 659
 660         meson_sar_adc_start_sample_engine(indio_dev);
 661         ret = meson_sar_adc_read_raw_sample(indio_dev, chan, val);
 662         meson_sar_adc_stop_sample_engine(indio_dev);
 663
 664         meson_sar_adc_unlock(indio_dev);
 665
 666         if (ret) {
 667                 dev_warn(dev, "failed to read sample for channel %lu: %d\n",
 668                          chan->address, ret);
 669                 return ret;
 670         }
 671
 672         return IIO_VAL_INT;
 673 }
 674
 675 static int meson_sar_adc_iio_info_read_raw(struct iio_dev *indio_dev,
 676                                            const struct iio_chan_spec *chan,
 677                                            int *val, int *val2, long mask)
 678 {
 679         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 680         struct device *dev = indio_dev->dev.parent;
 681         int ret;
 682
 683         switch (mask) {
 684         case IIO_CHAN_INFO_RAW:
 685                 return meson_sar_adc_get_sample(indio_dev, chan, NO_AVERAGING,
 686                                                 ONE_SAMPLE, val);
 687
 688         case IIO_CHAN_INFO_AVERAGE_RAW:
 689                 return meson_sar_adc_get_sample(indio_dev, chan,
 690                                                 MEAN_AVERAGING, EIGHT_SAMPLES,
 691                                                 val);
 692
 693         case IIO_CHAN_INFO_SCALE:
 694                 if (chan->type == IIO_VOLTAGE) {
 695                         ret = regulator_get_voltage(priv->vref);
 696                         if (ret < 0) {
 697                                 dev_err(dev, "failed to get vref voltage: %d\n", ret);
 698                                 return ret;
 699                         }
 700
 701                         *val = ret / 1000;
 702                         *val2 = priv->param->resolution;
 703                         return IIO_VAL_FRACTIONAL_LOG2;
 704                 } else if (chan->type == IIO_TEMP) {
 705                         /* SoC specific multiplier and divider */
 706                         *val = priv->param->temperature_multiplier;
 707                         *val2 = priv->param->temperature_divider;
 708
 709                         /* celsius to millicelsius */
 710                         *val *= 1000;
 711
 712                         return IIO_VAL_FRACTIONAL;
 713                 } else {
 714                         return -EINVAL;
 715                 }
 716
 717         case IIO_CHAN_INFO_CALIBBIAS:
 718                 *val = priv->calibbias;
 719                 return IIO_VAL_INT;
 720
 721         case IIO_CHAN_INFO_CALIBSCALE:
 722                 *val = priv->calibscale / MILLION;
 723                 *val2 = priv->calibscale % MILLION;
 724                 return IIO_VAL_INT_PLUS_MICRO;
 725
 726         case IIO_CHAN_INFO_OFFSET:
 727                 *val = DIV_ROUND_CLOSEST(MESON_SAR_ADC_TEMP_OFFSET *
 728                                          priv->param->temperature_divider,
 729                                          priv->param->temperature_multiplier);
 730                 *val -= priv->temperature_sensor_adc_val;
 731                 return IIO_VAL_INT;
 732
 733         default:
 734                 return -EINVAL;
 735         }
 736 }
 737
 738 static int meson_sar_adc_clk_init(struct iio_dev *indio_dev,
 739                                   void __iomem *base)
 740 {
 741         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 742         struct device *dev = indio_dev->dev.parent;
 743         struct clk_init_data init;
 744         const char *clk_parents[1];
 745
 746         init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_div", dev_name(dev));
 747         if (!init.name)
 748                 return -ENOMEM;
 749
 750         init.flags = 0;
 751         init.ops = &clk_divider_ops;
 752         clk_parents[0] = __clk_get_name(priv->clkin);
 753         init.parent_names = clk_parents;
 754         init.num_parents = 1;
 755
 756         priv->clk_div.reg = base + MESON_SAR_ADC_REG3;
 757         priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;
 758         priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;
 759         priv->clk_div.hw.init = &init;
 760         priv->clk_div.flags = 0;
 761
 762         priv->adc_div_clk = devm_clk_register(dev, &priv->clk_div.hw);
 763         if (WARN_ON(IS_ERR(priv->adc_div_clk)))
 764                 return PTR_ERR(priv->adc_div_clk);
 765
 766         init.name = devm_kasprintf(dev, GFP_KERNEL, "%s#adc_en", dev_name(dev));
 767         if (!init.name)
 768                 return -ENOMEM;
 769
 770         init.flags = CLK_SET_RATE_PARENT;
 771         init.ops = &clk_gate_ops;
 772         clk_parents[0] = __clk_get_name(priv->adc_div_clk);
 773         init.parent_names = clk_parents;
 774         init.num_parents = 1;
 775
 776         priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;
 777         priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);
 778         priv->clk_gate.hw.init = &init;
 779
 780         priv->adc_clk = devm_clk_register(dev, &priv->clk_gate.hw);
 781         if (WARN_ON(IS_ERR(priv->adc_clk)))
 782                 return PTR_ERR(priv->adc_clk);
 783
 784         return 0;
 785 }
 786
 787 static int meson_sar_adc_temp_sensor_init(struct iio_dev *indio_dev)
 788 {
 789         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 790         u8 *buf, trimming_bits, trimming_mask, upper_adc_val;
 791         struct device *dev = indio_dev->dev.parent;
 792         struct nvmem_cell *temperature_calib;
 793         size_t read_len;
 794         int ret;
 795
 796         temperature_calib = devm_nvmem_cell_get(dev, "temperature_calib");
 797         if (IS_ERR(temperature_calib)) {
 798                 ret = PTR_ERR(temperature_calib);
 799
 800                 /*
 801                  * leave the temperature sensor disabled if no calibration data
 802                  * was passed via nvmem-cells.
 803                  */
 804                 if (ret == -ENODEV)
 805                         return 0;
 806
 807                 return dev_err_probe(dev, ret, "failed to get temperature_calib cell\n");
 808         }
 809
 810         priv->tsc_regmap = syscon_regmap_lookup_by_phandle(dev->of_node, "amlogic,hhi-sysctrl");
 811         if (IS_ERR(priv->tsc_regmap))
 812                 return dev_err_probe(dev, PTR_ERR(priv->tsc_regmap),
 813                                      "failed to get amlogic,hhi-sysctrl regmap\n");
 814
 815         read_len = MESON_SAR_ADC_EFUSE_BYTES;
 816         buf = nvmem_cell_read(temperature_calib, &read_len);
 817         if (IS_ERR(buf))
 818                 return dev_err_probe(dev, PTR_ERR(buf), "failed to read temperature_calib cell\n");
 819         if (read_len != MESON_SAR_ADC_EFUSE_BYTES) {
 820                 kfree(buf);
 821                 return dev_err_probe(dev, -EINVAL, "invalid read size of temperature_calib cell\n");
 822         }
 823
 824         trimming_bits = priv->param->temperature_trimming_bits;
 825         trimming_mask = BIT(trimming_bits) - 1;
 826
 827         priv->temperature_sensor_calibrated =
 828                 buf[3] & MESON_SAR_ADC_EFUSE_BYTE3_IS_CALIBRATED;
 829         priv->temperature_sensor_coefficient = buf[2] & trimming_mask;
 830
 831         upper_adc_val = FIELD_GET(MESON_SAR_ADC_EFUSE_BYTE3_UPPER_ADC_VAL,
 832                                   buf[3]);
 833
 834         priv->temperature_sensor_adc_val = buf[2];
 835         priv->temperature_sensor_adc_val |= upper_adc_val << BITS_PER_BYTE;
 836         priv->temperature_sensor_adc_val >>= trimming_bits;
 837
 838         kfree(buf);
 839
 840         return 0;
 841 }
 842
 843 static int meson_sar_adc_init(struct iio_dev *indio_dev)
 844 {
 845         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
 846         struct device *dev = indio_dev->dev.parent;
 847         int regval, i, ret;
 848
 849         /*
 850          * make sure we start at CH7 input since the other muxes are only used
 851          * for internal calibration.
 852          */
 853         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
 854
 855         if (priv->param->has_bl30_integration) {
 856                 /*
 857                  * leave sampling delay and the input clocks as configured by
 858                  * BL30 to make sure BL30 gets the values it expects when
 859                  * reading the temperature sensor.
 860                  */
 861                 regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);
 862                 if (regval & MESON_SAR_ADC_REG3_BL30_INITIALIZED)
 863                         return 0;
 864         }
 865
 866         meson_sar_adc_stop_sample_engine(indio_dev);
 867
 868         /*
 869          * disable this bit as seems to be only relevant for Meson6 (based
 870          * on the vendor driver), which we don't support at the moment.
 871          */
 872         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
 873                            MESON_SAR_ADC_REG0_ADC_TEMP_SEN_SEL, 0);
 874
 875         /* disable all channels by default */
 876         regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);
 877
 878         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 879                            MESON_SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE, 0);
 880         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 881                            MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY,
 882                            MESON_SAR_ADC_REG3_CNTL_USE_SC_DLY);
 883
 884         /* delay between two samples = (10+1) * 1uS */
 885         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 886                            MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 887                            FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK,
 888                                       10));
 889         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 890                            MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
 891                            FIELD_PREP(MESON_SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK,
 892                                       0));
 893
 894         /* delay between two samples = (10+1) * 1uS */
 895         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 896                            MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 897                            FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_CNT_MASK,
 898                                       10));
 899         regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,
 900                            MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
 901                            FIELD_PREP(MESON_SAR_ADC_DELAY_INPUT_DLY_SEL_MASK,
 902                                       1));
 903
 904         /*
 905          * set up the input channel muxes in MESON_SAR_ADC_CHAN_10_SW
 906          * (0 = SAR_ADC_CH0, 1 = SAR_ADC_CH1)
 907          */
 908         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK, 0);
 909         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 910                            MESON_SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK,
 911                            regval);
 912         regval = FIELD_PREP(MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK, 1);
 913         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 914                            MESON_SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK,
 915                            regval);
 916
 917         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 918                            MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW,
 919                            MESON_SAR_ADC_CHAN_10_SW_CHAN0_XP_DRIVE_SW);
 920
 921         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 922                            MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW,
 923                            MESON_SAR_ADC_CHAN_10_SW_CHAN0_YP_DRIVE_SW);
 924
 925         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 926                            MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW,
 927                            MESON_SAR_ADC_CHAN_10_SW_CHAN1_XP_DRIVE_SW);
 928
 929         regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,
 930                            MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW,
 931                            MESON_SAR_ADC_CHAN_10_SW_CHAN1_YP_DRIVE_SW);
 932
 933         /*
 934          * set up the input channel muxes in MESON_SAR_ADC_AUX_SW
 935          * (2 = SAR_ADC_CH2, 3 = SAR_ADC_CH3, ...) and enable
 936          * MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW and
 937          * MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW like the vendor driver.
 938          */
 939         regval = 0;
 940         for (i = 2; i <= 7; i++)
 941                 regval |= i << MESON_SAR_ADC_AUX_SW_MUX_SEL_CHAN_SHIFT(i);
 942         regval |= MESON_SAR_ADC_AUX_SW_YP_DRIVE_SW;
 943         regval |= MESON_SAR_ADC_AUX_SW_XP_DRIVE_SW;
 944         regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);
 945
 946         if (priv->temperature_sensor_calibrated) {
 947                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 948                                    MESON_SAR_ADC_DELTA_10_TS_REVE1,
 949                                    MESON_SAR_ADC_DELTA_10_TS_REVE1);
 950                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 951                                    MESON_SAR_ADC_DELTA_10_TS_REVE0,
 952                                    MESON_SAR_ADC_DELTA_10_TS_REVE0);
 953
 954                 /*
 955                  * set bits [3:0] of the TSC (temperature sensor coefficient)
 956                  * to get the correct values when reading the temperature.
 957                  */
 958                 regval = FIELD_PREP(MESON_SAR_ADC_DELTA_10_TS_C_MASK,
 959                                     priv->temperature_sensor_coefficient);
 960                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 961                                    MESON_SAR_ADC_DELTA_10_TS_C_MASK, regval);
 962
 963                 if (priv->param->temperature_trimming_bits == 5) {
 964                         if (priv->temperature_sensor_coefficient & BIT(4))
 965                                 regval = MESON_HHI_DPLL_TOP_0_TSC_BIT4;
 966                         else
 967                                 regval = 0;
 968
 969                         /*
 970                          * bit [4] (the 5th bit when starting to count at 1)
 971                          * of the TSC is located in the HHI register area.
 972                          */
 973                         regmap_update_bits(priv->tsc_regmap,
 974                                            MESON_HHI_DPLL_TOP_0,
 975                                            MESON_HHI_DPLL_TOP_0_TSC_BIT4,
 976                                            regval);
 977                 }
 978         } else {
 979                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 980                                    MESON_SAR_ADC_DELTA_10_TS_REVE1, 0);
 981                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,
 982                                    MESON_SAR_ADC_DELTA_10_TS_REVE0, 0);
 983         }
 984
 985         regval = FIELD_PREP(MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
 986                             priv->param->disable_ring_counter);
 987         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
 988                            MESON_SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN,
 989                            regval);
 990
 991         if (priv->param->has_reg11) {
 992                 regval = FIELD_PREP(MESON_SAR_ADC_REG11_EOC, priv->param->adc_eoc);
 993                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
 994                                    MESON_SAR_ADC_REG11_EOC, regval);
 995
 996                 if (priv->param->has_vref_select) {
 997                         regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_SEL,
 998                                             priv->param->vref_select);
 999                         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
1000                                            MESON_SAR_ADC_REG11_VREF_SEL, regval);
1001                 }
1002
1003                 regval = FIELD_PREP(MESON_SAR_ADC_REG11_VREF_VOLTAGE,
1004                                     priv->param->vref_volatge);
1005                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
1006                                    MESON_SAR_ADC_REG11_VREF_VOLTAGE, regval);
1007
1008                 regval = FIELD_PREP(MESON_SAR_ADC_REG11_CMV_SEL,
1009                                     priv->param->cmv_select);
1010                 regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG11,
1011                                    MESON_SAR_ADC_REG11_CMV_SEL, regval);
1012         }
1013
1014         ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);
1015         if (ret)
1016                 return dev_err_probe(dev, ret, "failed to set adc parent to clkin\n");
1017
1018         ret = clk_set_rate(priv->adc_clk, priv->param->clock_rate);
1019         if (ret)
1020                 return dev_err_probe(dev, ret, "failed to set adc clock rate\n");
1021
1022         return 0;
1023 }
1024
1025 static void meson_sar_adc_set_bandgap(struct iio_dev *indio_dev, bool on_off)
1026 {
1027         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1028         const struct meson_sar_adc_param *param = priv->param;
1029         u32 enable_mask;
1030
1031         if (param->bandgap_reg == MESON_SAR_ADC_REG11)
1032                 enable_mask = MESON_SAR_ADC_REG11_BANDGAP_EN;
1033         else
1034                 enable_mask = MESON_SAR_ADC_DELTA_10_TS_VBG_EN;
1035
1036         regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,
1037                            on_off ? enable_mask : 0);
1038 }
1039
1040 static int meson_sar_adc_hw_enable(struct iio_dev *indio_dev)
1041 {
1042         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1043         struct device *dev = indio_dev->dev.parent;
1044         int ret;
1045         u32 regval;
1046
1047         ret = meson_sar_adc_lock(indio_dev);
1048         if (ret) {
1049                 dev_err(dev, "failed to lock adc\n");
1050                 goto err_lock;
1051         }
1052
1053         ret = regulator_enable(priv->vref);
1054         if (ret < 0) {
1055                 dev_err(dev, "failed to enable vref regulator\n");
1056                 goto err_vref;
1057         }
1058
1059         regval = FIELD_PREP(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, 1);
1060         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,
1061                            MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
1062
1063         meson_sar_adc_set_bandgap(indio_dev, true);
1064
1065         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
1066                            MESON_SAR_ADC_REG3_ADC_EN,
1067                            MESON_SAR_ADC_REG3_ADC_EN);
1068
1069         udelay(5);
1070
1071         ret = clk_prepare_enable(priv->adc_clk);
1072         if (ret) {
1073                 dev_err(dev, "failed to enable adc clk\n");
1074                 goto err_adc_clk;
1075         }
1076
1077         meson_sar_adc_unlock(indio_dev);
1078
1079         return 0;
1080
1081 err_adc_clk:
1082         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
1083                            MESON_SAR_ADC_REG3_ADC_EN, 0);
1084         meson_sar_adc_set_bandgap(indio_dev, false);
1085         regulator_disable(priv->vref);
1086 err_vref:
1087         meson_sar_adc_unlock(indio_dev);
1088 err_lock:
1089         return ret;
1090 }
1091
1092 static void meson_sar_adc_hw_disable(struct iio_dev *indio_dev)
1093 {
1094         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1095         int ret;
1096
1097         /*
1098          * If taking the lock fails we have to assume that BL30 is broken. The
1099          * best we can do then is to release the resources anyhow.
1100          */
1101         ret = meson_sar_adc_lock(indio_dev);
1102         if (ret)
1103                 dev_err(indio_dev->dev.parent, "Failed to lock ADC (%pE)\n", ERR_PTR(ret));
1104
1105         clk_disable_unprepare(priv->adc_clk);
1106
1107         regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,
1108                            MESON_SAR_ADC_REG3_ADC_EN, 0);
1109
1110         meson_sar_adc_set_bandgap(indio_dev, false);
1111
1112         regulator_disable(priv->vref);
1113
1114         if (!ret)
1115                 meson_sar_adc_unlock(indio_dev);
1116 }
1117
1118 static irqreturn_t meson_sar_adc_irq(int irq, void *data)
1119 {
1120         struct iio_dev *indio_dev = data;
1121         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1122         unsigned int cnt, threshold;
1123         u32 regval;
1124
1125         regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);
1126         cnt = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_COUNT_MASK, regval);
1127         threshold = FIELD_GET(MESON_SAR_ADC_REG0_FIFO_CNT_IRQ_MASK, regval);
1128
1129         if (cnt < threshold)
1130                 return IRQ_NONE;
1131
1132         complete(&priv->done);
1133
1134         return IRQ_HANDLED;
1135 }
1136
1137 static int meson_sar_adc_calib(struct iio_dev *indio_dev)
1138 {
1139         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1140         int ret, nominal0, nominal1, value0, value1;
1141
1142         /* use points 25% and 75% for calibration */
1143         nominal0 = (1 << priv->param->resolution) / 4;
1144         nominal1 = (1 << priv->param->resolution) * 3 / 4;
1145
1146         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_DIV4);
1147         usleep_range(10, 20);
1148         ret = meson_sar_adc_get_sample(indio_dev,
1149                                        find_channel_by_num(indio_dev,
1150                                                            NUM_MUX_1_VDD_DIV4),
1151                                        MEAN_AVERAGING, EIGHT_SAMPLES, &value0);
1152         if (ret < 0)
1153                 goto out;
1154
1155         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_VDD_MUL3_DIV4);
1156         usleep_range(10, 20);
1157         ret = meson_sar_adc_get_sample(indio_dev,
1158                                        find_channel_by_num(indio_dev,
1159                                                            NUM_MUX_3_VDD_MUL3_DIV4),
1160                                        MEAN_AVERAGING, EIGHT_SAMPLES, &value1);
1161         if (ret < 0)
1162                 goto out;
1163
1164         if (value1 <= value0) {
1165                 ret = -EINVAL;
1166                 goto out;
1167         }
1168
1169         priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,
1170                                    value1 - value0);
1171         priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,
1172                                              MILLION);
1173         ret = 0;
1174 out:
1175         meson_sar_adc_set_chan7_mux(indio_dev, CHAN7_MUX_CH7_INPUT);
1176
1177         return ret;
1178 }
1179
1180 static int read_label(struct iio_dev *indio_dev,
1181                       struct iio_chan_spec const *chan,
1182                       char *label)
1183 {
1184         if (chan->type == IIO_TEMP)
1185                 return sprintf(label, "temp-sensor\n");
1186         if (chan->type == IIO_VOLTAGE && chan->channel >= NUM_MUX_0_VSS)
1187                 return sprintf(label, "%s\n",
1188                                chan7_mux_names[chan->channel - NUM_MUX_0_VSS]);
1189         if (chan->type == IIO_VOLTAGE)
1190                 return sprintf(label, "channel-%d\n", chan->channel);
1191         return 0;
1192 }
1193
1194 static const struct iio_info meson_sar_adc_iio_info = {
1195         .read_raw = meson_sar_adc_iio_info_read_raw,
1196         .read_label = read_label,
1197 };
1198
1199 static const struct meson_sar_adc_param meson_sar_adc_meson8_param = {
1200         .has_bl30_integration = false,
1201         .clock_rate = 1150000,
1202         .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1203         .regmap_config = &meson_sar_adc_regmap_config_meson8,
1204         .resolution = 10,
1205         .temperature_trimming_bits = 4,
1206         .temperature_multiplier = 18 * 10000,
1207         .temperature_divider = 1024 * 10 * 85,
1208 };
1209
1210 static const struct meson_sar_adc_param meson_sar_adc_meson8b_param = {
1211         .has_bl30_integration = false,
1212         .clock_rate = 1150000,
1213         .bandgap_reg = MESON_SAR_ADC_DELTA_10,
1214         .regmap_config = &meson_sar_adc_regmap_config_meson8,
1215         .resolution = 10,
1216         .temperature_trimming_bits = 5,
1217         .temperature_multiplier = 10,
1218         .temperature_divider = 32,
1219 };
1220
1221 static const struct meson_sar_adc_param meson_sar_adc_gxbb_param = {
1222         .has_bl30_integration = true,
1223         .clock_rate = 1200000,
1224         .bandgap_reg = MESON_SAR_ADC_REG11,
1225         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1226         .resolution = 10,
1227         .has_reg11 = true,
1228         .vref_volatge = 1,
1229         .cmv_select = 1,
1230 };
1231
1232 static const struct meson_sar_adc_param meson_sar_adc_gxl_param = {
1233         .has_bl30_integration = true,
1234         .clock_rate = 1200000,
1235         .bandgap_reg = MESON_SAR_ADC_REG11,
1236         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1237         .resolution = 12,
1238         .disable_ring_counter = 1,
1239         .has_reg11 = true,
1240         .vref_volatge = 1,
1241         .cmv_select = 1,
1242 };
1243
1244 static const struct meson_sar_adc_param meson_sar_adc_axg_param = {
1245         .has_bl30_integration = true,
1246         .clock_rate = 1200000,
1247         .bandgap_reg = MESON_SAR_ADC_REG11,
1248         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1249         .resolution = 12,
1250         .disable_ring_counter = 1,
1251         .has_reg11 = true,
1252         .vref_volatge = 1,
1253         .has_vref_select = true,
1254         .vref_select = VREF_VDDA,
1255         .cmv_select = 1,
1256 };
1257
1258 static const struct meson_sar_adc_param meson_sar_adc_g12a_param = {
1259         .has_bl30_integration = false,
1260         .clock_rate = 1200000,
1261         .bandgap_reg = MESON_SAR_ADC_REG11,
1262         .regmap_config = &meson_sar_adc_regmap_config_gxbb,
1263         .resolution = 12,
1264         .disable_ring_counter = 1,
1265         .has_reg11 = true,
1266         .adc_eoc = 1,
1267         .has_vref_select = true,
1268         .vref_select = VREF_VDDA,
1269 };
1270
1271 static const struct meson_sar_adc_data meson_sar_adc_meson8_data = {
1272         .param = &meson_sar_adc_meson8_param,
1273         .name = "meson-meson8-saradc",
1274 };
1275
1276 static const struct meson_sar_adc_data meson_sar_adc_meson8b_data = {
1277         .param = &meson_sar_adc_meson8b_param,
1278         .name = "meson-meson8b-saradc",
1279 };
1280
1281 static const struct meson_sar_adc_data meson_sar_adc_meson8m2_data = {
1282         .param = &meson_sar_adc_meson8b_param,
1283         .name = "meson-meson8m2-saradc",
1284 };
1285
1286 static const struct meson_sar_adc_data meson_sar_adc_gxbb_data = {
1287         .param = &meson_sar_adc_gxbb_param,
1288         .name = "meson-gxbb-saradc",
1289 };
1290
1291 static const struct meson_sar_adc_data meson_sar_adc_gxl_data = {
1292         .param = &meson_sar_adc_gxl_param,
1293         .name = "meson-gxl-saradc",
1294 };
1295
1296 static const struct meson_sar_adc_data meson_sar_adc_gxm_data = {
1297         .param = &meson_sar_adc_gxl_param,
1298         .name = "meson-gxm-saradc",
1299 };
1300
1301 static const struct meson_sar_adc_data meson_sar_adc_axg_data = {
1302         .param = &meson_sar_adc_axg_param,
1303         .name = "meson-axg-saradc",
1304 };
1305
1306 static const struct meson_sar_adc_data meson_sar_adc_g12a_data = {
1307         .param = &meson_sar_adc_g12a_param,
1308         .name = "meson-g12a-saradc",
1309 };
1310
1311 static const struct of_device_id meson_sar_adc_of_match[] = {
1312         {
1313                 .compatible = "amlogic,meson8-saradc",
1314                 .data = &meson_sar_adc_meson8_data,
1315         }, {
1316                 .compatible = "amlogic,meson8b-saradc",
1317                 .data = &meson_sar_adc_meson8b_data,
1318         }, {
1319                 .compatible = "amlogic,meson8m2-saradc",
1320                 .data = &meson_sar_adc_meson8m2_data,
1321         }, {
1322                 .compatible = "amlogic,meson-gxbb-saradc",
1323                 .data = &meson_sar_adc_gxbb_data,
1324         }, {
1325                 .compatible = "amlogic,meson-gxl-saradc",
1326                 .data = &meson_sar_adc_gxl_data,
1327         }, {
1328                 .compatible = "amlogic,meson-gxm-saradc",
1329                 .data = &meson_sar_adc_gxm_data,
1330         }, {
1331                 .compatible = "amlogic,meson-axg-saradc",
1332                 .data = &meson_sar_adc_axg_data,
1333         }, {
1334                 .compatible = "amlogic,meson-g12a-saradc",
1335                 .data = &meson_sar_adc_g12a_data,
1336         },
1337         { /* sentinel */ }
1338 };
1339 MODULE_DEVICE_TABLE(of, meson_sar_adc_of_match);
1340
1341 static int meson_sar_adc_probe(struct platform_device *pdev)
1342 {
1343         const struct meson_sar_adc_data *match_data;
1344         struct meson_sar_adc_priv *priv;
1345         struct device *dev = &pdev->dev;
1346         struct iio_dev *indio_dev;
1347         void __iomem *base;
1348         int irq, ret;
1349
1350         indio_dev = devm_iio_device_alloc(dev, sizeof(*priv));
1351         if (!indio_dev)
1352                 return dev_err_probe(dev, -ENOMEM, "failed allocating iio device\n");
1353
1354         priv = iio_priv(indio_dev);
1355         init_completion(&priv->done);
1356
1357         match_data = of_device_get_match_data(dev);
1358         if (!match_data)
1359                 return dev_err_probe(dev, -ENODEV, "failed to get match data\n");
1360
1361         priv->param = match_data->param;
1362
1363         indio_dev->name = match_data->name;
1364         indio_dev->modes = INDIO_DIRECT_MODE;
1365         indio_dev->info = &meson_sar_adc_iio_info;
1366
1367         base = devm_platform_ioremap_resource(pdev, 0);
1368         if (IS_ERR(base))
1369                 return PTR_ERR(base);
1370
1371         priv->regmap = devm_regmap_init_mmio(dev, base, priv->param->regmap_config);
1372         if (IS_ERR(priv->regmap))
1373                 return dev_err_probe(dev, PTR_ERR(priv->regmap), "failed to init regmap\n");
1374
1375         irq = irq_of_parse_and_map(dev->of_node, 0);
1376         if (!irq)
1377                 return dev_err_probe(dev, -EINVAL, "failed to get irq\n");
1378
1379         ret = devm_request_irq(dev, irq, meson_sar_adc_irq, IRQF_SHARED, dev_name(dev), indio_dev);
1380         if (ret)
1381                 return dev_err_probe(dev, ret, "failed to request irq\n");
1382
1383         priv->clkin = devm_clk_get(dev, "clkin");
1384         if (IS_ERR(priv->clkin))
1385                 return dev_err_probe(dev, PTR_ERR(priv->clkin), "failed to get clkin\n");
1386
1387         priv->core_clk = devm_clk_get_enabled(dev, "core");
1388         if (IS_ERR(priv->core_clk))
1389                 return dev_err_probe(dev, PTR_ERR(priv->core_clk), "failed to get core clk\n");
1390
1391         priv->adc_clk = devm_clk_get_optional(dev, "adc_clk");
1392         if (IS_ERR(priv->adc_clk))
1393                 return dev_err_probe(dev, PTR_ERR(priv->adc_clk), "failed to get adc clk\n");
1394
1395         priv->adc_sel_clk = devm_clk_get_optional(dev, "adc_sel");
1396         if (IS_ERR(priv->adc_sel_clk))
1397                 return dev_err_probe(dev, PTR_ERR(priv->adc_sel_clk), "failed to get adc_sel clk\n");
1398
1399         /* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */
1400         if (!priv->adc_clk) {
1401                 ret = meson_sar_adc_clk_init(indio_dev, base);
1402                 if (ret)
1403                         return dev_err_probe(dev, ret, "failed to init internal clk\n");
1404         }
1405
1406         priv->vref = devm_regulator_get(dev, "vref");
1407         if (IS_ERR(priv->vref))
1408                 return dev_err_probe(dev, PTR_ERR(priv->vref), "failed to get vref regulator\n");
1409
1410         priv->calibscale = MILLION;
1411
1412         if (priv->param->temperature_trimming_bits) {
1413                 ret = meson_sar_adc_temp_sensor_init(indio_dev);
1414                 if (ret)
1415                         return ret;
1416         }
1417
1418         if (priv->temperature_sensor_calibrated) {
1419                 indio_dev->channels = meson_sar_adc_and_temp_iio_channels;
1420                 indio_dev->num_channels =
1421                         ARRAY_SIZE(meson_sar_adc_and_temp_iio_channels);
1422         } else {
1423                 indio_dev->channels = meson_sar_adc_iio_channels;
1424                 indio_dev->num_channels =
1425                         ARRAY_SIZE(meson_sar_adc_iio_channels);
1426         }
1427
1428         ret = meson_sar_adc_init(indio_dev);
1429         if (ret)
1430                 goto err;
1431
1432         mutex_init(&priv->lock);
1433
1434         ret = meson_sar_adc_hw_enable(indio_dev);
1435         if (ret)
1436                 goto err;
1437
1438         ret = meson_sar_adc_calib(indio_dev);
1439         if (ret)
1440                 dev_warn(dev, "calibration failed\n");
1441
1442         platform_set_drvdata(pdev, indio_dev);
1443
1444         ret = iio_device_register(indio_dev);
1445         if (ret) {
1446                 dev_err_probe(dev, ret, "failed to register iio device\n");
1447                 goto err_hw;
1448         }
1449
1450         return 0;
1451
1452 err_hw:
1453         meson_sar_adc_hw_disable(indio_dev);
1454 err:
1455         return ret;
1456 }
1457
1458 static void meson_sar_adc_remove(struct platform_device *pdev)
1459 {
1460         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
1461
1462         iio_device_unregister(indio_dev);
1463
1464         meson_sar_adc_hw_disable(indio_dev);
1465 }
1466
1467 static int meson_sar_adc_suspend(struct device *dev)
1468 {
1469         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1470         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1471
1472         meson_sar_adc_hw_disable(indio_dev);
1473
1474         clk_disable_unprepare(priv->core_clk);
1475
1476         return 0;
1477 }
1478
1479 static int meson_sar_adc_resume(struct device *dev)
1480 {
1481         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1482         struct meson_sar_adc_priv *priv = iio_priv(indio_dev);
1483         int ret;
1484
1485         ret = clk_prepare_enable(priv->core_clk);
1486         if (ret) {
1487                 dev_err(dev, "failed to enable core clk\n");
1488                 return ret;
1489         }
1490
1491         return meson_sar_adc_hw_enable(indio_dev);
1492 }
1493
1494 static DEFINE_SIMPLE_DEV_PM_OPS(meson_sar_adc_pm_ops,
1495                                 meson_sar_adc_suspend, meson_sar_adc_resume);
1496
1497 static struct platform_driver meson_sar_adc_driver = {
1498         .probe          = meson_sar_adc_probe,
1499         .remove_new     = meson_sar_adc_remove,
1500         .driver         = {
1501                 .name   = "meson-saradc",
1502                 .of_match_table = meson_sar_adc_of_match,
1503                 .pm = pm_sleep_ptr(&meson_sar_adc_pm_ops),
1504         },
1505 };
1506
1507 module_platform_driver(meson_sar_adc_driver);
1508
1509 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
1510 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");
1511 MODULE_LICENSE("GPL v2");