2 * mcp3422.c - driver for the Microchip mcp3421/2/3/4/5/6/7/8 chip family
4 * Copyright (C) 2013, Angelo Compagnucci
5 * Author: Angelo Compagnucci <angelo.compagnucci@gmail.com>
7 * Datasheet: http://ww1.microchip.com/downloads/en/devicedoc/22088b.pdf
8 * http://ww1.microchip.com/downloads/en/DeviceDoc/22226a.pdf
9 * http://ww1.microchip.com/downloads/en/DeviceDoc/22072b.pdf
11 * This driver exports the value of analog input voltage to sysfs, the
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
20 #include <linux/err.h>
21 #include <linux/i2c.h>
22 #include <linux/module.h>
23 #include <linux/delay.h>
24 #include <linux/sysfs.h>
27 #include <linux/iio/iio.h>
28 #include <linux/iio/sysfs.h>
31 #define MCP3422_CHANNEL_MASK 0x60
32 #define MCP3422_PGA_MASK 0x03
33 #define MCP3422_SRATE_MASK 0x0C
34 #define MCP3422_SRATE_240 0x0
35 #define MCP3422_SRATE_60 0x1
36 #define MCP3422_SRATE_15 0x2
37 #define MCP3422_SRATE_3 0x3
38 #define MCP3422_PGA_1 0
39 #define MCP3422_PGA_2 1
40 #define MCP3422_PGA_4 2
41 #define MCP3422_PGA_8 3
42 #define MCP3422_CONT_SAMPLING 0x10
44 #define MCP3422_CHANNEL(config) (((config) & MCP3422_CHANNEL_MASK) >> 5)
45 #define MCP3422_PGA(config) ((config) & MCP3422_PGA_MASK)
46 #define MCP3422_SAMPLE_RATE(config) (((config) & MCP3422_SRATE_MASK) >> 2)
48 #define MCP3422_CHANNEL_VALUE(value) (((value) << 5) & MCP3422_CHANNEL_MASK)
49 #define MCP3422_PGA_VALUE(value) ((value) & MCP3422_PGA_MASK)
50 #define MCP3422_SAMPLE_RATE_VALUE(value) ((value << 2) & MCP3422_SRATE_MASK)
52 #define MCP3422_CHAN(_index) \
54 .type = IIO_VOLTAGE, \
57 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) \
58 | BIT(IIO_CHAN_INFO_SCALE), \
59 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ), \
62 static const int mcp3422_scales[4][4] = {
63 { 1000000, 500000, 250000, 125000 },
64 { 250000, 125000, 62500, 31250 },
65 { 62500, 31250, 15625, 7812 },
66 { 15625, 7812, 3906, 1953 } };
68 /* Constant msleep times for data acquisitions */
69 static const int mcp3422_read_times[4] = {
70 [MCP3422_SRATE_240] = 1000 / 240,
71 [MCP3422_SRATE_60] = 1000 / 60,
72 [MCP3422_SRATE_15] = 1000 / 15,
73 [MCP3422_SRATE_3] = 1000 / 3 };
75 /* sample rates to integer conversion table */
76 static const int mcp3422_sample_rates[4] = {
77 [MCP3422_SRATE_240] = 240,
78 [MCP3422_SRATE_60] = 60,
79 [MCP3422_SRATE_15] = 15,
80 [MCP3422_SRATE_3] = 3 };
82 /* sample rates to sign extension table */
83 static const int mcp3422_sign_extend[4] = {
84 [MCP3422_SRATE_240] = 11,
85 [MCP3422_SRATE_60] = 13,
86 [MCP3422_SRATE_15] = 15,
87 [MCP3422_SRATE_3] = 17 };
89 /* Client data (each client gets its own) */
91 struct i2c_client *i2c;
98 static int mcp3422_update_config(struct mcp3422 *adc, u8 newconfig)
102 ret = i2c_master_send(adc->i2c, &newconfig, 1);
104 adc->config = newconfig;
111 static int mcp3422_read(struct mcp3422 *adc, int *value, u8 *config)
114 u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
115 u8 buf[4] = {0, 0, 0, 0};
118 if (sample_rate == MCP3422_SRATE_3) {
119 ret = i2c_master_recv(adc->i2c, buf, 4);
120 temp = buf[0] << 16 | buf[1] << 8 | buf[2];
123 ret = i2c_master_recv(adc->i2c, buf, 3);
124 temp = buf[0] << 8 | buf[1];
128 *value = sign_extend32(temp, mcp3422_sign_extend[sample_rate]);
133 static int mcp3422_read_channel(struct mcp3422 *adc,
134 struct iio_chan_spec const *channel, int *value)
138 u8 req_channel = channel->channel;
140 mutex_lock(&adc->lock);
142 if (req_channel != MCP3422_CHANNEL(adc->config)) {
143 config = adc->config;
144 config &= ~MCP3422_CHANNEL_MASK;
145 config |= MCP3422_CHANNEL_VALUE(req_channel);
146 config &= ~MCP3422_PGA_MASK;
147 config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
148 ret = mcp3422_update_config(adc, config);
150 mutex_unlock(&adc->lock);
153 msleep(mcp3422_read_times[MCP3422_SAMPLE_RATE(adc->config)]);
156 ret = mcp3422_read(adc, value, &config);
158 mutex_unlock(&adc->lock);
163 static int mcp3422_read_raw(struct iio_dev *iio,
164 struct iio_chan_spec const *channel, int *val1,
165 int *val2, long mask)
167 struct mcp3422 *adc = iio_priv(iio);
170 u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
171 u8 pga = MCP3422_PGA(adc->config);
174 case IIO_CHAN_INFO_RAW:
175 err = mcp3422_read_channel(adc, channel, val1);
180 case IIO_CHAN_INFO_SCALE:
183 *val2 = mcp3422_scales[sample_rate][pga];
184 return IIO_VAL_INT_PLUS_NANO;
186 case IIO_CHAN_INFO_SAMP_FREQ:
187 *val1 = mcp3422_sample_rates[MCP3422_SAMPLE_RATE(adc->config)];
197 static int mcp3422_write_raw(struct iio_dev *iio,
198 struct iio_chan_spec const *channel, int val1,
201 struct mcp3422 *adc = iio_priv(iio);
203 u8 config = adc->config;
204 u8 req_channel = channel->channel;
205 u8 sample_rate = MCP3422_SAMPLE_RATE(config);
209 case IIO_CHAN_INFO_SCALE:
213 for (i = 0; i < ARRAY_SIZE(mcp3422_scales[0]); i++) {
214 if (val2 == mcp3422_scales[sample_rate][i]) {
215 adc->pga[req_channel] = i;
217 config &= ~MCP3422_CHANNEL_MASK;
218 config |= MCP3422_CHANNEL_VALUE(req_channel);
219 config &= ~MCP3422_PGA_MASK;
220 config |= MCP3422_PGA_VALUE(adc->pga[req_channel]);
222 return mcp3422_update_config(adc, config);
227 case IIO_CHAN_INFO_SAMP_FREQ:
230 temp = MCP3422_SRATE_240;
233 temp = MCP3422_SRATE_60;
236 temp = MCP3422_SRATE_15;
241 temp = MCP3422_SRATE_3;
247 config &= ~MCP3422_CHANNEL_MASK;
248 config |= MCP3422_CHANNEL_VALUE(req_channel);
249 config &= ~MCP3422_SRATE_MASK;
250 config |= MCP3422_SAMPLE_RATE_VALUE(temp);
252 return mcp3422_update_config(adc, config);
261 static int mcp3422_write_raw_get_fmt(struct iio_dev *indio_dev,
262 struct iio_chan_spec const *chan, long mask)
265 case IIO_CHAN_INFO_SCALE:
266 return IIO_VAL_INT_PLUS_NANO;
267 case IIO_CHAN_INFO_SAMP_FREQ:
268 return IIO_VAL_INT_PLUS_MICRO;
274 static ssize_t mcp3422_show_samp_freqs(struct device *dev,
275 struct device_attribute *attr, char *buf)
277 struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
280 return sprintf(buf, "240 60 15\n");
282 return sprintf(buf, "240 60 15 3\n");
285 static ssize_t mcp3422_show_scales(struct device *dev,
286 struct device_attribute *attr, char *buf)
288 struct mcp3422 *adc = iio_priv(dev_to_iio_dev(dev));
289 u8 sample_rate = MCP3422_SAMPLE_RATE(adc->config);
291 return sprintf(buf, "0.%09u 0.%09u 0.%09u 0.%09u\n",
292 mcp3422_scales[sample_rate][0],
293 mcp3422_scales[sample_rate][1],
294 mcp3422_scales[sample_rate][2],
295 mcp3422_scales[sample_rate][3]);
298 static IIO_DEVICE_ATTR(sampling_frequency_available, S_IRUGO,
299 mcp3422_show_samp_freqs, NULL, 0);
300 static IIO_DEVICE_ATTR(in_voltage_scale_available, S_IRUGO,
301 mcp3422_show_scales, NULL, 0);
303 static struct attribute *mcp3422_attributes[] = {
304 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
305 &iio_dev_attr_in_voltage_scale_available.dev_attr.attr,
309 static const struct attribute_group mcp3422_attribute_group = {
310 .attrs = mcp3422_attributes,
313 static const struct iio_chan_spec mcp3421_channels[] = {
317 static const struct iio_chan_spec mcp3422_channels[] = {
322 static const struct iio_chan_spec mcp3424_channels[] = {
329 static const struct iio_info mcp3422_info = {
330 .read_raw = mcp3422_read_raw,
331 .write_raw = mcp3422_write_raw,
332 .write_raw_get_fmt = mcp3422_write_raw_get_fmt,
333 .attrs = &mcp3422_attribute_group,
334 .driver_module = THIS_MODULE,
337 static int mcp3422_probe(struct i2c_client *client,
338 const struct i2c_device_id *id)
340 struct iio_dev *indio_dev;
345 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C))
348 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*adc));
352 adc = iio_priv(indio_dev);
354 adc->id = (u8)(id->driver_data);
356 mutex_init(&adc->lock);
358 indio_dev->dev.parent = &client->dev;
359 indio_dev->dev.of_node = client->dev.of_node;
360 indio_dev->name = dev_name(&client->dev);
361 indio_dev->modes = INDIO_DIRECT_MODE;
362 indio_dev->info = &mcp3422_info;
367 indio_dev->channels = mcp3421_channels;
368 indio_dev->num_channels = ARRAY_SIZE(mcp3421_channels);
374 indio_dev->channels = mcp3422_channels;
375 indio_dev->num_channels = ARRAY_SIZE(mcp3422_channels);
379 indio_dev->channels = mcp3424_channels;
380 indio_dev->num_channels = ARRAY_SIZE(mcp3424_channels);
384 /* meaningful default configuration */
385 config = (MCP3422_CONT_SAMPLING
386 | MCP3422_CHANNEL_VALUE(1)
387 | MCP3422_PGA_VALUE(MCP3422_PGA_1)
388 | MCP3422_SAMPLE_RATE_VALUE(MCP3422_SRATE_240));
389 mcp3422_update_config(adc, config);
391 err = devm_iio_device_register(&client->dev, indio_dev);
395 i2c_set_clientdata(client, indio_dev);
400 static const struct i2c_device_id mcp3422_id[] = {
411 MODULE_DEVICE_TABLE(i2c, mcp3422_id);
414 static const struct of_device_id mcp3422_of_match[] = {
415 { .compatible = "mcp3422" },
418 MODULE_DEVICE_TABLE(of, mcp3422_of_match);
421 static struct i2c_driver mcp3422_driver = {
424 .of_match_table = of_match_ptr(mcp3422_of_match),
426 .probe = mcp3422_probe,
427 .id_table = mcp3422_id,
429 module_i2c_driver(mcp3422_driver);
431 MODULE_AUTHOR("Angelo Compagnucci <angelo.compagnucci@gmail.com>");
432 MODULE_DESCRIPTION("Microchip mcp3421/2/3/4/5/6/7/8 driver");
433 MODULE_LICENSE("GPL v2");