drivers/iio/adc/max1027.c

   1  /*
   2   * iio/adc/max1027.c
   3   * Copyright (C) 2014 Philippe Reynes
   4   *
   5   * based on linux/drivers/iio/ad7923.c
   6   * Copyright 2011 Analog Devices Inc (from AD7923 Driver)
   7   * Copyright 2012 CS Systemes d'Information
   8   *
   9   * This program is free software; you can redistribute it and/or modify
  10   * it under the terms of the GNU General Public License version 2 as
  11   * published by the Free Software Foundation.
  12   *
  13   * max1027.c
  14   *
  15   * Partial support for max1027 and similar chips.
  16   */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/module.h>
  20 #include <linux/spi/spi.h>
  21 #include <linux/delay.h>
  22
  23 #include <linux/iio/iio.h>
  24 #include <linux/iio/buffer.h>
  25 #include <linux/iio/trigger.h>
  26 #include <linux/iio/trigger_consumer.h>
  27 #include <linux/iio/triggered_buffer.h>
  28
  29 #define MAX1027_CONV_REG  BIT(7)
  30 #define MAX1027_SETUP_REG BIT(6)
  31 #define MAX1027_AVG_REG   BIT(5)
  32 #define MAX1027_RST_REG   BIT(4)
  33
  34 /* conversion register */
  35 #define MAX1027_TEMP      BIT(0)
  36 #define MAX1027_SCAN_0_N  (0x00 << 1)
  37 #define MAX1027_SCAN_N_M  (0x01 << 1)
  38 #define MAX1027_SCAN_N    (0x02 << 1)
  39 #define MAX1027_NOSCAN    (0x03 << 1)
  40 #define MAX1027_CHAN(n)   ((n) << 3)
  41
  42 /* setup register */
  43 #define MAX1027_UNIPOLAR  0x02
  44 #define MAX1027_BIPOLAR   0x03
  45 #define MAX1027_REF_MODE0 (0x00 << 2)
  46 #define MAX1027_REF_MODE1 (0x01 << 2)
  47 #define MAX1027_REF_MODE2 (0x02 << 2)
  48 #define MAX1027_REF_MODE3 (0x03 << 2)
  49 #define MAX1027_CKS_MODE0 (0x00 << 4)
  50 #define MAX1027_CKS_MODE1 (0x01 << 4)
  51 #define MAX1027_CKS_MODE2 (0x02 << 4)
  52 #define MAX1027_CKS_MODE3 (0x03 << 4)
  53
  54 /* averaging register */
  55 #define MAX1027_NSCAN_4   0x00
  56 #define MAX1027_NSCAN_8   0x01
  57 #define MAX1027_NSCAN_12  0x02
  58 #define MAX1027_NSCAN_16  0x03
  59 #define MAX1027_NAVG_4    (0x00 << 2)
  60 #define MAX1027_NAVG_8    (0x01 << 2)
  61 #define MAX1027_NAVG_16   (0x02 << 2)
  62 #define MAX1027_NAVG_32   (0x03 << 2)
  63 #define MAX1027_AVG_EN    BIT(4)
  64
  65 enum max1027_id {
  66         max1027,
  67         max1029,
  68         max1031,
  69 };
  70
  71 static const struct spi_device_id max1027_id[] = {
  72         {"max1027", max1027},
  73         {"max1029", max1029},
  74         {"max1031", max1031},
  75         {}
  76 };
  77 MODULE_DEVICE_TABLE(spi, max1027_id);
  78
  79 #ifdef CONFIG_OF
  80 static const struct of_device_id max1027_adc_dt_ids[] = {
  81         { .compatible = "maxim,max1027" },
  82         { .compatible = "maxim,max1029" },
  83         { .compatible = "maxim,max1031" },
  84         {},
  85 };
  86 MODULE_DEVICE_TABLE(of, max1027_adc_dt_ids);
  87 #endif
  88
  89 #define MAX1027_V_CHAN(index)                                           \
  90         {                                                               \
  91                 .type = IIO_VOLTAGE,                                    \
  92                 .indexed = 1,                                           \
  93                 .channel = index,                                       \
  94                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
  95                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
  96                 .scan_index = index + 1,                                \
  97                 .scan_type = {                                          \
  98                         .sign = 'u',                                    \
  99                         .realbits = 10,                                 \
 100                         .storagebits = 16,                              \
 101                         .shift = 2,                                     \
 102                         .endianness = IIO_BE,                           \
 103                 },                                                      \
 104         }
 105
 106 #define MAX1027_T_CHAN                                                  \
 107         {                                                               \
 108                 .type = IIO_TEMP,                                       \
 109                 .channel = 0,                                           \
 110                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 111                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 112                 .scan_index = 0,                                        \
 113                 .scan_type = {                                          \
 114                         .sign = 'u',                                    \
 115                         .realbits = 12,                                 \
 116                         .storagebits = 16,                              \
 117                         .endianness = IIO_BE,                           \
 118                 },                                                      \
 119         }
 120
 121 static const struct iio_chan_spec max1027_channels[] = {
 122         MAX1027_T_CHAN,
 123         MAX1027_V_CHAN(0),
 124         MAX1027_V_CHAN(1),
 125         MAX1027_V_CHAN(2),
 126         MAX1027_V_CHAN(3),
 127         MAX1027_V_CHAN(4),
 128         MAX1027_V_CHAN(5),
 129         MAX1027_V_CHAN(6),
 130         MAX1027_V_CHAN(7)
 131 };
 132
 133 static const struct iio_chan_spec max1029_channels[] = {
 134         MAX1027_T_CHAN,
 135         MAX1027_V_CHAN(0),
 136         MAX1027_V_CHAN(1),
 137         MAX1027_V_CHAN(2),
 138         MAX1027_V_CHAN(3),
 139         MAX1027_V_CHAN(4),
 140         MAX1027_V_CHAN(5),
 141         MAX1027_V_CHAN(6),
 142         MAX1027_V_CHAN(7),
 143         MAX1027_V_CHAN(8),
 144         MAX1027_V_CHAN(9),
 145         MAX1027_V_CHAN(10),
 146         MAX1027_V_CHAN(11)
 147 };
 148
 149 static const struct iio_chan_spec max1031_channels[] = {
 150         MAX1027_T_CHAN,
 151         MAX1027_V_CHAN(0),
 152         MAX1027_V_CHAN(1),
 153         MAX1027_V_CHAN(2),
 154         MAX1027_V_CHAN(3),
 155         MAX1027_V_CHAN(4),
 156         MAX1027_V_CHAN(5),
 157         MAX1027_V_CHAN(6),
 158         MAX1027_V_CHAN(7),
 159         MAX1027_V_CHAN(8),
 160         MAX1027_V_CHAN(9),
 161         MAX1027_V_CHAN(10),
 162         MAX1027_V_CHAN(11),
 163         MAX1027_V_CHAN(12),
 164         MAX1027_V_CHAN(13),
 165         MAX1027_V_CHAN(14),
 166         MAX1027_V_CHAN(15)
 167 };
 168
 169 static const unsigned long max1027_available_scan_masks[] = {
 170         0x000001ff,
 171         0x00000000,
 172 };
 173
 174 static const unsigned long max1029_available_scan_masks[] = {
 175         0x00001fff,
 176         0x00000000,
 177 };
 178
 179 static const unsigned long max1031_available_scan_masks[] = {
 180         0x0001ffff,
 181         0x00000000,
 182 };
 183
 184 struct max1027_chip_info {
 185         const struct iio_chan_spec *channels;
 186         unsigned int num_channels;
 187         const unsigned long *available_scan_masks;
 188 };
 189
 190 static const struct max1027_chip_info max1027_chip_info_tbl[] = {
 191         [max1027] = {
 192                 .channels = max1027_channels,
 193                 .num_channels = ARRAY_SIZE(max1027_channels),
 194                 .available_scan_masks = max1027_available_scan_masks,
 195         },
 196         [max1029] = {
 197                 .channels = max1029_channels,
 198                 .num_channels = ARRAY_SIZE(max1029_channels),
 199                 .available_scan_masks = max1029_available_scan_masks,
 200         },
 201         [max1031] = {
 202                 .channels = max1031_channels,
 203                 .num_channels = ARRAY_SIZE(max1031_channels),
 204                 .available_scan_masks = max1031_available_scan_masks,
 205         },
 206 };
 207
 208 struct max1027_state {
 209         const struct max1027_chip_info  *info;
 210         struct spi_device               *spi;
 211         struct iio_trigger              *trig;
 212         __be16                          *buffer;
 213         struct mutex                    lock;
 214
 215         u8                              reg ____cacheline_aligned;
 216 };
 217
 218 static int max1027_read_single_value(struct iio_dev *indio_dev,
 219                                      struct iio_chan_spec const *chan,
 220                                      int *val)
 221 {
 222         int ret;
 223         struct max1027_state *st = iio_priv(indio_dev);
 224
 225         if (iio_buffer_enabled(indio_dev)) {
 226                 dev_warn(&indio_dev->dev, "trigger mode already enabled");
 227                 return -EBUSY;
 228         }
 229
 230         /* Start acquisition on conversion register write */
 231         st->reg = MAX1027_SETUP_REG | MAX1027_REF_MODE2 | MAX1027_CKS_MODE2;
 232         ret = spi_write(st->spi, &st->reg, 1);
 233         if (ret < 0) {
 234                 dev_err(&indio_dev->dev,
 235                         "Failed to configure setup register\n");
 236                 return ret;
 237         }
 238
 239         /* Configure conversion register with the requested chan */
 240         st->reg = MAX1027_CONV_REG | MAX1027_CHAN(chan->channel) |
 241                   MAX1027_NOSCAN;
 242         if (chan->type == IIO_TEMP)
 243                 st->reg |= MAX1027_TEMP;
 244         ret = spi_write(st->spi, &st->reg, 1);
 245         if (ret < 0) {
 246                 dev_err(&indio_dev->dev,
 247                         "Failed to configure conversion register\n");
 248                 return ret;
 249         }
 250
 251         /*
 252          * For an unknown reason, when we use the mode "10" (write
 253          * conversion register), the interrupt doesn't occur every time.
 254          * So we just wait 1 ms.
 255          */
 256         mdelay(1);
 257
 258         /* Read result */
 259         ret = spi_read(st->spi, st->buffer, (chan->type == IIO_TEMP) ? 4 : 2);
 260         if (ret < 0)
 261                 return ret;
 262
 263         *val = be16_to_cpu(st->buffer[0]);
 264
 265         return IIO_VAL_INT;
 266 }
 267
 268 static int max1027_read_raw(struct iio_dev *indio_dev,
 269                             struct iio_chan_spec const *chan,
 270                             int *val, int *val2, long mask)
 271 {
 272         int ret = 0;
 273         struct max1027_state *st = iio_priv(indio_dev);
 274
 275         mutex_lock(&st->lock);
 276
 277         switch (mask) {
 278         case IIO_CHAN_INFO_RAW:
 279                 ret = max1027_read_single_value(indio_dev, chan, val);
 280                 break;
 281         case IIO_CHAN_INFO_SCALE:
 282                 switch (chan->type) {
 283                 case IIO_TEMP:
 284                         *val = 1;
 285                         *val2 = 8;
 286                         ret = IIO_VAL_FRACTIONAL;
 287                         break;
 288                 case IIO_VOLTAGE:
 289                         *val = 2500;
 290                         *val2 = 10;
 291                         ret = IIO_VAL_FRACTIONAL_LOG2;
 292                         break;
 293                 default:
 294                         ret = -EINVAL;
 295                         break;
 296                 }
 297                 break;
 298         default:
 299                 ret = -EINVAL;
 300                 break;
 301         }
 302
 303         mutex_unlock(&st->lock);
 304
 305         return ret;
 306 }
 307
 308 static int max1027_debugfs_reg_access(struct iio_dev *indio_dev,
 309                                       unsigned reg, unsigned writeval,
 310                                       unsigned *readval)
 311 {
 312         struct max1027_state *st = iio_priv(indio_dev);
 313         u8 *val = (u8 *)st->buffer;
 314
 315         if (readval != NULL)
 316                 return -EINVAL;
 317
 318         *val = (u8)writeval;
 319         return spi_write(st->spi, val, 1);
 320 }
 321
 322 static int max1027_validate_trigger(struct iio_dev *indio_dev,
 323                                     struct iio_trigger *trig)
 324 {
 325         struct max1027_state *st = iio_priv(indio_dev);
 326
 327         if (st->trig != trig)
 328                 return -EINVAL;
 329
 330         return 0;
 331 }
 332
 333 static int max1027_set_trigger_state(struct iio_trigger *trig, bool state)
 334 {
 335         struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
 336         struct max1027_state *st = iio_priv(indio_dev);
 337         int ret;
 338
 339         if (state) {
 340                 /* Start acquisition on cnvst */
 341                 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE0 |
 342                           MAX1027_REF_MODE2;
 343                 ret = spi_write(st->spi, &st->reg, 1);
 344                 if (ret < 0)
 345                         return ret;
 346
 347                 /* Scan from 0 to max */
 348                 st->reg = MAX1027_CONV_REG | MAX1027_CHAN(0) |
 349                           MAX1027_SCAN_N_M | MAX1027_TEMP;
 350                 ret = spi_write(st->spi, &st->reg, 1);
 351                 if (ret < 0)
 352                         return ret;
 353         } else {
 354                 /* Start acquisition on conversion register write */
 355                 st->reg = MAX1027_SETUP_REG | MAX1027_CKS_MODE2 |
 356                           MAX1027_REF_MODE2;
 357                 ret = spi_write(st->spi, &st->reg, 1);
 358                 if (ret < 0)
 359                         return ret;
 360         }
 361
 362         return 0;
 363 }
 364
 365 static irqreturn_t max1027_trigger_handler(int irq, void *private)
 366 {
 367         struct iio_poll_func *pf = private;
 368         struct iio_dev *indio_dev = pf->indio_dev;
 369         struct max1027_state *st = iio_priv(indio_dev);
 370
 371         pr_debug("%s(irq=%d, private=0x%p)\n", __func__, irq, private);
 372
 373         /* fill buffer with all channel */
 374         spi_read(st->spi, st->buffer, indio_dev->masklength * 2);
 375
 376         iio_push_to_buffers(indio_dev, st->buffer);
 377
 378         iio_trigger_notify_done(indio_dev->trig);
 379
 380         return IRQ_HANDLED;
 381 }
 382
 383 static const struct iio_trigger_ops max1027_trigger_ops = {
 384         .owner = THIS_MODULE,
 385         .validate_device = &iio_trigger_validate_own_device,
 386         .set_trigger_state = &max1027_set_trigger_state,
 387 };
 388
 389 static const struct iio_info max1027_info = {
 390         .driver_module = THIS_MODULE,
 391         .read_raw = &max1027_read_raw,
 392         .validate_trigger = &max1027_validate_trigger,
 393         .debugfs_reg_access = &max1027_debugfs_reg_access,
 394 };
 395
 396 static int max1027_probe(struct spi_device *spi)
 397 {
 398         int ret;
 399         struct iio_dev *indio_dev;
 400         struct max1027_state *st;
 401
 402         pr_debug("%s: probe(spi = 0x%p)\n", __func__, spi);
 403
 404         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 405         if (indio_dev == NULL) {
 406                 pr_err("Can't allocate iio device\n");
 407                 return -ENOMEM;
 408         }
 409
 410         spi_set_drvdata(spi, indio_dev);
 411
 412         st = iio_priv(indio_dev);
 413         st->spi = spi;
 414         st->info = &max1027_chip_info_tbl[spi_get_device_id(spi)->driver_data];
 415
 416         mutex_init(&st->lock);
 417
 418         indio_dev->name = spi_get_device_id(spi)->name;
 419         indio_dev->dev.parent = &spi->dev;
 420         indio_dev->dev.of_node = spi->dev.of_node;
 421         indio_dev->info = &max1027_info;
 422         indio_dev->modes = INDIO_DIRECT_MODE;
 423         indio_dev->channels = st->info->channels;
 424         indio_dev->num_channels = st->info->num_channels;
 425         indio_dev->available_scan_masks = st->info->available_scan_masks;
 426
 427         st->buffer = devm_kmalloc(&indio_dev->dev,
 428                                   indio_dev->num_channels * 2,
 429                                   GFP_KERNEL);
 430         if (st->buffer == NULL) {
 431                 dev_err(&indio_dev->dev, "Can't allocate buffer\n");
 432                 return -ENOMEM;
 433         }
 434
 435         ret = iio_triggered_buffer_setup(indio_dev, &iio_pollfunc_store_time,
 436                                          &max1027_trigger_handler, NULL);
 437         if (ret < 0) {
 438                 dev_err(&indio_dev->dev, "Failed to setup buffer\n");
 439                 return ret;
 440         }
 441
 442         st->trig = devm_iio_trigger_alloc(&spi->dev, "%s-trigger",
 443                                                         indio_dev->name);
 444         if (st->trig == NULL) {
 445                 ret = -ENOMEM;
 446                 dev_err(&indio_dev->dev, "Failed to allocate iio trigger\n");
 447                 goto fail_trigger_alloc;
 448         }
 449
 450         st->trig->ops = &max1027_trigger_ops;
 451         st->trig->dev.parent = &spi->dev;
 452         iio_trigger_set_drvdata(st->trig, indio_dev);
 453         iio_trigger_register(st->trig);
 454
 455         ret = devm_request_threaded_irq(&spi->dev, spi->irq,
 456                                         iio_trigger_generic_data_rdy_poll,
 457                                         NULL,
 458                                         IRQF_TRIGGER_FALLING,
 459                                         spi->dev.driver->name, st->trig);
 460         if (ret < 0) {
 461                 dev_err(&indio_dev->dev, "Failed to allocate IRQ.\n");
 462                 goto fail_dev_register;
 463         }
 464
 465         /* Internal reset */
 466         st->reg = MAX1027_RST_REG;
 467         ret = spi_write(st->spi, &st->reg, 1);
 468         if (ret < 0) {
 469                 dev_err(&indio_dev->dev, "Failed to reset the ADC\n");
 470                 return ret;
 471         }
 472
 473         /* Disable averaging */
 474         st->reg = MAX1027_AVG_REG;
 475         ret = spi_write(st->spi, &st->reg, 1);
 476         if (ret < 0) {
 477                 dev_err(&indio_dev->dev, "Failed to configure averaging register\n");
 478                 goto fail_dev_register;
 479         }
 480
 481         ret = iio_device_register(indio_dev);
 482         if (ret < 0) {
 483                 dev_err(&indio_dev->dev, "Failed to register iio device\n");
 484                 goto fail_dev_register;
 485         }
 486
 487         return 0;
 488
 489 fail_dev_register:
 490 fail_trigger_alloc:
 491         iio_triggered_buffer_cleanup(indio_dev);
 492
 493         return ret;
 494 }
 495
 496 static int max1027_remove(struct spi_device *spi)
 497 {
 498         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 499
 500         pr_debug("%s: remove(spi = 0x%p)\n", __func__, spi);
 501
 502         iio_device_unregister(indio_dev);
 503         iio_triggered_buffer_cleanup(indio_dev);
 504
 505         return 0;
 506 }
 507
 508 static struct spi_driver max1027_driver = {
 509         .driver = {
 510                 .name   = "max1027",
 511                 .of_match_table = of_match_ptr(max1027_adc_dt_ids),
 512         },
 513         .probe          = max1027_probe,
 514         .remove         = max1027_remove,
 515         .id_table       = max1027_id,
 516 };
 517 module_spi_driver(max1027_driver);
 518
 519 MODULE_AUTHOR("Philippe Reynes <tremyfr@yahoo.fr>");
 520 MODULE_DESCRIPTION("MAX1027/MAX1029/MAX1031 ADC");
 521 MODULE_LICENSE("GPL v2");