1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * exynos_adc.c - Support for ADC in EXYNOS SoCs
5 * 8 ~ 10 channel, 10/12-bit ADC
7 * Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <linux/interrupt.h>
13 #include <linux/delay.h>
14 #include <linux/errno.h>
15 #include <linux/kernel.h>
16 #include <linux/slab.h>
18 #include <linux/clk.h>
19 #include <linux/completion.h>
21 #include <linux/of_irq.h>
22 #include <linux/regulator/consumer.h>
23 #include <linux/of_platform.h>
24 #include <linux/err.h>
25 #include <linux/input.h>
27 #include <linux/iio/iio.h>
28 #include <linux/iio/machine.h>
29 #include <linux/iio/driver.h>
30 #include <linux/mfd/syscon.h>
31 #include <linux/regmap.h>
33 #include <linux/platform_data/touchscreen-s3c2410.h>
35 /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
36 #define ADC_V1_CON(x) ((x) + 0x00)
37 #define ADC_V1_TSC(x) ((x) + 0x04)
38 #define ADC_V1_DLY(x) ((x) + 0x08)
39 #define ADC_V1_DATX(x) ((x) + 0x0C)
40 #define ADC_V1_DATY(x) ((x) + 0x10)
41 #define ADC_V1_UPDN(x) ((x) + 0x14)
42 #define ADC_V1_INTCLR(x) ((x) + 0x18)
43 #define ADC_V1_MUX(x) ((x) + 0x1c)
44 #define ADC_V1_CLRINTPNDNUP(x) ((x) + 0x20)
46 /* S3C2410 ADC registers definitions */
47 #define ADC_S3C2410_MUX(x) ((x) + 0x18)
49 /* Future ADC_V2 registers definitions */
50 #define ADC_V2_CON1(x) ((x) + 0x00)
51 #define ADC_V2_CON2(x) ((x) + 0x04)
52 #define ADC_V2_STAT(x) ((x) + 0x08)
53 #define ADC_V2_INT_EN(x) ((x) + 0x10)
54 #define ADC_V2_INT_ST(x) ((x) + 0x14)
55 #define ADC_V2_VER(x) ((x) + 0x20)
57 /* Bit definitions for ADC_V1 */
58 #define ADC_V1_CON_RES (1u << 16)
59 #define ADC_V1_CON_PRSCEN (1u << 14)
60 #define ADC_V1_CON_PRSCLV(x) (((x) & 0xFF) << 6)
61 #define ADC_V1_CON_STANDBY (1u << 2)
63 /* Bit definitions for S3C2410 ADC */
64 #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
65 #define ADC_S3C2410_DATX_MASK 0x3FF
66 #define ADC_S3C2416_CON_RES_SEL (1u << 3)
68 /* touch screen always uses channel 0 */
69 #define ADC_S3C2410_MUX_TS 0
71 /* ADCTSC Register Bits */
72 #define ADC_S3C2443_TSC_UD_SEN (1u << 8)
73 #define ADC_S3C2410_TSC_YM_SEN (1u << 7)
74 #define ADC_S3C2410_TSC_YP_SEN (1u << 6)
75 #define ADC_S3C2410_TSC_XM_SEN (1u << 5)
76 #define ADC_S3C2410_TSC_XP_SEN (1u << 4)
77 #define ADC_S3C2410_TSC_PULL_UP_DISABLE (1u << 3)
78 #define ADC_S3C2410_TSC_AUTO_PST (1u << 2)
79 #define ADC_S3C2410_TSC_XY_PST(x) (((x) & 0x3) << 0)
81 #define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \
82 ADC_S3C2410_TSC_YP_SEN | \
83 ADC_S3C2410_TSC_XP_SEN | \
84 ADC_S3C2410_TSC_XY_PST(3))
86 #define ADC_TSC_AUTOPST (ADC_S3C2410_TSC_YM_SEN | \
87 ADC_S3C2410_TSC_YP_SEN | \
88 ADC_S3C2410_TSC_XP_SEN | \
89 ADC_S3C2410_TSC_AUTO_PST | \
90 ADC_S3C2410_TSC_XY_PST(0))
92 /* Bit definitions for ADC_V2 */
93 #define ADC_V2_CON1_SOFT_RESET (1u << 2)
95 #define ADC_V2_CON2_OSEL (1u << 10)
96 #define ADC_V2_CON2_ESEL (1u << 9)
97 #define ADC_V2_CON2_HIGHF (1u << 8)
98 #define ADC_V2_CON2_C_TIME(x) (((x) & 7) << 4)
99 #define ADC_V2_CON2_ACH_SEL(x) (((x) & 0xF) << 0)
100 #define ADC_V2_CON2_ACH_MASK 0xF
102 #define MAX_ADC_V2_CHANNELS 10
103 #define MAX_ADC_V1_CHANNELS 8
104 #define MAX_EXYNOS3250_ADC_CHANNELS 2
105 #define MAX_EXYNOS4212_ADC_CHANNELS 4
106 #define MAX_S5PV210_ADC_CHANNELS 10
108 /* Bit definitions common for ADC_V1 and ADC_V2 */
109 #define ADC_CON_EN_START (1u << 0)
110 #define ADC_CON_EN_START_MASK (0x3 << 0)
111 #define ADC_DATX_PRESSED (1u << 15)
112 #define ADC_DATX_MASK 0xFFF
113 #define ADC_DATY_MASK 0xFFF
115 #define EXYNOS_ADC_TIMEOUT (msecs_to_jiffies(100))
117 #define EXYNOS_ADCV1_PHY_OFFSET 0x0718
118 #define EXYNOS_ADCV2_PHY_OFFSET 0x0720
121 struct exynos_adc_data *data;
123 struct input_dev *input;
125 struct regmap *pmu_map;
131 struct regulator *vdd;
133 struct completion completion;
136 unsigned int version;
143 * Lock to protect from potential concurrent access to the
144 * completion callback during a manual conversion. For this driver
145 * a wait-callback is used to wait for the conversion result,
146 * so in the meantime no other read request (or conversion start)
147 * must be performed, otherwise it would interfere with the
148 * current conversion result.
153 struct exynos_adc_data {
160 void (*init_hw)(struct exynos_adc *info);
161 void (*exit_hw)(struct exynos_adc *info);
162 void (*clear_irq)(struct exynos_adc *info);
163 void (*start_conv)(struct exynos_adc *info, unsigned long addr);
166 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
168 if (info->data->needs_sclk)
169 clk_unprepare(info->sclk);
170 clk_unprepare(info->clk);
173 static int exynos_adc_prepare_clk(struct exynos_adc *info)
177 ret = clk_prepare(info->clk);
179 dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
183 if (info->data->needs_sclk) {
184 ret = clk_prepare(info->sclk);
186 clk_unprepare(info->clk);
188 "failed preparing sclk_adc clock: %d\n", ret);
196 static void exynos_adc_disable_clk(struct exynos_adc *info)
198 if (info->data->needs_sclk)
199 clk_disable(info->sclk);
200 clk_disable(info->clk);
203 static int exynos_adc_enable_clk(struct exynos_adc *info)
207 ret = clk_enable(info->clk);
209 dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
213 if (info->data->needs_sclk) {
214 ret = clk_enable(info->sclk);
216 clk_disable(info->clk);
218 "failed enabling sclk_adc clock: %d\n", ret);
226 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
230 if (info->data->needs_adc_phy)
231 regmap_write(info->pmu_map, info->data->phy_offset, 1);
233 /* set default prescaler values and Enable prescaler */
234 con1 = ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
236 /* Enable 12-bit ADC resolution */
237 con1 |= ADC_V1_CON_RES;
238 writel(con1, ADC_V1_CON(info->regs));
240 /* set touchscreen delay */
241 writel(info->delay, ADC_V1_DLY(info->regs));
244 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
248 if (info->data->needs_adc_phy)
249 regmap_write(info->pmu_map, info->data->phy_offset, 0);
251 con = readl(ADC_V1_CON(info->regs));
252 con |= ADC_V1_CON_STANDBY;
253 writel(con, ADC_V1_CON(info->regs));
256 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
258 writel(1, ADC_V1_INTCLR(info->regs));
261 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
266 writel(addr, ADC_V1_MUX(info->regs));
268 con1 = readl(ADC_V1_CON(info->regs));
269 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
272 /* Exynos4212 and 4412 is like ADCv1 but with four channels only */
273 static const struct exynos_adc_data exynos4212_adc_data = {
274 .num_channels = MAX_EXYNOS4212_ADC_CHANNELS,
275 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
276 .needs_adc_phy = true,
277 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
279 .init_hw = exynos_adc_v1_init_hw,
280 .exit_hw = exynos_adc_v1_exit_hw,
281 .clear_irq = exynos_adc_v1_clear_irq,
282 .start_conv = exynos_adc_v1_start_conv,
285 static const struct exynos_adc_data exynos_adc_v1_data = {
286 .num_channels = MAX_ADC_V1_CHANNELS,
287 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
288 .needs_adc_phy = true,
289 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
291 .init_hw = exynos_adc_v1_init_hw,
292 .exit_hw = exynos_adc_v1_exit_hw,
293 .clear_irq = exynos_adc_v1_clear_irq,
294 .start_conv = exynos_adc_v1_start_conv,
297 static const struct exynos_adc_data exynos_adc_s5pv210_data = {
298 .num_channels = MAX_S5PV210_ADC_CHANNELS,
299 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
301 .init_hw = exynos_adc_v1_init_hw,
302 .exit_hw = exynos_adc_v1_exit_hw,
303 .clear_irq = exynos_adc_v1_clear_irq,
304 .start_conv = exynos_adc_v1_start_conv,
307 static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
312 /* Enable 12 bit ADC resolution */
313 con1 = readl(ADC_V1_CON(info->regs));
314 con1 |= ADC_S3C2416_CON_RES_SEL;
315 writel(con1, ADC_V1_CON(info->regs));
317 /* Select channel for S3C2416 */
318 writel(addr, ADC_S3C2410_MUX(info->regs));
320 con1 = readl(ADC_V1_CON(info->regs));
321 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
324 static struct exynos_adc_data const exynos_adc_s3c2416_data = {
325 .num_channels = MAX_ADC_V1_CHANNELS,
326 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
328 .init_hw = exynos_adc_v1_init_hw,
329 .exit_hw = exynos_adc_v1_exit_hw,
330 .start_conv = exynos_adc_s3c2416_start_conv,
333 static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
338 /* Select channel for S3C2433 */
339 writel(addr, ADC_S3C2410_MUX(info->regs));
341 con1 = readl(ADC_V1_CON(info->regs));
342 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
345 static struct exynos_adc_data const exynos_adc_s3c2443_data = {
346 .num_channels = MAX_ADC_V1_CHANNELS,
347 .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
349 .init_hw = exynos_adc_v1_init_hw,
350 .exit_hw = exynos_adc_v1_exit_hw,
351 .start_conv = exynos_adc_s3c2443_start_conv,
354 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
359 con1 = readl(ADC_V1_CON(info->regs));
360 con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
361 con1 |= ADC_S3C2410_CON_SELMUX(addr);
362 writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
365 static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
366 .num_channels = MAX_ADC_V1_CHANNELS,
367 .mask = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
369 .init_hw = exynos_adc_v1_init_hw,
370 .exit_hw = exynos_adc_v1_exit_hw,
371 .start_conv = exynos_adc_s3c64xx_start_conv,
374 static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
375 .num_channels = MAX_ADC_V1_CHANNELS,
376 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
378 .init_hw = exynos_adc_v1_init_hw,
379 .exit_hw = exynos_adc_v1_exit_hw,
380 .clear_irq = exynos_adc_v1_clear_irq,
381 .start_conv = exynos_adc_s3c64xx_start_conv,
384 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
388 if (info->data->needs_adc_phy)
389 regmap_write(info->pmu_map, info->data->phy_offset, 1);
391 con1 = ADC_V2_CON1_SOFT_RESET;
392 writel(con1, ADC_V2_CON1(info->regs));
394 con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
395 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
396 writel(con2, ADC_V2_CON2(info->regs));
398 /* Enable interrupts */
399 writel(1, ADC_V2_INT_EN(info->regs));
402 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
406 if (info->data->needs_adc_phy)
407 regmap_write(info->pmu_map, info->data->phy_offset, 0);
409 con = readl(ADC_V2_CON1(info->regs));
410 con &= ~ADC_CON_EN_START;
411 writel(con, ADC_V2_CON1(info->regs));
414 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
416 writel(1, ADC_V2_INT_ST(info->regs));
419 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
424 con2 = readl(ADC_V2_CON2(info->regs));
425 con2 &= ~ADC_V2_CON2_ACH_MASK;
426 con2 |= ADC_V2_CON2_ACH_SEL(addr);
427 writel(con2, ADC_V2_CON2(info->regs));
429 con1 = readl(ADC_V2_CON1(info->regs));
430 writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
433 static const struct exynos_adc_data exynos_adc_v2_data = {
434 .num_channels = MAX_ADC_V2_CHANNELS,
435 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
436 .needs_adc_phy = true,
437 .phy_offset = EXYNOS_ADCV2_PHY_OFFSET,
439 .init_hw = exynos_adc_v2_init_hw,
440 .exit_hw = exynos_adc_v2_exit_hw,
441 .clear_irq = exynos_adc_v2_clear_irq,
442 .start_conv = exynos_adc_v2_start_conv,
445 static const struct exynos_adc_data exynos3250_adc_data = {
446 .num_channels = MAX_EXYNOS3250_ADC_CHANNELS,
447 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
449 .needs_adc_phy = true,
450 .phy_offset = EXYNOS_ADCV1_PHY_OFFSET,
452 .init_hw = exynos_adc_v2_init_hw,
453 .exit_hw = exynos_adc_v2_exit_hw,
454 .clear_irq = exynos_adc_v2_clear_irq,
455 .start_conv = exynos_adc_v2_start_conv,
458 static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
462 con1 = ADC_V2_CON1_SOFT_RESET;
463 writel(con1, ADC_V2_CON1(info->regs));
465 con2 = readl(ADC_V2_CON2(info->regs));
466 con2 &= ~ADC_V2_CON2_C_TIME(7);
467 con2 |= ADC_V2_CON2_C_TIME(0);
468 writel(con2, ADC_V2_CON2(info->regs));
470 /* Enable interrupts */
471 writel(1, ADC_V2_INT_EN(info->regs));
474 static const struct exynos_adc_data exynos7_adc_data = {
475 .num_channels = MAX_ADC_V1_CHANNELS,
476 .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
478 .init_hw = exynos_adc_exynos7_init_hw,
479 .exit_hw = exynos_adc_v2_exit_hw,
480 .clear_irq = exynos_adc_v2_clear_irq,
481 .start_conv = exynos_adc_v2_start_conv,
484 static const struct of_device_id exynos_adc_match[] = {
486 .compatible = "samsung,s3c2410-adc",
487 .data = &exynos_adc_s3c24xx_data,
489 .compatible = "samsung,s3c2416-adc",
490 .data = &exynos_adc_s3c2416_data,
492 .compatible = "samsung,s3c2440-adc",
493 .data = &exynos_adc_s3c24xx_data,
495 .compatible = "samsung,s3c2443-adc",
496 .data = &exynos_adc_s3c2443_data,
498 .compatible = "samsung,s3c6410-adc",
499 .data = &exynos_adc_s3c64xx_data,
501 .compatible = "samsung,s5pv210-adc",
502 .data = &exynos_adc_s5pv210_data,
504 .compatible = "samsung,exynos4212-adc",
505 .data = &exynos4212_adc_data,
507 .compatible = "samsung,exynos-adc-v1",
508 .data = &exynos_adc_v1_data,
510 .compatible = "samsung,exynos-adc-v2",
511 .data = &exynos_adc_v2_data,
513 .compatible = "samsung,exynos3250-adc",
514 .data = &exynos3250_adc_data,
516 .compatible = "samsung,exynos7-adc",
517 .data = &exynos7_adc_data,
521 MODULE_DEVICE_TABLE(of, exynos_adc_match);
523 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
525 const struct of_device_id *match;
527 match = of_match_node(exynos_adc_match, pdev->dev.of_node);
528 return (struct exynos_adc_data *)match->data;
531 static int exynos_read_raw(struct iio_dev *indio_dev,
532 struct iio_chan_spec const *chan,
537 struct exynos_adc *info = iio_priv(indio_dev);
538 unsigned long timeout;
541 if (mask == IIO_CHAN_INFO_SCALE) {
542 ret = regulator_get_voltage(info->vdd);
546 /* Regulator voltage is in uV, but need mV */
548 *val2 = info->data->mask;
550 return IIO_VAL_FRACTIONAL;
551 } else if (mask != IIO_CHAN_INFO_RAW) {
555 mutex_lock(&info->lock);
556 reinit_completion(&info->completion);
558 /* Select the channel to be used and Trigger conversion */
559 if (info->data->start_conv)
560 info->data->start_conv(info, chan->address);
562 timeout = wait_for_completion_timeout(&info->completion,
565 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
566 if (info->data->init_hw)
567 info->data->init_hw(info);
575 mutex_unlock(&info->lock);
580 static int exynos_read_s3c64xx_ts(struct iio_dev *indio_dev, int *x, int *y)
582 struct exynos_adc *info = iio_priv(indio_dev);
583 unsigned long timeout;
586 mutex_lock(&info->lock);
587 info->read_ts = true;
589 reinit_completion(&info->completion);
591 writel(ADC_S3C2410_TSC_PULL_UP_DISABLE | ADC_TSC_AUTOPST,
592 ADC_V1_TSC(info->regs));
594 /* Select the ts channel to be used and Trigger conversion */
595 info->data->start_conv(info, ADC_S3C2410_MUX_TS);
597 timeout = wait_for_completion_timeout(&info->completion,
600 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
601 if (info->data->init_hw)
602 info->data->init_hw(info);
610 info->read_ts = false;
611 mutex_unlock(&info->lock);
616 static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
618 struct exynos_adc *info = dev_id;
619 u32 mask = info->data->mask;
623 info->ts_x = readl(ADC_V1_DATX(info->regs));
624 info->ts_y = readl(ADC_V1_DATY(info->regs));
625 writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs));
627 info->value = readl(ADC_V1_DATX(info->regs)) & mask;
631 if (info->data->clear_irq)
632 info->data->clear_irq(info);
634 complete(&info->completion);
640 * Here we (ab)use a threaded interrupt handler to stay running
641 * for as long as the touchscreen remains pressed, we report
642 * a new event with the latest data and then sleep until the
643 * next timer tick. This mirrors the behavior of the old
644 * driver, with much less code.
646 static irqreturn_t exynos_ts_isr(int irq, void *dev_id)
648 struct exynos_adc *info = dev_id;
649 struct iio_dev *dev = dev_get_drvdata(info->dev);
654 while (info->input->users) {
655 ret = exynos_read_s3c64xx_ts(dev, &x, &y);
656 if (ret == -ETIMEDOUT)
659 pressed = x & y & ADC_DATX_PRESSED;
661 input_report_key(info->input, BTN_TOUCH, 0);
662 input_sync(info->input);
666 input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK);
667 input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK);
668 input_report_key(info->input, BTN_TOUCH, 1);
669 input_sync(info->input);
671 usleep_range(1000, 1100);
674 writel(0, ADC_V1_CLRINTPNDNUP(info->regs));
679 static int exynos_adc_reg_access(struct iio_dev *indio_dev,
680 unsigned reg, unsigned writeval,
683 struct exynos_adc *info = iio_priv(indio_dev);
688 *readval = readl(info->regs + reg);
693 static const struct iio_info exynos_adc_iio_info = {
694 .read_raw = &exynos_read_raw,
695 .debugfs_reg_access = &exynos_adc_reg_access,
698 #define ADC_CHANNEL(_index, _id) { \
699 .type = IIO_VOLTAGE, \
703 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
704 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE), \
705 .datasheet_name = _id, \
708 static const struct iio_chan_spec exynos_adc_iio_channels[] = {
709 ADC_CHANNEL(0, "adc0"),
710 ADC_CHANNEL(1, "adc1"),
711 ADC_CHANNEL(2, "adc2"),
712 ADC_CHANNEL(3, "adc3"),
713 ADC_CHANNEL(4, "adc4"),
714 ADC_CHANNEL(5, "adc5"),
715 ADC_CHANNEL(6, "adc6"),
716 ADC_CHANNEL(7, "adc7"),
717 ADC_CHANNEL(8, "adc8"),
718 ADC_CHANNEL(9, "adc9"),
721 static int exynos_adc_remove_devices(struct device *dev, void *c)
723 struct platform_device *pdev = to_platform_device(dev);
725 platform_device_unregister(pdev);
730 static int exynos_adc_ts_open(struct input_dev *dev)
732 struct exynos_adc *info = input_get_drvdata(dev);
734 enable_irq(info->tsirq);
739 static void exynos_adc_ts_close(struct input_dev *dev)
741 struct exynos_adc *info = input_get_drvdata(dev);
743 disable_irq(info->tsirq);
746 static int exynos_adc_ts_init(struct exynos_adc *info)
750 if (info->tsirq <= 0)
753 info->input = input_allocate_device();
757 info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
758 info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
760 input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0);
761 input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0);
763 info->input->name = "S3C24xx TouchScreen";
764 info->input->id.bustype = BUS_HOST;
765 info->input->open = exynos_adc_ts_open;
766 info->input->close = exynos_adc_ts_close;
768 input_set_drvdata(info->input, info);
770 ret = input_register_device(info->input);
772 input_free_device(info->input);
776 disable_irq(info->tsirq);
777 ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr,
778 IRQF_ONESHOT, "touchscreen", info);
780 input_unregister_device(info->input);
785 static int exynos_adc_probe(struct platform_device *pdev)
787 struct exynos_adc *info = NULL;
788 struct device_node *np = pdev->dev.of_node;
789 struct s3c2410_ts_mach_info *pdata = dev_get_platdata(&pdev->dev);
790 struct iio_dev *indio_dev = NULL;
795 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
797 dev_err(&pdev->dev, "failed allocating iio device\n");
801 info = iio_priv(indio_dev);
803 info->data = exynos_adc_get_data(pdev);
805 dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
809 info->regs = devm_platform_ioremap_resource(pdev, 0);
810 if (IS_ERR(info->regs))
811 return PTR_ERR(info->regs);
814 if (info->data->needs_adc_phy) {
815 info->pmu_map = syscon_regmap_lookup_by_phandle(
817 "samsung,syscon-phandle");
818 if (IS_ERR(info->pmu_map)) {
819 dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
820 return PTR_ERR(info->pmu_map);
824 irq = platform_get_irq(pdev, 0);
829 irq = platform_get_irq(pdev, 1);
830 if (irq == -EPROBE_DEFER)
835 info->dev = &pdev->dev;
837 init_completion(&info->completion);
839 info->clk = devm_clk_get(&pdev->dev, "adc");
840 if (IS_ERR(info->clk)) {
841 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
843 return PTR_ERR(info->clk);
846 if (info->data->needs_sclk) {
847 info->sclk = devm_clk_get(&pdev->dev, "sclk");
848 if (IS_ERR(info->sclk)) {
850 "failed getting sclk clock, err = %ld\n",
851 PTR_ERR(info->sclk));
852 return PTR_ERR(info->sclk);
856 info->vdd = devm_regulator_get(&pdev->dev, "vdd");
857 if (IS_ERR(info->vdd))
858 return dev_err_probe(&pdev->dev, PTR_ERR(info->vdd),
859 "failed getting regulator");
861 ret = regulator_enable(info->vdd);
865 ret = exynos_adc_prepare_clk(info);
867 goto err_disable_reg;
869 ret = exynos_adc_enable_clk(info);
871 goto err_unprepare_clk;
873 platform_set_drvdata(pdev, indio_dev);
875 indio_dev->name = dev_name(&pdev->dev);
876 indio_dev->info = &exynos_adc_iio_info;
877 indio_dev->modes = INDIO_DIRECT_MODE;
878 indio_dev->channels = exynos_adc_iio_channels;
879 indio_dev->num_channels = info->data->num_channels;
881 mutex_init(&info->lock);
883 ret = request_irq(info->irq, exynos_adc_isr,
884 0, dev_name(&pdev->dev), info);
886 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
888 goto err_disable_clk;
891 ret = iio_device_register(indio_dev);
895 if (info->data->init_hw)
896 info->data->init_hw(info);
898 /* leave out any TS related code if unreachable */
899 if (IS_REACHABLE(CONFIG_INPUT)) {
900 has_ts = of_property_read_bool(pdev->dev.of_node,
901 "has-touchscreen") || pdata;
905 info->delay = pdata->delay;
910 ret = exynos_adc_ts_init(info);
914 ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
916 dev_err(&pdev->dev, "failed adding child nodes\n");
917 goto err_of_populate;
923 device_for_each_child(&indio_dev->dev, NULL,
924 exynos_adc_remove_devices);
926 input_unregister_device(info->input);
927 free_irq(info->tsirq, info);
930 iio_device_unregister(indio_dev);
932 free_irq(info->irq, info);
934 if (info->data->exit_hw)
935 info->data->exit_hw(info);
936 exynos_adc_disable_clk(info);
938 exynos_adc_unprepare_clk(info);
940 regulator_disable(info->vdd);
944 static int exynos_adc_remove(struct platform_device *pdev)
946 struct iio_dev *indio_dev = platform_get_drvdata(pdev);
947 struct exynos_adc *info = iio_priv(indio_dev);
949 if (IS_REACHABLE(CONFIG_INPUT) && info->input) {
950 free_irq(info->tsirq, info);
951 input_unregister_device(info->input);
953 device_for_each_child(&indio_dev->dev, NULL,
954 exynos_adc_remove_devices);
955 iio_device_unregister(indio_dev);
956 free_irq(info->irq, info);
957 if (info->data->exit_hw)
958 info->data->exit_hw(info);
959 exynos_adc_disable_clk(info);
960 exynos_adc_unprepare_clk(info);
961 regulator_disable(info->vdd);
966 #ifdef CONFIG_PM_SLEEP
967 static int exynos_adc_suspend(struct device *dev)
969 struct iio_dev *indio_dev = dev_get_drvdata(dev);
970 struct exynos_adc *info = iio_priv(indio_dev);
972 if (info->data->exit_hw)
973 info->data->exit_hw(info);
974 exynos_adc_disable_clk(info);
975 regulator_disable(info->vdd);
980 static int exynos_adc_resume(struct device *dev)
982 struct iio_dev *indio_dev = dev_get_drvdata(dev);
983 struct exynos_adc *info = iio_priv(indio_dev);
986 ret = regulator_enable(info->vdd);
990 ret = exynos_adc_enable_clk(info);
994 if (info->data->init_hw)
995 info->data->init_hw(info);
1001 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
1005 static struct platform_driver exynos_adc_driver = {
1006 .probe = exynos_adc_probe,
1007 .remove = exynos_adc_remove,
1009 .name = "exynos-adc",
1010 .of_match_table = exynos_adc_match,
1011 .pm = &exynos_adc_pm_ops,
1015 module_platform_driver(exynos_adc_driver);
1017 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
1018 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
1019 MODULE_LICENSE("GPL v2");