drivers/iio/adc/exynos_adc.c

   1 /*
   2  *  exynos_adc.c - Support for ADC in EXYNOS SoCs
   3  *
   4  *  8 ~ 10 channel, 10/12-bit ADC
   5  *
   6  *  Copyright (C) 2013 Naveen Krishna Chatradhi <ch.naveen@samsung.com>
   7  *
   8  *  This program is free software; you can redistribute it and/or modify
   9  *  it under the terms of the GNU General Public License as published by
  10  *  the Free Software Foundation; either version 2 of the License, or
  11  *  (at your option) any later version.
  12  *
  13  *  This program is distributed in the hope that it will be useful,
  14  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  *  GNU General Public License for more details.
  17  *
  18  *  You should have received a copy of the GNU General Public License
  19  *  along with this program; if not, write to the Free Software
  20  *  Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  21  */
  22
  23 #include <linux/module.h>
  24 #include <linux/platform_device.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/kernel.h>
  29 #include <linux/slab.h>
  30 #include <linux/io.h>
  31 #include <linux/clk.h>
  32 #include <linux/completion.h>
  33 #include <linux/of.h>
  34 #include <linux/of_irq.h>
  35 #include <linux/regulator/consumer.h>
  36 #include <linux/of_platform.h>
  37 #include <linux/err.h>
  38 #include <linux/input.h>
  39
  40 #include <linux/iio/iio.h>
  41 #include <linux/iio/machine.h>
  42 #include <linux/iio/driver.h>
  43 #include <linux/mfd/syscon.h>
  44 #include <linux/regmap.h>
  45
  46 #include <linux/platform_data/touchscreen-s3c2410.h>
  47
  48 /* S3C/EXYNOS4412/5250 ADC_V1 registers definitions */
  49 #define ADC_V1_CON(x)           ((x) + 0x00)
  50 #define ADC_V1_TSC(x)           ((x) + 0x04)
  51 #define ADC_V1_DLY(x)           ((x) + 0x08)
  52 #define ADC_V1_DATX(x)          ((x) + 0x0C)
  53 #define ADC_V1_DATY(x)          ((x) + 0x10)
  54 #define ADC_V1_UPDN(x)          ((x) + 0x14)
  55 #define ADC_V1_INTCLR(x)        ((x) + 0x18)
  56 #define ADC_V1_MUX(x)           ((x) + 0x1c)
  57 #define ADC_V1_CLRINTPNDNUP(x)  ((x) + 0x20)
  58
  59 /* S3C2410 ADC registers definitions */
  60 #define ADC_S3C2410_MUX(x)      ((x) + 0x18)
  61
  62 /* Future ADC_V2 registers definitions */
  63 #define ADC_V2_CON1(x)          ((x) + 0x00)
  64 #define ADC_V2_CON2(x)          ((x) + 0x04)
  65 #define ADC_V2_STAT(x)          ((x) + 0x08)
  66 #define ADC_V2_INT_EN(x)        ((x) + 0x10)
  67 #define ADC_V2_INT_ST(x)        ((x) + 0x14)
  68 #define ADC_V2_VER(x)           ((x) + 0x20)
  69
  70 /* Bit definitions for ADC_V1 */
  71 #define ADC_V1_CON_RES          (1u << 16)
  72 #define ADC_V1_CON_PRSCEN       (1u << 14)
  73 #define ADC_V1_CON_PRSCLV(x)    (((x) & 0xFF) << 6)
  74 #define ADC_V1_CON_STANDBY      (1u << 2)
  75
  76 /* Bit definitions for S3C2410 ADC */
  77 #define ADC_S3C2410_CON_SELMUX(x) (((x) & 7) << 3)
  78 #define ADC_S3C2410_DATX_MASK   0x3FF
  79 #define ADC_S3C2416_CON_RES_SEL (1u << 3)
  80
  81 /* touch screen always uses channel 0 */
  82 #define ADC_S3C2410_MUX_TS      0
  83
  84 /* ADCTSC Register Bits */
  85 #define ADC_S3C2443_TSC_UD_SEN          (1u << 8)
  86 #define ADC_S3C2410_TSC_YM_SEN          (1u << 7)
  87 #define ADC_S3C2410_TSC_YP_SEN          (1u << 6)
  88 #define ADC_S3C2410_TSC_XM_SEN          (1u << 5)
  89 #define ADC_S3C2410_TSC_XP_SEN          (1u << 4)
  90 #define ADC_S3C2410_TSC_PULL_UP_DISABLE (1u << 3)
  91 #define ADC_S3C2410_TSC_AUTO_PST        (1u << 2)
  92 #define ADC_S3C2410_TSC_XY_PST(x)       (((x) & 0x3) << 0)
  93
  94 #define ADC_TSC_WAIT4INT (ADC_S3C2410_TSC_YM_SEN | \
  95                          ADC_S3C2410_TSC_YP_SEN | \
  96                          ADC_S3C2410_TSC_XP_SEN | \
  97                          ADC_S3C2410_TSC_XY_PST(3))
  98
  99 #define ADC_TSC_AUTOPST (ADC_S3C2410_TSC_YM_SEN | \
 100                          ADC_S3C2410_TSC_YP_SEN | \
 101                          ADC_S3C2410_TSC_XP_SEN | \
 102                          ADC_S3C2410_TSC_AUTO_PST | \
 103                          ADC_S3C2410_TSC_XY_PST(0))
 104
 105 /* Bit definitions for ADC_V2 */
 106 #define ADC_V2_CON1_SOFT_RESET  (1u << 2)
 107
 108 #define ADC_V2_CON2_OSEL        (1u << 10)
 109 #define ADC_V2_CON2_ESEL        (1u << 9)
 110 #define ADC_V2_CON2_HIGHF       (1u << 8)
 111 #define ADC_V2_CON2_C_TIME(x)   (((x) & 7) << 4)
 112 #define ADC_V2_CON2_ACH_SEL(x)  (((x) & 0xF) << 0)
 113 #define ADC_V2_CON2_ACH_MASK    0xF
 114
 115 #define MAX_ADC_V2_CHANNELS             10
 116 #define MAX_ADC_V1_CHANNELS             8
 117 #define MAX_EXYNOS3250_ADC_CHANNELS     2
 118 #define MAX_EXYNOS4212_ADC_CHANNELS     4
 119 #define MAX_S5PV210_ADC_CHANNELS        10
 120
 121 /* Bit definitions common for ADC_V1 and ADC_V2 */
 122 #define ADC_CON_EN_START        (1u << 0)
 123 #define ADC_CON_EN_START_MASK   (0x3 << 0)
 124 #define ADC_DATX_PRESSED        (1u << 15)
 125 #define ADC_DATX_MASK           0xFFF
 126 #define ADC_DATY_MASK           0xFFF
 127
 128 #define EXYNOS_ADC_TIMEOUT      (msecs_to_jiffies(100))
 129
 130 #define EXYNOS_ADCV1_PHY_OFFSET 0x0718
 131 #define EXYNOS_ADCV2_PHY_OFFSET 0x0720
 132
 133 struct exynos_adc {
 134         struct exynos_adc_data  *data;
 135         struct device           *dev;
 136         struct input_dev        *input;
 137         void __iomem            *regs;
 138         struct regmap           *pmu_map;
 139         struct clk              *clk;
 140         struct clk              *sclk;
 141         unsigned int            irq;
 142         unsigned int            tsirq;
 143         unsigned int            delay;
 144         struct regulator        *vdd;
 145
 146         struct completion       completion;
 147
 148         u32                     value;
 149         unsigned int            version;
 150
 151         bool                    read_ts;
 152         u32                     ts_x;
 153         u32                     ts_y;
 154 };
 155
 156 struct exynos_adc_data {
 157         int num_channels;
 158         bool needs_sclk;
 159         bool needs_adc_phy;
 160         int phy_offset;
 161         u32 mask;
 162
 163         void (*init_hw)(struct exynos_adc *info);
 164         void (*exit_hw)(struct exynos_adc *info);
 165         void (*clear_irq)(struct exynos_adc *info);
 166         void (*start_conv)(struct exynos_adc *info, unsigned long addr);
 167 };
 168
 169 static void exynos_adc_unprepare_clk(struct exynos_adc *info)
 170 {
 171         if (info->data->needs_sclk)
 172                 clk_unprepare(info->sclk);
 173         clk_unprepare(info->clk);
 174 }
 175
 176 static int exynos_adc_prepare_clk(struct exynos_adc *info)
 177 {
 178         int ret;
 179
 180         ret = clk_prepare(info->clk);
 181         if (ret) {
 182                 dev_err(info->dev, "failed preparing adc clock: %d\n", ret);
 183                 return ret;
 184         }
 185
 186         if (info->data->needs_sclk) {
 187                 ret = clk_prepare(info->sclk);
 188                 if (ret) {
 189                         clk_unprepare(info->clk);
 190                         dev_err(info->dev,
 191                                 "failed preparing sclk_adc clock: %d\n", ret);
 192                         return ret;
 193                 }
 194         }
 195
 196         return 0;
 197 }
 198
 199 static void exynos_adc_disable_clk(struct exynos_adc *info)
 200 {
 201         if (info->data->needs_sclk)
 202                 clk_disable(info->sclk);
 203         clk_disable(info->clk);
 204 }
 205
 206 static int exynos_adc_enable_clk(struct exynos_adc *info)
 207 {
 208         int ret;
 209
 210         ret = clk_enable(info->clk);
 211         if (ret) {
 212                 dev_err(info->dev, "failed enabling adc clock: %d\n", ret);
 213                 return ret;
 214         }
 215
 216         if (info->data->needs_sclk) {
 217                 ret = clk_enable(info->sclk);
 218                 if (ret) {
 219                         clk_disable(info->clk);
 220                         dev_err(info->dev,
 221                                 "failed enabling sclk_adc clock: %d\n", ret);
 222                         return ret;
 223                 }
 224         }
 225
 226         return 0;
 227 }
 228
 229 static void exynos_adc_v1_init_hw(struct exynos_adc *info)
 230 {
 231         u32 con1;
 232
 233         if (info->data->needs_adc_phy)
 234                 regmap_write(info->pmu_map, info->data->phy_offset, 1);
 235
 236         /* set default prescaler values and Enable prescaler */
 237         con1 =  ADC_V1_CON_PRSCLV(49) | ADC_V1_CON_PRSCEN;
 238
 239         /* Enable 12-bit ADC resolution */
 240         con1 |= ADC_V1_CON_RES;
 241         writel(con1, ADC_V1_CON(info->regs));
 242
 243         /* set touchscreen delay */
 244         writel(info->delay, ADC_V1_DLY(info->regs));
 245 }
 246
 247 static void exynos_adc_v1_exit_hw(struct exynos_adc *info)
 248 {
 249         u32 con;
 250
 251         if (info->data->needs_adc_phy)
 252                 regmap_write(info->pmu_map, info->data->phy_offset, 0);
 253
 254         con = readl(ADC_V1_CON(info->regs));
 255         con |= ADC_V1_CON_STANDBY;
 256         writel(con, ADC_V1_CON(info->regs));
 257 }
 258
 259 static void exynos_adc_v1_clear_irq(struct exynos_adc *info)
 260 {
 261         writel(1, ADC_V1_INTCLR(info->regs));
 262 }
 263
 264 static void exynos_adc_v1_start_conv(struct exynos_adc *info,
 265                                      unsigned long addr)
 266 {
 267         u32 con1;
 268
 269         writel(addr, ADC_V1_MUX(info->regs));
 270
 271         con1 = readl(ADC_V1_CON(info->regs));
 272         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 273 }
 274
 275 /* Exynos4212 and 4412 is like ADCv1 but with four channels only */
 276 static const struct exynos_adc_data exynos4212_adc_data = {
 277         .num_channels   = MAX_EXYNOS4212_ADC_CHANNELS,
 278         .mask           = ADC_DATX_MASK,        /* 12 bit ADC resolution */
 279         .needs_adc_phy  = true,
 280         .phy_offset     = EXYNOS_ADCV1_PHY_OFFSET,
 281
 282         .init_hw        = exynos_adc_v1_init_hw,
 283         .exit_hw        = exynos_adc_v1_exit_hw,
 284         .clear_irq      = exynos_adc_v1_clear_irq,
 285         .start_conv     = exynos_adc_v1_start_conv,
 286 };
 287
 288 static const struct exynos_adc_data exynos_adc_v1_data = {
 289         .num_channels   = MAX_ADC_V1_CHANNELS,
 290         .mask           = ADC_DATX_MASK,        /* 12 bit ADC resolution */
 291         .needs_adc_phy  = true,
 292         .phy_offset     = EXYNOS_ADCV1_PHY_OFFSET,
 293
 294         .init_hw        = exynos_adc_v1_init_hw,
 295         .exit_hw        = exynos_adc_v1_exit_hw,
 296         .clear_irq      = exynos_adc_v1_clear_irq,
 297         .start_conv     = exynos_adc_v1_start_conv,
 298 };
 299
 300 static const struct exynos_adc_data exynos_adc_s5pv210_data = {
 301         .num_channels   = MAX_S5PV210_ADC_CHANNELS,
 302         .mask           = ADC_DATX_MASK,        /* 12 bit ADC resolution */
 303
 304         .init_hw        = exynos_adc_v1_init_hw,
 305         .exit_hw        = exynos_adc_v1_exit_hw,
 306         .clear_irq      = exynos_adc_v1_clear_irq,
 307         .start_conv     = exynos_adc_v1_start_conv,
 308 };
 309
 310 static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
 311                                           unsigned long addr)
 312 {
 313         u32 con1;
 314
 315         /* Enable 12 bit ADC resolution */
 316         con1 = readl(ADC_V1_CON(info->regs));
 317         con1 |= ADC_S3C2416_CON_RES_SEL;
 318         writel(con1, ADC_V1_CON(info->regs));
 319
 320         /* Select channel for S3C2416 */
 321         writel(addr, ADC_S3C2410_MUX(info->regs));
 322
 323         con1 = readl(ADC_V1_CON(info->regs));
 324         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 325 }
 326
 327 static struct exynos_adc_data const exynos_adc_s3c2416_data = {
 328         .num_channels   = MAX_ADC_V1_CHANNELS,
 329         .mask           = ADC_DATX_MASK,        /* 12 bit ADC resolution */
 330
 331         .init_hw        = exynos_adc_v1_init_hw,
 332         .exit_hw        = exynos_adc_v1_exit_hw,
 333         .start_conv     = exynos_adc_s3c2416_start_conv,
 334 };
 335
 336 static void exynos_adc_s3c2443_start_conv(struct exynos_adc *info,
 337                                           unsigned long addr)
 338 {
 339         u32 con1;
 340
 341         /* Select channel for S3C2433 */
 342         writel(addr, ADC_S3C2410_MUX(info->regs));
 343
 344         con1 = readl(ADC_V1_CON(info->regs));
 345         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 346 }
 347
 348 static struct exynos_adc_data const exynos_adc_s3c2443_data = {
 349         .num_channels   = MAX_ADC_V1_CHANNELS,
 350         .mask           = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
 351
 352         .init_hw        = exynos_adc_v1_init_hw,
 353         .exit_hw        = exynos_adc_v1_exit_hw,
 354         .start_conv     = exynos_adc_s3c2443_start_conv,
 355 };
 356
 357 static void exynos_adc_s3c64xx_start_conv(struct exynos_adc *info,
 358                                           unsigned long addr)
 359 {
 360         u32 con1;
 361
 362         con1 = readl(ADC_V1_CON(info->regs));
 363         con1 &= ~ADC_S3C2410_CON_SELMUX(0x7);
 364         con1 |= ADC_S3C2410_CON_SELMUX(addr);
 365         writel(con1 | ADC_CON_EN_START, ADC_V1_CON(info->regs));
 366 }
 367
 368 static struct exynos_adc_data const exynos_adc_s3c24xx_data = {
 369         .num_channels   = MAX_ADC_V1_CHANNELS,
 370         .mask           = ADC_S3C2410_DATX_MASK, /* 10 bit ADC resolution */
 371
 372         .init_hw        = exynos_adc_v1_init_hw,
 373         .exit_hw        = exynos_adc_v1_exit_hw,
 374         .start_conv     = exynos_adc_s3c64xx_start_conv,
 375 };
 376
 377 static struct exynos_adc_data const exynos_adc_s3c64xx_data = {
 378         .num_channels   = MAX_ADC_V1_CHANNELS,
 379         .mask           = ADC_DATX_MASK,        /* 12 bit ADC resolution */
 380
 381         .init_hw        = exynos_adc_v1_init_hw,
 382         .exit_hw        = exynos_adc_v1_exit_hw,
 383         .clear_irq      = exynos_adc_v1_clear_irq,
 384         .start_conv     = exynos_adc_s3c64xx_start_conv,
 385 };
 386
 387 static void exynos_adc_v2_init_hw(struct exynos_adc *info)
 388 {
 389         u32 con1, con2;
 390
 391         if (info->data->needs_adc_phy)
 392                 regmap_write(info->pmu_map, info->data->phy_offset, 1);
 393
 394         con1 = ADC_V2_CON1_SOFT_RESET;
 395         writel(con1, ADC_V2_CON1(info->regs));
 396
 397         con2 = ADC_V2_CON2_OSEL | ADC_V2_CON2_ESEL |
 398                 ADC_V2_CON2_HIGHF | ADC_V2_CON2_C_TIME(0);
 399         writel(con2, ADC_V2_CON2(info->regs));
 400
 401         /* Enable interrupts */
 402         writel(1, ADC_V2_INT_EN(info->regs));
 403 }
 404
 405 static void exynos_adc_v2_exit_hw(struct exynos_adc *info)
 406 {
 407         u32 con;
 408
 409         if (info->data->needs_adc_phy)
 410                 regmap_write(info->pmu_map, info->data->phy_offset, 0);
 411
 412         con = readl(ADC_V2_CON1(info->regs));
 413         con &= ~ADC_CON_EN_START;
 414         writel(con, ADC_V2_CON1(info->regs));
 415 }
 416
 417 static void exynos_adc_v2_clear_irq(struct exynos_adc *info)
 418 {
 419         writel(1, ADC_V2_INT_ST(info->regs));
 420 }
 421
 422 static void exynos_adc_v2_start_conv(struct exynos_adc *info,
 423                                      unsigned long addr)
 424 {
 425         u32 con1, con2;
 426
 427         con2 = readl(ADC_V2_CON2(info->regs));
 428         con2 &= ~ADC_V2_CON2_ACH_MASK;
 429         con2 |= ADC_V2_CON2_ACH_SEL(addr);
 430         writel(con2, ADC_V2_CON2(info->regs));
 431
 432         con1 = readl(ADC_V2_CON1(info->regs));
 433         writel(con1 | ADC_CON_EN_START, ADC_V2_CON1(info->regs));
 434 }
 435
 436 static const struct exynos_adc_data exynos_adc_v2_data = {
 437         .num_channels   = MAX_ADC_V2_CHANNELS,
 438         .mask           = ADC_DATX_MASK, /* 12 bit ADC resolution */
 439         .needs_adc_phy  = true,
 440         .phy_offset     = EXYNOS_ADCV2_PHY_OFFSET,
 441
 442         .init_hw        = exynos_adc_v2_init_hw,
 443         .exit_hw        = exynos_adc_v2_exit_hw,
 444         .clear_irq      = exynos_adc_v2_clear_irq,
 445         .start_conv     = exynos_adc_v2_start_conv,
 446 };
 447
 448 static const struct exynos_adc_data exynos3250_adc_data = {
 449         .num_channels   = MAX_EXYNOS3250_ADC_CHANNELS,
 450         .mask           = ADC_DATX_MASK, /* 12 bit ADC resolution */
 451         .needs_sclk     = true,
 452         .needs_adc_phy  = true,
 453         .phy_offset     = EXYNOS_ADCV1_PHY_OFFSET,
 454
 455         .init_hw        = exynos_adc_v2_init_hw,
 456         .exit_hw        = exynos_adc_v2_exit_hw,
 457         .clear_irq      = exynos_adc_v2_clear_irq,
 458         .start_conv     = exynos_adc_v2_start_conv,
 459 };
 460
 461 static void exynos_adc_exynos7_init_hw(struct exynos_adc *info)
 462 {
 463         u32 con1, con2;
 464
 465         if (info->data->needs_adc_phy)
 466                 regmap_write(info->pmu_map, info->data->phy_offset, 1);
 467
 468         con1 = ADC_V2_CON1_SOFT_RESET;
 469         writel(con1, ADC_V2_CON1(info->regs));
 470
 471         con2 = readl(ADC_V2_CON2(info->regs));
 472         con2 &= ~ADC_V2_CON2_C_TIME(7);
 473         con2 |= ADC_V2_CON2_C_TIME(0);
 474         writel(con2, ADC_V2_CON2(info->regs));
 475
 476         /* Enable interrupts */
 477         writel(1, ADC_V2_INT_EN(info->regs));
 478 }
 479
 480 static const struct exynos_adc_data exynos7_adc_data = {
 481         .num_channels   = MAX_ADC_V1_CHANNELS,
 482         .mask           = ADC_DATX_MASK, /* 12 bit ADC resolution */
 483
 484         .init_hw        = exynos_adc_exynos7_init_hw,
 485         .exit_hw        = exynos_adc_v2_exit_hw,
 486         .clear_irq      = exynos_adc_v2_clear_irq,
 487         .start_conv     = exynos_adc_v2_start_conv,
 488 };
 489
 490 static const struct of_device_id exynos_adc_match[] = {
 491         {
 492                 .compatible = "samsung,s3c2410-adc",
 493                 .data = &exynos_adc_s3c24xx_data,
 494         }, {
 495                 .compatible = "samsung,s3c2416-adc",
 496                 .data = &exynos_adc_s3c2416_data,
 497         }, {
 498                 .compatible = "samsung,s3c2440-adc",
 499                 .data = &exynos_adc_s3c24xx_data,
 500         }, {
 501                 .compatible = "samsung,s3c2443-adc",
 502                 .data = &exynos_adc_s3c2443_data,
 503         }, {
 504                 .compatible = "samsung,s3c6410-adc",
 505                 .data = &exynos_adc_s3c64xx_data,
 506         }, {
 507                 .compatible = "samsung,s5pv210-adc",
 508                 .data = &exynos_adc_s5pv210_data,
 509         }, {
 510                 .compatible = "samsung,exynos4212-adc",
 511                 .data = &exynos4212_adc_data,
 512         }, {
 513                 .compatible = "samsung,exynos-adc-v1",
 514                 .data = &exynos_adc_v1_data,
 515         }, {
 516                 .compatible = "samsung,exynos-adc-v2",
 517                 .data = &exynos_adc_v2_data,
 518         }, {
 519                 .compatible = "samsung,exynos3250-adc",
 520                 .data = &exynos3250_adc_data,
 521         }, {
 522                 .compatible = "samsung,exynos7-adc",
 523                 .data = &exynos7_adc_data,
 524         },
 525         {},
 526 };
 527 MODULE_DEVICE_TABLE(of, exynos_adc_match);
 528
 529 static struct exynos_adc_data *exynos_adc_get_data(struct platform_device *pdev)
 530 {
 531         const struct of_device_id *match;
 532
 533         match = of_match_node(exynos_adc_match, pdev->dev.of_node);
 534         return (struct exynos_adc_data *)match->data;
 535 }
 536
 537 static int exynos_read_raw(struct iio_dev *indio_dev,
 538                                 struct iio_chan_spec const *chan,
 539                                 int *val,
 540                                 int *val2,
 541                                 long mask)
 542 {
 543         struct exynos_adc *info = iio_priv(indio_dev);
 544         unsigned long timeout;
 545         int ret;
 546
 547         if (mask != IIO_CHAN_INFO_RAW)
 548                 return -EINVAL;
 549
 550         mutex_lock(&indio_dev->mlock);
 551         reinit_completion(&info->completion);
 552
 553         /* Select the channel to be used and Trigger conversion */
 554         if (info->data->start_conv)
 555                 info->data->start_conv(info, chan->address);
 556
 557         timeout = wait_for_completion_timeout(&info->completion,
 558                                               EXYNOS_ADC_TIMEOUT);
 559         if (timeout == 0) {
 560                 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
 561                 if (info->data->init_hw)
 562                         info->data->init_hw(info);
 563                 ret = -ETIMEDOUT;
 564         } else {
 565                 *val = info->value;
 566                 *val2 = 0;
 567                 ret = IIO_VAL_INT;
 568         }
 569
 570         mutex_unlock(&indio_dev->mlock);
 571
 572         return ret;
 573 }
 574
 575 static int exynos_read_s3c64xx_ts(struct iio_dev *indio_dev, int *x, int *y)
 576 {
 577         struct exynos_adc *info = iio_priv(indio_dev);
 578         unsigned long timeout;
 579         int ret;
 580
 581         mutex_lock(&indio_dev->mlock);
 582         info->read_ts = true;
 583
 584         reinit_completion(&info->completion);
 585
 586         writel(ADC_S3C2410_TSC_PULL_UP_DISABLE | ADC_TSC_AUTOPST,
 587                ADC_V1_TSC(info->regs));
 588
 589         /* Select the ts channel to be used and Trigger conversion */
 590         info->data->start_conv(info, ADC_S3C2410_MUX_TS);
 591
 592         timeout = wait_for_completion_timeout(&info->completion,
 593                                               EXYNOS_ADC_TIMEOUT);
 594         if (timeout == 0) {
 595                 dev_warn(&indio_dev->dev, "Conversion timed out! Resetting\n");
 596                 if (info->data->init_hw)
 597                         info->data->init_hw(info);
 598                 ret = -ETIMEDOUT;
 599         } else {
 600                 *x = info->ts_x;
 601                 *y = info->ts_y;
 602                 ret = 0;
 603         }
 604
 605         info->read_ts = false;
 606         mutex_unlock(&indio_dev->mlock);
 607
 608         return ret;
 609 }
 610
 611 static irqreturn_t exynos_adc_isr(int irq, void *dev_id)
 612 {
 613         struct exynos_adc *info = dev_id;
 614         u32 mask = info->data->mask;
 615
 616         /* Read value */
 617         if (info->read_ts) {
 618                 info->ts_x = readl(ADC_V1_DATX(info->regs));
 619                 info->ts_y = readl(ADC_V1_DATY(info->regs));
 620                 writel(ADC_TSC_WAIT4INT | ADC_S3C2443_TSC_UD_SEN, ADC_V1_TSC(info->regs));
 621         } else {
 622                 info->value = readl(ADC_V1_DATX(info->regs)) & mask;
 623         }
 624
 625         /* clear irq */
 626         if (info->data->clear_irq)
 627                 info->data->clear_irq(info);
 628
 629         complete(&info->completion);
 630
 631         return IRQ_HANDLED;
 632 }
 633
 634 /*
 635  * Here we (ab)use a threaded interrupt handler to stay running
 636  * for as long as the touchscreen remains pressed, we report
 637  * a new event with the latest data and then sleep until the
 638  * next timer tick. This mirrors the behavior of the old
 639  * driver, with much less code.
 640  */
 641 static irqreturn_t exynos_ts_isr(int irq, void *dev_id)
 642 {
 643         struct exynos_adc *info = dev_id;
 644         struct iio_dev *dev = dev_get_drvdata(info->dev);
 645         u32 x, y;
 646         bool pressed;
 647         int ret;
 648
 649         while (info->input->users) {
 650                 ret = exynos_read_s3c64xx_ts(dev, &x, &y);
 651                 if (ret == -ETIMEDOUT)
 652                         break;
 653
 654                 pressed = x & y & ADC_DATX_PRESSED;
 655                 if (!pressed) {
 656                         input_report_key(info->input, BTN_TOUCH, 0);
 657                         input_sync(info->input);
 658                         break;
 659                 }
 660
 661                 input_report_abs(info->input, ABS_X, x & ADC_DATX_MASK);
 662                 input_report_abs(info->input, ABS_Y, y & ADC_DATY_MASK);
 663                 input_report_key(info->input, BTN_TOUCH, 1);
 664                 input_sync(info->input);
 665
 666                 usleep_range(1000, 1100);
 667         };
 668
 669         writel(0, ADC_V1_CLRINTPNDNUP(info->regs));
 670
 671         return IRQ_HANDLED;
 672 }
 673
 674 static int exynos_adc_reg_access(struct iio_dev *indio_dev,
 675                               unsigned reg, unsigned writeval,
 676                               unsigned *readval)
 677 {
 678         struct exynos_adc *info = iio_priv(indio_dev);
 679
 680         if (readval == NULL)
 681                 return -EINVAL;
 682
 683         *readval = readl(info->regs + reg);
 684
 685         return 0;
 686 }
 687
 688 static const struct iio_info exynos_adc_iio_info = {
 689         .read_raw = &exynos_read_raw,
 690         .debugfs_reg_access = &exynos_adc_reg_access,
 691 };
 692
 693 #define ADC_CHANNEL(_index, _id) {                      \
 694         .type = IIO_VOLTAGE,                            \
 695         .indexed = 1,                                   \
 696         .channel = _index,                              \
 697         .address = _index,                              \
 698         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),   \
 699         .datasheet_name = _id,                          \
 700 }
 701
 702 static const struct iio_chan_spec exynos_adc_iio_channels[] = {
 703         ADC_CHANNEL(0, "adc0"),
 704         ADC_CHANNEL(1, "adc1"),
 705         ADC_CHANNEL(2, "adc2"),
 706         ADC_CHANNEL(3, "adc3"),
 707         ADC_CHANNEL(4, "adc4"),
 708         ADC_CHANNEL(5, "adc5"),
 709         ADC_CHANNEL(6, "adc6"),
 710         ADC_CHANNEL(7, "adc7"),
 711         ADC_CHANNEL(8, "adc8"),
 712         ADC_CHANNEL(9, "adc9"),
 713 };
 714
 715 static int exynos_adc_remove_devices(struct device *dev, void *c)
 716 {
 717         struct platform_device *pdev = to_platform_device(dev);
 718
 719         platform_device_unregister(pdev);
 720
 721         return 0;
 722 }
 723
 724 static int exynos_adc_ts_open(struct input_dev *dev)
 725 {
 726         struct exynos_adc *info = input_get_drvdata(dev);
 727
 728         enable_irq(info->tsirq);
 729
 730         return 0;
 731 }
 732
 733 static void exynos_adc_ts_close(struct input_dev *dev)
 734 {
 735         struct exynos_adc *info = input_get_drvdata(dev);
 736
 737         disable_irq(info->tsirq);
 738 }
 739
 740 static int exynos_adc_ts_init(struct exynos_adc *info)
 741 {
 742         int ret;
 743
 744         if (info->tsirq <= 0)
 745                 return -ENODEV;
 746
 747         info->input = input_allocate_device();
 748         if (!info->input)
 749                 return -ENOMEM;
 750
 751         info->input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
 752         info->input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
 753
 754         input_set_abs_params(info->input, ABS_X, 0, 0x3FF, 0, 0);
 755         input_set_abs_params(info->input, ABS_Y, 0, 0x3FF, 0, 0);
 756
 757         info->input->name = "S3C24xx TouchScreen";
 758         info->input->id.bustype = BUS_HOST;
 759         info->input->open = exynos_adc_ts_open;
 760         info->input->close = exynos_adc_ts_close;
 761
 762         input_set_drvdata(info->input, info);
 763
 764         ret = input_register_device(info->input);
 765         if (ret) {
 766                 input_free_device(info->input);
 767                 return ret;
 768         }
 769
 770         disable_irq(info->tsirq);
 771         ret = request_threaded_irq(info->tsirq, NULL, exynos_ts_isr,
 772                                    IRQF_ONESHOT, "touchscreen", info);
 773         if (ret)
 774                 input_unregister_device(info->input);
 775
 776         return ret;
 777 }
 778
 779 static int exynos_adc_probe(struct platform_device *pdev)
 780 {
 781         struct exynos_adc *info = NULL;
 782         struct device_node *np = pdev->dev.of_node;
 783         struct s3c2410_ts_mach_info *pdata = dev_get_platdata(&pdev->dev);
 784         struct iio_dev *indio_dev = NULL;
 785         struct resource *mem;
 786         bool has_ts = false;
 787         int ret = -ENODEV;
 788         int irq;
 789
 790         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(struct exynos_adc));
 791         if (!indio_dev) {
 792                 dev_err(&pdev->dev, "failed allocating iio device\n");
 793                 return -ENOMEM;
 794         }
 795
 796         info = iio_priv(indio_dev);
 797
 798         info->data = exynos_adc_get_data(pdev);
 799         if (!info->data) {
 800                 dev_err(&pdev->dev, "failed getting exynos_adc_data\n");
 801                 return -EINVAL;
 802         }
 803
 804         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 805         info->regs = devm_ioremap_resource(&pdev->dev, mem);
 806         if (IS_ERR(info->regs))
 807                 return PTR_ERR(info->regs);
 808
 809
 810         if (info->data->needs_adc_phy) {
 811                 info->pmu_map = syscon_regmap_lookup_by_phandle(
 812                                         pdev->dev.of_node,
 813                                         "samsung,syscon-phandle");
 814                 if (IS_ERR(info->pmu_map)) {
 815                         dev_err(&pdev->dev, "syscon regmap lookup failed.\n");
 816                         return PTR_ERR(info->pmu_map);
 817                 }
 818         }
 819
 820         irq = platform_get_irq(pdev, 0);
 821         if (irq < 0) {
 822                 dev_err(&pdev->dev, "no irq resource?\n");
 823                 return irq;
 824         }
 825         info->irq = irq;
 826
 827         irq = platform_get_irq(pdev, 1);
 828         if (irq == -EPROBE_DEFER)
 829                 return irq;
 830
 831         info->tsirq = irq;
 832
 833         info->dev = &pdev->dev;
 834
 835         init_completion(&info->completion);
 836
 837         info->clk = devm_clk_get(&pdev->dev, "adc");
 838         if (IS_ERR(info->clk)) {
 839                 dev_err(&pdev->dev, "failed getting clock, err = %ld\n",
 840                                                         PTR_ERR(info->clk));
 841                 return PTR_ERR(info->clk);
 842         }
 843
 844         if (info->data->needs_sclk) {
 845                 info->sclk = devm_clk_get(&pdev->dev, "sclk");
 846                 if (IS_ERR(info->sclk)) {
 847                         dev_err(&pdev->dev,
 848                                 "failed getting sclk clock, err = %ld\n",
 849                                 PTR_ERR(info->sclk));
 850                         return PTR_ERR(info->sclk);
 851                 }
 852         }
 853
 854         info->vdd = devm_regulator_get(&pdev->dev, "vdd");
 855         if (IS_ERR(info->vdd)) {
 856                 dev_err(&pdev->dev, "failed getting regulator, err = %ld\n",
 857                                                         PTR_ERR(info->vdd));
 858                 return PTR_ERR(info->vdd);
 859         }
 860
 861         ret = regulator_enable(info->vdd);
 862         if (ret)
 863                 return ret;
 864
 865         ret = exynos_adc_prepare_clk(info);
 866         if (ret)
 867                 goto err_disable_reg;
 868
 869         ret = exynos_adc_enable_clk(info);
 870         if (ret)
 871                 goto err_unprepare_clk;
 872
 873         platform_set_drvdata(pdev, indio_dev);
 874
 875         indio_dev->name = dev_name(&pdev->dev);
 876         indio_dev->dev.parent = &pdev->dev;
 877         indio_dev->dev.of_node = pdev->dev.of_node;
 878         indio_dev->info = &exynos_adc_iio_info;
 879         indio_dev->modes = INDIO_DIRECT_MODE;
 880         indio_dev->channels = exynos_adc_iio_channels;
 881         indio_dev->num_channels = info->data->num_channels;
 882
 883         ret = request_irq(info->irq, exynos_adc_isr,
 884                                         0, dev_name(&pdev->dev), info);
 885         if (ret < 0) {
 886                 dev_err(&pdev->dev, "failed requesting irq, irq = %d\n",
 887                                                         info->irq);
 888                 goto err_disable_clk;
 889         }
 890
 891         ret = iio_device_register(indio_dev);
 892         if (ret)
 893                 goto err_irq;
 894
 895         if (info->data->init_hw)
 896                 info->data->init_hw(info);
 897
 898         /* leave out any TS related code if unreachable */
 899         if (IS_REACHABLE(CONFIG_INPUT)) {
 900                 has_ts = of_property_read_bool(pdev->dev.of_node,
 901                                                "has-touchscreen") || pdata;
 902         }
 903
 904         if (pdata)
 905                 info->delay = pdata->delay;
 906         else
 907                 info->delay = 10000;
 908
 909         if (has_ts)
 910                 ret = exynos_adc_ts_init(info);
 911         if (ret)
 912                 goto err_iio;
 913
 914         ret = of_platform_populate(np, exynos_adc_match, NULL, &indio_dev->dev);
 915         if (ret < 0) {
 916                 dev_err(&pdev->dev, "failed adding child nodes\n");
 917                 goto err_of_populate;
 918         }
 919
 920         return 0;
 921
 922 err_of_populate:
 923         device_for_each_child(&indio_dev->dev, NULL,
 924                                 exynos_adc_remove_devices);
 925         if (has_ts) {
 926                 input_unregister_device(info->input);
 927                 free_irq(info->tsirq, info);
 928         }
 929 err_iio:
 930         iio_device_unregister(indio_dev);
 931 err_irq:
 932         free_irq(info->irq, info);
 933 err_disable_clk:
 934         if (info->data->exit_hw)
 935                 info->data->exit_hw(info);
 936         exynos_adc_disable_clk(info);
 937 err_unprepare_clk:
 938         exynos_adc_unprepare_clk(info);
 939 err_disable_reg:
 940         regulator_disable(info->vdd);
 941         return ret;
 942 }
 943
 944 static int exynos_adc_remove(struct platform_device *pdev)
 945 {
 946         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 947         struct exynos_adc *info = iio_priv(indio_dev);
 948
 949         if (IS_REACHABLE(CONFIG_INPUT) && info->input) {
 950                 free_irq(info->tsirq, info);
 951                 input_unregister_device(info->input);
 952         }
 953         device_for_each_child(&indio_dev->dev, NULL,
 954                                 exynos_adc_remove_devices);
 955         iio_device_unregister(indio_dev);
 956         free_irq(info->irq, info);
 957         if (info->data->exit_hw)
 958                 info->data->exit_hw(info);
 959         exynos_adc_disable_clk(info);
 960         exynos_adc_unprepare_clk(info);
 961         regulator_disable(info->vdd);
 962
 963         return 0;
 964 }
 965
 966 #ifdef CONFIG_PM_SLEEP
 967 static int exynos_adc_suspend(struct device *dev)
 968 {
 969         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 970         struct exynos_adc *info = iio_priv(indio_dev);
 971
 972         if (info->data->exit_hw)
 973                 info->data->exit_hw(info);
 974         exynos_adc_disable_clk(info);
 975         regulator_disable(info->vdd);
 976
 977         return 0;
 978 }
 979
 980 static int exynos_adc_resume(struct device *dev)
 981 {
 982         struct iio_dev *indio_dev = dev_get_drvdata(dev);
 983         struct exynos_adc *info = iio_priv(indio_dev);
 984         int ret;
 985
 986         ret = regulator_enable(info->vdd);
 987         if (ret)
 988                 return ret;
 989
 990         ret = exynos_adc_enable_clk(info);
 991         if (ret)
 992                 return ret;
 993
 994         if (info->data->init_hw)
 995                 info->data->init_hw(info);
 996
 997         return 0;
 998 }
 999 #endif
1000
1001 static SIMPLE_DEV_PM_OPS(exynos_adc_pm_ops,
1002                         exynos_adc_suspend,
1003                         exynos_adc_resume);
1004
1005 static struct platform_driver exynos_adc_driver = {
1006         .probe          = exynos_adc_probe,
1007         .remove         = exynos_adc_remove,
1008         .driver         = {
1009                 .name   = "exynos-adc",
1010                 .of_match_table = exynos_adc_match,
1011                 .pm     = &exynos_adc_pm_ops,
1012         },
1013 };
1014
1015 module_platform_driver(exynos_adc_driver);
1016
1017 MODULE_AUTHOR("Naveen Krishna Chatradhi <ch.naveen@samsung.com>");
1018 MODULE_DESCRIPTION("Samsung EXYNOS5 ADC driver");
1019 MODULE_LICENSE("GPL v2");