2 * Driver for ADC module on the Cirrus Logic EP93xx series of SoCs
4 * Copyright (C) 2015 Alexander Sverdlin
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * The driver uses polling to get the conversion status. According to EP93xx
11 * datasheets, reading ADCResult register starts the conversion, but user is also
12 * responsible for ensuring that delay between adjacent conversion triggers is
13 * long enough so that maximum allowed conversion rate is not exceeded. This
14 * basically renders IRQ mode unusable.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/err.h>
21 #include <linux/iio/iio.h>
23 #include <linux/irqflags.h>
24 #include <linux/module.h>
25 #include <linux/mutex.h>
26 #include <linux/platform_device.h>
29 * This code could benefit from real HR Timers, but jiffy granularity would
30 * lower ADC conversion rate down to CONFIG_HZ, so we fallback to busy wait
33 * HR Timers-based version loads CPU only up to 10% during back to back ADC
34 * conversion, while busy wait-based version consumes whole CPU power.
36 #ifdef CONFIG_HIGH_RES_TIMERS
37 #define ep93xx_adc_delay(usmin, usmax) usleep_range(usmin, usmax)
39 #define ep93xx_adc_delay(usmin, usmax) udelay(usmin)
42 #define EP93XX_ADC_RESULT 0x08
43 #define EP93XX_ADC_SDR BIT(31)
44 #define EP93XX_ADC_SWITCH 0x18
45 #define EP93XX_ADC_SW_LOCK 0x20
47 struct ep93xx_adc_priv {
54 #define EP93XX_ADC_CH(index, dname, swcfg) { \
55 .type = IIO_VOLTAGE, \
59 .datasheet_name = dname, \
60 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
61 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) | \
62 BIT(IIO_CHAN_INFO_OFFSET), \
66 * Numbering scheme for channels 0..4 is defined in EP9301 and EP9302 datasheets.
67 * EP9307, EP9312 and EP9312 have 3 channels more (total 8), but the numbering is
68 * not defined. So the last three are numbered randomly, let's say.
70 static const struct iio_chan_spec ep93xx_adc_channels[8] = {
71 EP93XX_ADC_CH(0, "YM", 0x608),
72 EP93XX_ADC_CH(1, "SXP", 0x680),
73 EP93XX_ADC_CH(2, "SXM", 0x640),
74 EP93XX_ADC_CH(3, "SYP", 0x620),
75 EP93XX_ADC_CH(4, "SYM", 0x610),
76 EP93XX_ADC_CH(5, "XP", 0x601),
77 EP93XX_ADC_CH(6, "XM", 0x602),
78 EP93XX_ADC_CH(7, "YP", 0x604),
81 static int ep93xx_read_raw(struct iio_dev *iiodev,
82 struct iio_chan_spec const *channel, int *value,
83 int *shift, long mask)
85 struct ep93xx_adc_priv *priv = iio_priv(iiodev);
86 unsigned long timeout;
90 case IIO_CHAN_INFO_RAW:
91 mutex_lock(&priv->lock);
92 if (priv->lastch != channel->channel) {
93 priv->lastch = channel->channel;
95 * Switch register is software-locked, unlocking must be
96 * immediately followed by write
99 writel_relaxed(0xAA, priv->base + EP93XX_ADC_SW_LOCK);
100 writel_relaxed(channel->address,
101 priv->base + EP93XX_ADC_SWITCH);
104 * Settling delay depends on module clock and could be
107 ep93xx_adc_delay(2000, 2000);
109 /* Start the conversion, eventually discarding old result */
110 readl_relaxed(priv->base + EP93XX_ADC_RESULT);
111 /* Ensure maximum conversion rate is not exceeded */
112 ep93xx_adc_delay(DIV_ROUND_UP(1000000, 925),
113 DIV_ROUND_UP(1000000, 925));
114 /* At this point conversion must be completed, but anyway... */
116 timeout = jiffies + msecs_to_jiffies(1) + 1;
120 t = readl_relaxed(priv->base + EP93XX_ADC_RESULT);
121 if (t & EP93XX_ADC_SDR) {
122 *value = sign_extend32(t, 15);
126 if (time_after(jiffies, timeout)) {
127 dev_err(&iiodev->dev, "Conversion timeout\n");
134 mutex_unlock(&priv->lock);
137 case IIO_CHAN_INFO_OFFSET:
138 /* According to datasheet, range is -25000..25000 */
142 case IIO_CHAN_INFO_SCALE:
143 /* Typical supply voltage is 3.3v */
144 *value = (1ULL << 32) * 3300 / 50000;
146 return IIO_VAL_FRACTIONAL_LOG2;
152 static const struct iio_info ep93xx_adc_info = {
153 .driver_module = THIS_MODULE,
154 .read_raw = ep93xx_read_raw,
157 static int ep93xx_adc_probe(struct platform_device *pdev)
160 struct iio_dev *iiodev;
161 struct ep93xx_adc_priv *priv;
163 struct resource *res;
165 iiodev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));
168 priv = iio_priv(iiodev);
170 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
172 dev_err(&pdev->dev, "Cannot obtain memory resource\n");
175 priv->base = devm_ioremap_resource(&pdev->dev, res);
176 if (IS_ERR(priv->base)) {
177 dev_err(&pdev->dev, "Cannot map memory resource\n");
178 return PTR_ERR(priv->base);
181 iiodev->dev.parent = &pdev->dev;
182 iiodev->name = dev_name(&pdev->dev);
183 iiodev->modes = INDIO_DIRECT_MODE;
184 iiodev->info = &ep93xx_adc_info;
185 iiodev->num_channels = ARRAY_SIZE(ep93xx_adc_channels);
186 iiodev->channels = ep93xx_adc_channels;
189 mutex_init(&priv->lock);
191 platform_set_drvdata(pdev, iiodev);
193 priv->clk = devm_clk_get(&pdev->dev, NULL);
194 if (IS_ERR(priv->clk)) {
195 dev_err(&pdev->dev, "Cannot obtain clock\n");
196 return PTR_ERR(priv->clk);
199 pclk = clk_get_parent(priv->clk);
201 dev_warn(&pdev->dev, "Cannot obtain parent clock\n");
204 * This is actually a place for improvement:
205 * EP93xx ADC supports two clock divisors -- 4 and 16,
206 * resulting in conversion rates 3750 and 925 samples per second
207 * with 500us or 2ms settling time respectively.
208 * One might find this interesting enough to be configurable.
210 ret = clk_set_rate(priv->clk, clk_get_rate(pclk) / 16);
212 dev_warn(&pdev->dev, "Cannot set clock rate\n");
214 * We can tolerate rate setting failure because the module should
219 ret = clk_enable(priv->clk);
221 dev_err(&pdev->dev, "Cannot enable clock\n");
225 ret = iio_device_register(iiodev);
227 clk_disable(priv->clk);
232 static int ep93xx_adc_remove(struct platform_device *pdev)
234 struct iio_dev *iiodev = platform_get_drvdata(pdev);
235 struct ep93xx_adc_priv *priv = iio_priv(iiodev);
237 iio_device_unregister(iiodev);
238 clk_disable(priv->clk);
243 static struct platform_driver ep93xx_adc_driver = {
245 .name = "ep93xx-adc",
247 .probe = ep93xx_adc_probe,
248 .remove = ep93xx_adc_remove,
250 module_platform_driver(ep93xx_adc_driver);
252 MODULE_AUTHOR("Alexander Sverdlin <alexander.sverdlin@gmail.com>");
253 MODULE_DESCRIPTION("Cirrus Logic EP93XX ADC driver");
254 MODULE_LICENSE("GPL");
255 MODULE_ALIAS("platform:ep93xx-adc");