drivers/iio/adc/dln2-adc.c

   1 /*
   2  * Driver for the Diolan DLN-2 USB-ADC adapter
   3  *
   4  * Copyright (c) 2017 Jack Andersen
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License as
   8  * published by the Free Software Foundation, version 2.
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/module.h>
  13 #include <linux/types.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/mfd/dln2.h>
  16
  17 #include <linux/iio/iio.h>
  18 #include <linux/iio/sysfs.h>
  19 #include <linux/iio/trigger.h>
  20 #include <linux/iio/trigger_consumer.h>
  21 #include <linux/iio/triggered_buffer.h>
  22 #include <linux/iio/buffer.h>
  23 #include <linux/iio/kfifo_buf.h>
  24
  25 #define DLN2_ADC_MOD_NAME "dln2-adc"
  26
  27 #define DLN2_ADC_ID             0x06
  28
  29 #define DLN2_ADC_GET_CHANNEL_COUNT      DLN2_CMD(0x01, DLN2_ADC_ID)
  30 #define DLN2_ADC_ENABLE                 DLN2_CMD(0x02, DLN2_ADC_ID)
  31 #define DLN2_ADC_DISABLE                DLN2_CMD(0x03, DLN2_ADC_ID)
  32 #define DLN2_ADC_CHANNEL_ENABLE         DLN2_CMD(0x05, DLN2_ADC_ID)
  33 #define DLN2_ADC_CHANNEL_DISABLE        DLN2_CMD(0x06, DLN2_ADC_ID)
  34 #define DLN2_ADC_SET_RESOLUTION         DLN2_CMD(0x08, DLN2_ADC_ID)
  35 #define DLN2_ADC_CHANNEL_GET_VAL        DLN2_CMD(0x0A, DLN2_ADC_ID)
  36 #define DLN2_ADC_CHANNEL_GET_ALL_VAL    DLN2_CMD(0x0B, DLN2_ADC_ID)
  37 #define DLN2_ADC_CHANNEL_SET_CFG        DLN2_CMD(0x0C, DLN2_ADC_ID)
  38 #define DLN2_ADC_CHANNEL_GET_CFG        DLN2_CMD(0x0D, DLN2_ADC_ID)
  39 #define DLN2_ADC_CONDITION_MET_EV       DLN2_CMD(0x10, DLN2_ADC_ID)
  40
  41 #define DLN2_ADC_EVENT_NONE             0
  42 #define DLN2_ADC_EVENT_BELOW            1
  43 #define DLN2_ADC_EVENT_LEVEL_ABOVE      2
  44 #define DLN2_ADC_EVENT_OUTSIDE          3
  45 #define DLN2_ADC_EVENT_INSIDE           4
  46 #define DLN2_ADC_EVENT_ALWAYS           5
  47
  48 #define DLN2_ADC_MAX_CHANNELS 8
  49 #define DLN2_ADC_DATA_BITS 10
  50
  51 /*
  52  * Plays similar role to iio_demux_table in subsystem core; except allocated
  53  * in a fixed 8-element array.
  54  */
  55 struct dln2_adc_demux_table {
  56         unsigned int from;
  57         unsigned int to;
  58         unsigned int length;
  59 };
  60
  61 struct dln2_adc {
  62         struct platform_device *pdev;
  63         struct iio_chan_spec iio_channels[DLN2_ADC_MAX_CHANNELS + 1];
  64         int port, trigger_chan;
  65         struct iio_trigger *trig;
  66         struct mutex mutex;
  67         /* Cached sample period in milliseconds */
  68         unsigned int sample_period;
  69         /* Demux table */
  70         unsigned int demux_count;
  71         struct dln2_adc_demux_table demux[DLN2_ADC_MAX_CHANNELS];
  72         /* Precomputed timestamp padding offset and length */
  73         unsigned int ts_pad_offset, ts_pad_length;
  74 };
  75
  76 struct dln2_adc_port_chan {
  77         u8 port;
  78         u8 chan;
  79 };
  80
  81 struct dln2_adc_get_all_vals {
  82         __le16 channel_mask;
  83         __le16 values[DLN2_ADC_MAX_CHANNELS];
  84 };
  85
  86 static void dln2_adc_add_demux(struct dln2_adc *dln2,
  87         unsigned int in_loc, unsigned int out_loc,
  88         unsigned int length)
  89 {
  90         struct dln2_adc_demux_table *p = dln2->demux_count ?
  91                 &dln2->demux[dln2->demux_count - 1] : NULL;
  92
  93         if (p && p->from + p->length == in_loc &&
  94                 p->to + p->length == out_loc) {
  95                 p->length += length;
  96         } else if (dln2->demux_count < DLN2_ADC_MAX_CHANNELS) {
  97                 p = &dln2->demux[dln2->demux_count++];
  98                 p->from = in_loc;
  99                 p->to = out_loc;
 100                 p->length = length;
 101         }
 102 }
 103
 104 static void dln2_adc_update_demux(struct dln2_adc *dln2)
 105 {
 106         int in_ind = -1, out_ind;
 107         unsigned int in_loc = 0, out_loc = 0;
 108         struct iio_dev *indio_dev = platform_get_drvdata(dln2->pdev);
 109
 110         /* Clear out any old demux */
 111         dln2->demux_count = 0;
 112
 113         /* Optimize all 8-channels case */
 114         if (indio_dev->masklength &&
 115             (*indio_dev->active_scan_mask & 0xff) == 0xff) {
 116                 dln2_adc_add_demux(dln2, 0, 0, 16);
 117                 dln2->ts_pad_offset = 0;
 118                 dln2->ts_pad_length = 0;
 119                 return;
 120         }
 121
 122         /* Build demux table from fixed 8-channels to active_scan_mask */
 123         for_each_set_bit(out_ind,
 124                          indio_dev->active_scan_mask,
 125                          indio_dev->masklength) {
 126                 /* Handle timestamp separately */
 127                 if (out_ind == DLN2_ADC_MAX_CHANNELS)
 128                         break;
 129                 for (++in_ind; in_ind != out_ind; ++in_ind)
 130                         in_loc += 2;
 131                 dln2_adc_add_demux(dln2, in_loc, out_loc, 2);
 132                 out_loc += 2;
 133                 in_loc += 2;
 134         }
 135
 136         if (indio_dev->scan_timestamp) {
 137                 size_t ts_offset = indio_dev->scan_bytes / sizeof(int64_t) - 1;
 138
 139                 dln2->ts_pad_offset = out_loc;
 140                 dln2->ts_pad_length = ts_offset * sizeof(int64_t) - out_loc;
 141         } else {
 142                 dln2->ts_pad_offset = 0;
 143                 dln2->ts_pad_length = 0;
 144         }
 145 }
 146
 147 static int dln2_adc_get_chan_count(struct dln2_adc *dln2)
 148 {
 149         int ret;
 150         u8 port = dln2->port;
 151         u8 count;
 152         int olen = sizeof(count);
 153
 154         ret = dln2_transfer(dln2->pdev, DLN2_ADC_GET_CHANNEL_COUNT,
 155                             &port, sizeof(port), &count, &olen);
 156         if (ret < 0) {
 157                 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 158                 return ret;
 159         }
 160         if (olen < sizeof(count))
 161                 return -EPROTO;
 162
 163         return count;
 164 }
 165
 166 static int dln2_adc_set_port_resolution(struct dln2_adc *dln2)
 167 {
 168         int ret;
 169         struct dln2_adc_port_chan port_chan = {
 170                 .port = dln2->port,
 171                 .chan = DLN2_ADC_DATA_BITS,
 172         };
 173
 174         ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_SET_RESOLUTION,
 175                                &port_chan, sizeof(port_chan));
 176         if (ret < 0)
 177                 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 178
 179         return ret;
 180 }
 181
 182 static int dln2_adc_set_chan_enabled(struct dln2_adc *dln2,
 183                                      int channel, bool enable)
 184 {
 185         int ret;
 186         struct dln2_adc_port_chan port_chan = {
 187                 .port = dln2->port,
 188                 .chan = channel,
 189         };
 190         u16 cmd = enable ? DLN2_ADC_CHANNEL_ENABLE : DLN2_ADC_CHANNEL_DISABLE;
 191
 192         ret = dln2_transfer_tx(dln2->pdev, cmd, &port_chan, sizeof(port_chan));
 193         if (ret < 0)
 194                 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 195
 196         return ret;
 197 }
 198
 199 static int dln2_adc_set_port_enabled(struct dln2_adc *dln2, bool enable,
 200                                      u16 *conflict_out)
 201 {
 202         int ret;
 203         u8 port = dln2->port;
 204         __le16 conflict;
 205         int olen = sizeof(conflict);
 206         u16 cmd = enable ? DLN2_ADC_ENABLE : DLN2_ADC_DISABLE;
 207
 208         if (conflict_out)
 209                 *conflict_out = 0;
 210
 211         ret = dln2_transfer(dln2->pdev, cmd, &port, sizeof(port),
 212                             &conflict, &olen);
 213         if (ret < 0) {
 214                 dev_dbg(&dln2->pdev->dev, "Problem in %s(%d)\n",
 215                         __func__, (int)enable);
 216                 if (conflict_out && enable && olen >= sizeof(conflict))
 217                         *conflict_out = le16_to_cpu(conflict);
 218                 return ret;
 219         }
 220         if (enable && olen < sizeof(conflict))
 221                 return -EPROTO;
 222
 223         return ret;
 224 }
 225
 226 static int dln2_adc_set_chan_period(struct dln2_adc *dln2,
 227         unsigned int channel, unsigned int period)
 228 {
 229         int ret;
 230         struct {
 231                 struct dln2_adc_port_chan port_chan;
 232                 __u8 type;
 233                 __le16 period;
 234                 __le16 low;
 235                 __le16 high;
 236         } __packed set_cfg = {
 237                 .port_chan.port = dln2->port,
 238                 .port_chan.chan = channel,
 239                 .type = period ? DLN2_ADC_EVENT_ALWAYS : DLN2_ADC_EVENT_NONE,
 240                 .period = cpu_to_le16(period)
 241         };
 242
 243         ret = dln2_transfer_tx(dln2->pdev, DLN2_ADC_CHANNEL_SET_CFG,
 244                                &set_cfg, sizeof(set_cfg));
 245         if (ret < 0)
 246                 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 247
 248         return ret;
 249 }
 250
 251 static int dln2_adc_read(struct dln2_adc *dln2, unsigned int channel)
 252 {
 253         int ret, i;
 254         u16 conflict;
 255         __le16 value;
 256         int olen = sizeof(value);
 257         struct dln2_adc_port_chan port_chan = {
 258                 .port = dln2->port,
 259                 .chan = channel,
 260         };
 261
 262         ret = dln2_adc_set_chan_enabled(dln2, channel, true);
 263         if (ret < 0)
 264                 return ret;
 265
 266         ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
 267         if (ret < 0) {
 268                 if (conflict) {
 269                         dev_err(&dln2->pdev->dev,
 270                                 "ADC pins conflict with mask %04X\n",
 271                                 (int)conflict);
 272                         ret = -EBUSY;
 273                 }
 274                 goto disable_chan;
 275         }
 276
 277         /*
 278          * Call GET_VAL twice due to initial zero-return immediately after
 279          * enabling channel.
 280          */
 281         for (i = 0; i < 2; ++i) {
 282                 ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_VAL,
 283                                     &port_chan, sizeof(port_chan),
 284                                     &value, &olen);
 285                 if (ret < 0) {
 286                         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 287                         goto disable_port;
 288                 }
 289                 if (olen < sizeof(value)) {
 290                         ret = -EPROTO;
 291                         goto disable_port;
 292                 }
 293         }
 294
 295         ret = le16_to_cpu(value);
 296
 297 disable_port:
 298         dln2_adc_set_port_enabled(dln2, false, NULL);
 299 disable_chan:
 300         dln2_adc_set_chan_enabled(dln2, channel, false);
 301
 302         return ret;
 303 }
 304
 305 static int dln2_adc_read_all(struct dln2_adc *dln2,
 306                              struct dln2_adc_get_all_vals *get_all_vals)
 307 {
 308         int ret;
 309         __u8 port = dln2->port;
 310         int olen = sizeof(*get_all_vals);
 311
 312         ret = dln2_transfer(dln2->pdev, DLN2_ADC_CHANNEL_GET_ALL_VAL,
 313                             &port, sizeof(port), get_all_vals, &olen);
 314         if (ret < 0) {
 315                 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 316                 return ret;
 317         }
 318         if (olen < sizeof(*get_all_vals))
 319                 return -EPROTO;
 320
 321         return ret;
 322 }
 323
 324 static int dln2_adc_read_raw(struct iio_dev *indio_dev,
 325                              struct iio_chan_spec const *chan,
 326                              int *val,
 327                              int *val2,
 328                              long mask)
 329 {
 330         int ret;
 331         unsigned int microhertz;
 332         struct dln2_adc *dln2 = iio_priv(indio_dev);
 333
 334         switch (mask) {
 335         case IIO_CHAN_INFO_RAW:
 336                 ret = iio_device_claim_direct_mode(indio_dev);
 337                 if (ret < 0)
 338                         return ret;
 339
 340                 mutex_lock(&dln2->mutex);
 341                 ret = dln2_adc_read(dln2, chan->channel);
 342                 mutex_unlock(&dln2->mutex);
 343
 344                 iio_device_release_direct_mode(indio_dev);
 345
 346                 if (ret < 0)
 347                         return ret;
 348
 349                 *val = ret;
 350                 return IIO_VAL_INT;
 351
 352         case IIO_CHAN_INFO_SCALE:
 353                 /*
 354                  * Voltage reference is fixed at 3.3v
 355                  *  3.3 / (1 << 10) * 1000000000
 356                  */
 357                 *val = 0;
 358                 *val2 = 3222656;
 359                 return IIO_VAL_INT_PLUS_NANO;
 360
 361         case IIO_CHAN_INFO_SAMP_FREQ:
 362                 if (dln2->sample_period) {
 363                         microhertz = 1000000000 / dln2->sample_period;
 364                         *val = microhertz / 1000000;
 365                         *val2 = microhertz % 1000000;
 366                 } else {
 367                         *val = 0;
 368                         *val2 = 0;
 369                 }
 370
 371                 return IIO_VAL_INT_PLUS_MICRO;
 372
 373         default:
 374                 return -EINVAL;
 375         }
 376 }
 377
 378 static int dln2_adc_write_raw(struct iio_dev *indio_dev,
 379                               struct iio_chan_spec const *chan,
 380                               int val,
 381                               int val2,
 382                               long mask)
 383 {
 384         int ret;
 385         unsigned int microhertz;
 386         struct dln2_adc *dln2 = iio_priv(indio_dev);
 387
 388         switch (mask) {
 389         case IIO_CHAN_INFO_SAMP_FREQ:
 390                 microhertz = 1000000 * val + val2;
 391
 392                 mutex_lock(&dln2->mutex);
 393
 394                 dln2->sample_period =
 395                         microhertz ? 1000000000 / microhertz : UINT_MAX;
 396                 if (dln2->sample_period > 65535) {
 397                         dln2->sample_period = 65535;
 398                         dev_warn(&dln2->pdev->dev,
 399                                  "clamping period to 65535ms\n");
 400                 }
 401
 402                 /*
 403                  * The first requested channel is arbitrated as a shared
 404                  * trigger source, so only one event is registered with the
 405                  * DLN. The event handler will then read all enabled channel
 406                  * values using DLN2_ADC_CHANNEL_GET_ALL_VAL to maintain
 407                  * synchronization between ADC readings.
 408                  */
 409                 if (dln2->trigger_chan != -1)
 410                         ret = dln2_adc_set_chan_period(dln2,
 411                                 dln2->trigger_chan, dln2->sample_period);
 412                 else
 413                         ret = 0;
 414
 415                 mutex_unlock(&dln2->mutex);
 416
 417                 return ret;
 418
 419         default:
 420                 return -EINVAL;
 421         }
 422 }
 423
 424 static int dln2_update_scan_mode(struct iio_dev *indio_dev,
 425                                  const unsigned long *scan_mask)
 426 {
 427         struct dln2_adc *dln2 = iio_priv(indio_dev);
 428         int chan_count = indio_dev->num_channels - 1;
 429         int ret, i, j;
 430
 431         mutex_lock(&dln2->mutex);
 432
 433         for (i = 0; i < chan_count; ++i) {
 434                 ret = dln2_adc_set_chan_enabled(dln2, i,
 435                                                 test_bit(i, scan_mask));
 436                 if (ret < 0) {
 437                         for (j = 0; j < i; ++j)
 438                                 dln2_adc_set_chan_enabled(dln2, j, false);
 439                         mutex_unlock(&dln2->mutex);
 440                         dev_err(&dln2->pdev->dev,
 441                                 "Unable to enable ADC channel %d\n", i);
 442                         return -EBUSY;
 443                 }
 444         }
 445
 446         dln2_adc_update_demux(dln2);
 447
 448         mutex_unlock(&dln2->mutex);
 449
 450         return 0;
 451 }
 452
 453 #define DLN2_ADC_CHAN(lval, idx) {                                      \
 454         lval.type = IIO_VOLTAGE;                                        \
 455         lval.channel = idx;                                             \
 456         lval.indexed = 1;                                               \
 457         lval.info_mask_separate = BIT(IIO_CHAN_INFO_RAW);               \
 458         lval.info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) |       \
 459                                        BIT(IIO_CHAN_INFO_SAMP_FREQ);    \
 460         lval.scan_index = idx;                                          \
 461         lval.scan_type.sign = 'u';                                      \
 462         lval.scan_type.realbits = DLN2_ADC_DATA_BITS;                   \
 463         lval.scan_type.storagebits = 16;                                \
 464         lval.scan_type.endianness = IIO_LE;                             \
 465 }
 466
 467 /* Assignment version of IIO_CHAN_SOFT_TIMESTAMP */
 468 #define IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(lval, _si) {     \
 469         lval.type = IIO_TIMESTAMP;                      \
 470         lval.channel = -1;                              \
 471         lval.scan_index = _si;                          \
 472         lval.scan_type.sign = 's';                      \
 473         lval.scan_type.realbits = 64;                   \
 474         lval.scan_type.storagebits = 64;                \
 475 }
 476
 477 static const struct iio_info dln2_adc_info = {
 478         .read_raw = dln2_adc_read_raw,
 479         .write_raw = dln2_adc_write_raw,
 480         .update_scan_mode = dln2_update_scan_mode,
 481         .driver_module = THIS_MODULE,
 482 };
 483
 484 static irqreturn_t dln2_adc_trigger_h(int irq, void *p)
 485 {
 486         struct iio_poll_func *pf = p;
 487         struct iio_dev *indio_dev = pf->indio_dev;
 488         struct {
 489                 __le16 values[DLN2_ADC_MAX_CHANNELS];
 490                 int64_t timestamp_space;
 491         } data;
 492         struct dln2_adc_get_all_vals dev_data;
 493         struct dln2_adc *dln2 = iio_priv(indio_dev);
 494         const struct dln2_adc_demux_table *t;
 495         int ret, i;
 496
 497         mutex_lock(&dln2->mutex);
 498         ret = dln2_adc_read_all(dln2, &dev_data);
 499         mutex_unlock(&dln2->mutex);
 500         if (ret < 0)
 501                 goto done;
 502
 503         /* Demux operation */
 504         for (i = 0; i < dln2->demux_count; ++i) {
 505                 t = &dln2->demux[i];
 506                 memcpy((void *)data.values + t->to,
 507                        (void *)dev_data.values + t->from, t->length);
 508         }
 509
 510         /* Zero padding space between values and timestamp */
 511         if (dln2->ts_pad_length)
 512                 memset((void *)data.values + dln2->ts_pad_offset,
 513                        0, dln2->ts_pad_length);
 514
 515         iio_push_to_buffers_with_timestamp(indio_dev, &data,
 516                                            iio_get_time_ns(indio_dev));
 517
 518 done:
 519         iio_trigger_notify_done(indio_dev->trig);
 520         return IRQ_HANDLED;
 521 }
 522
 523 static int dln2_adc_triggered_buffer_postenable(struct iio_dev *indio_dev)
 524 {
 525         int ret;
 526         struct dln2_adc *dln2 = iio_priv(indio_dev);
 527         u16 conflict;
 528         unsigned int trigger_chan;
 529
 530         ret = iio_triggered_buffer_postenable(indio_dev);
 531         if (ret)
 532                 return ret;
 533
 534         mutex_lock(&dln2->mutex);
 535
 536         /* Enable ADC */
 537         ret = dln2_adc_set_port_enabled(dln2, true, &conflict);
 538         if (ret < 0) {
 539                 mutex_unlock(&dln2->mutex);
 540                 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 541                 if (conflict) {
 542                         dev_err(&dln2->pdev->dev,
 543                                 "ADC pins conflict with mask %04X\n",
 544                                 (int)conflict);
 545                         ret = -EBUSY;
 546                 }
 547                 iio_triggered_buffer_predisable(indio_dev);
 548                 return ret;
 549         }
 550
 551         /* Assign trigger channel based on first enabled channel */
 552         trigger_chan = find_first_bit(indio_dev->active_scan_mask,
 553                                       indio_dev->masklength);
 554         if (trigger_chan < DLN2_ADC_MAX_CHANNELS) {
 555                 dln2->trigger_chan = trigger_chan;
 556                 ret = dln2_adc_set_chan_period(dln2, dln2->trigger_chan,
 557                                                dln2->sample_period);
 558                 mutex_unlock(&dln2->mutex);
 559                 if (ret < 0) {
 560                         dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 561                         iio_triggered_buffer_predisable(indio_dev);
 562                         return ret;
 563                 }
 564         } else {
 565                 dln2->trigger_chan = -1;
 566                 mutex_unlock(&dln2->mutex);
 567         }
 568
 569         return 0;
 570 }
 571
 572 static int dln2_adc_triggered_buffer_predisable(struct iio_dev *indio_dev)
 573 {
 574         int ret, ret2;
 575         struct dln2_adc *dln2 = iio_priv(indio_dev);
 576
 577         mutex_lock(&dln2->mutex);
 578
 579         /* Disable trigger channel */
 580         if (dln2->trigger_chan != -1) {
 581                 dln2_adc_set_chan_period(dln2, dln2->trigger_chan, 0);
 582                 dln2->trigger_chan = -1;
 583         }
 584
 585         /* Disable ADC */
 586         ret = dln2_adc_set_port_enabled(dln2, false, NULL);
 587
 588         mutex_unlock(&dln2->mutex);
 589         if (ret < 0)
 590                 dev_dbg(&dln2->pdev->dev, "Problem in %s\n", __func__);
 591
 592         ret2 = iio_triggered_buffer_predisable(indio_dev);
 593         if (ret == 0)
 594                 ret = ret2;
 595
 596         return ret;
 597 }
 598
 599 static const struct iio_buffer_setup_ops dln2_adc_buffer_setup_ops = {
 600         .postenable = dln2_adc_triggered_buffer_postenable,
 601         .predisable = dln2_adc_triggered_buffer_predisable,
 602 };
 603
 604 static void dln2_adc_event(struct platform_device *pdev, u16 echo,
 605                            const void *data, int len)
 606 {
 607         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 608         struct dln2_adc *dln2 = iio_priv(indio_dev);
 609
 610         /* Called via URB completion handler */
 611         iio_trigger_poll(dln2->trig);
 612 }
 613
 614 static const struct iio_trigger_ops dln2_adc_trigger_ops = {
 615         .owner = THIS_MODULE,
 616 };
 617
 618 static int dln2_adc_probe(struct platform_device *pdev)
 619 {
 620         struct device *dev = &pdev->dev;
 621         struct dln2_adc *dln2;
 622         struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
 623         struct iio_dev *indio_dev;
 624         int i, ret, chans;
 625
 626         indio_dev = devm_iio_device_alloc(dev, sizeof(*dln2));
 627         if (!indio_dev) {
 628                 dev_err(dev, "failed allocating iio device\n");
 629                 return -ENOMEM;
 630         }
 631
 632         dln2 = iio_priv(indio_dev);
 633         dln2->pdev = pdev;
 634         dln2->port = pdata->port;
 635         dln2->trigger_chan = -1;
 636         mutex_init(&dln2->mutex);
 637
 638         platform_set_drvdata(pdev, indio_dev);
 639
 640         ret = dln2_adc_set_port_resolution(dln2);
 641         if (ret < 0) {
 642                 dev_err(dev, "failed to set ADC resolution to 10 bits\n");
 643                 return ret;
 644         }
 645
 646         chans = dln2_adc_get_chan_count(dln2);
 647         if (chans < 0) {
 648                 dev_err(dev, "failed to get channel count: %d\n", chans);
 649                 return chans;
 650         }
 651         if (chans > DLN2_ADC_MAX_CHANNELS) {
 652                 chans = DLN2_ADC_MAX_CHANNELS;
 653                 dev_warn(dev, "clamping channels to %d\n",
 654                          DLN2_ADC_MAX_CHANNELS);
 655         }
 656
 657         for (i = 0; i < chans; ++i)
 658                 DLN2_ADC_CHAN(dln2->iio_channels[i], i)
 659         IIO_CHAN_SOFT_TIMESTAMP_ASSIGN(dln2->iio_channels[i], i);
 660
 661         indio_dev->name = DLN2_ADC_MOD_NAME;
 662         indio_dev->dev.parent = dev;
 663         indio_dev->info = &dln2_adc_info;
 664         indio_dev->modes = INDIO_DIRECT_MODE;
 665         indio_dev->channels = dln2->iio_channels;
 666         indio_dev->num_channels = chans + 1;
 667         indio_dev->setup_ops = &dln2_adc_buffer_setup_ops;
 668
 669         dln2->trig = devm_iio_trigger_alloc(dev, "%s-dev%d",
 670                                             indio_dev->name, indio_dev->id);
 671         if (!dln2->trig) {
 672                 dev_err(dev, "failed to allocate trigger\n");
 673                 return -ENOMEM;
 674         }
 675         dln2->trig->ops = &dln2_adc_trigger_ops;
 676         iio_trigger_set_drvdata(dln2->trig, dln2);
 677         ret = devm_iio_trigger_register(dev, dln2->trig);
 678         if (ret) {
 679                 dev_err(dev, "failed to register trigger: %d\n", ret);
 680                 return ret;
 681         }
 682         iio_trigger_set_immutable(indio_dev, dln2->trig);
 683
 684         ret = devm_iio_triggered_buffer_setup(dev, indio_dev, NULL,
 685                                               dln2_adc_trigger_h,
 686                                               &dln2_adc_buffer_setup_ops);
 687         if (ret) {
 688                 dev_err(dev, "failed to allocate triggered buffer: %d\n", ret);
 689                 return ret;
 690         }
 691
 692         ret = dln2_register_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV,
 693                                      dln2_adc_event);
 694         if (ret) {
 695                 dev_err(dev, "failed to setup DLN2 periodic event: %d\n", ret);
 696                 return ret;
 697         }
 698
 699         ret = iio_device_register(indio_dev);
 700         if (ret) {
 701                 dev_err(dev, "failed to register iio device: %d\n", ret);
 702                 goto unregister_event;
 703         }
 704
 705         return ret;
 706
 707 unregister_event:
 708         dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
 709
 710         return ret;
 711 }
 712
 713 static int dln2_adc_remove(struct platform_device *pdev)
 714 {
 715         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 716
 717         iio_device_unregister(indio_dev);
 718         dln2_unregister_event_cb(pdev, DLN2_ADC_CONDITION_MET_EV);
 719         return 0;
 720 }
 721
 722 static struct platform_driver dln2_adc_driver = {
 723         .driver.name    = DLN2_ADC_MOD_NAME,
 724         .probe          = dln2_adc_probe,
 725         .remove         = dln2_adc_remove,
 726 };
 727
 728 module_platform_driver(dln2_adc_driver);
 729
 730 MODULE_AUTHOR("Jack Andersen <jackoalan@gmail.com");
 731 MODULE_DESCRIPTION("Driver for the Diolan DLN2 ADC interface");
 732 MODULE_LICENSE("GPL v2");
 733 MODULE_ALIAS("platform:dln2-adc");