2 * Driver for the ADC present in the Atmel AT91 evaluation boards.
4 * Copyright 2011 Free Electrons
6 * Licensed under the GPLv2 or later.
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
26 #include <linux/platform_data/at91_adc.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
35 #define AT91_ADC_CR 0x00 /* Control Register */
36 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
37 #define AT91_ADC_START (1 << 1) /* Start Conversion */
39 #define AT91_ADC_MR 0x04 /* Mode Register */
40 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
41 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
42 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
43 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
44 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
45 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
46 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
47 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
48 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
49 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
50 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
51 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
52 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
53 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
54 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
55 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
56 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
57 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
58 #define AT91_ADC_STARTUP_(x) ((x) << 16)
59 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
60 #define AT91_ADC_SHTIM_(x) ((x) << 24)
61 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
62 #define AT91_ADC_PENDBC_(x) ((x) << 28)
64 #define AT91_ADC_TSR 0x0C
65 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
66 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
68 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
69 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
70 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
71 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
73 #define AT91_ADC_SR 0x1C /* Status Register */
74 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
75 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
76 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
77 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
78 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
79 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
81 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
82 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
84 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
85 #define AT91_ADC_LDATA (0x3ff)
87 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
88 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
89 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
90 #define AT91RL_ADC_IER_PEN (1 << 20)
91 #define AT91RL_ADC_IER_NOPEN (1 << 21)
92 #define AT91_ADC_IER_PEN (1 << 29)
93 #define AT91_ADC_IER_NOPEN (1 << 30)
94 #define AT91_ADC_IER_XRDY (1 << 20)
95 #define AT91_ADC_IER_YRDY (1 << 21)
96 #define AT91_ADC_IER_PRDY (1 << 22)
97 #define AT91_ADC_ISR_PENS (1 << 31)
99 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
100 #define AT91_ADC_DATA (0x3ff)
102 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
104 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
105 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
107 #define AT91_ADC_TSMR 0xB0
108 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
109 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
110 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
111 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
112 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
113 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
114 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
115 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
116 #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
117 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
118 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
119 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
120 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
121 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
123 #define AT91_ADC_TSXPOSR 0xB4
124 #define AT91_ADC_TSYPOSR 0xB8
125 #define AT91_ADC_TSPRESSR 0xBC
127 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
128 #define AT91_ADC_TRGR_9G45 0x08
129 #define AT91_ADC_TRGR_9X5 0xC0
131 /* Trigger Register bit field */
132 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
133 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
134 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
135 #define AT91_ADC_TRGR_NONE (0 << 0)
136 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
138 #define AT91_ADC_CHAN(st, ch) \
139 (st->registers->channel_base + (ch * 4))
140 #define at91_adc_readl(st, reg) \
141 (readl_relaxed(st->reg_base + reg))
142 #define at91_adc_writel(st, reg, val) \
143 (writel_relaxed(val, st->reg_base + reg))
145 #define DRIVER_NAME "at91_adc"
146 #define MAX_POS_BITS 12
148 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
149 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
151 #define MAX_RLPOS_BITS 10
152 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
153 #define TOUCH_SHTIM 0xa
154 #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */
157 * struct at91_adc_reg_desc - Various informations relative to registers
158 * @channel_base: Base offset for the channel data registers
159 * @drdy_mask: Mask of the DRDY field in the relevant registers
160 (Interruptions registers mostly)
161 * @status_register: Offset of the Interrupt Status Register
162 * @trigger_register: Offset of the Trigger setup register
163 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
164 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
166 struct at91_adc_reg_desc {
175 struct at91_adc_caps {
176 bool has_ts; /* Support touch screen */
177 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
179 * Numbers of sampling data will be averaged. Can be 0~3.
180 * Hardware can average (2 ^ ts_filter_average) sample data.
182 u8 ts_filter_average;
183 /* Pen Detection input pull-up resistor, can be 0~3 */
184 u8 ts_pen_detect_sensitivity;
186 /* startup time calculate function */
187 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
190 struct at91_adc_reg_desc registers;
193 struct at91_adc_state {
196 unsigned long channels_mask;
204 void __iomem *reg_base;
205 struct at91_adc_reg_desc *registers;
209 struct iio_trigger **trig;
210 struct at91_adc_trigger *trigger_list;
214 u32 res; /* resolution used for convertions */
215 bool low_res; /* the resolution corresponds to the lowest one */
216 wait_queue_head_t wq_data_avail;
217 struct at91_adc_caps *caps;
220 * Following ADC channels are shared by touchscreen:
222 * CH0 -- Touch screen XP/UL
223 * CH1 -- Touch screen XM/UR
224 * CH2 -- Touch screen YP/LL
225 * CH3 -- Touch screen YM/Sense
226 * CH4 -- Touch screen LR(5-wire only)
228 * The bitfields below represents the reserved channel in the
231 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
232 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
233 enum atmel_adc_ts_type touchscreen_type;
234 struct input_dev *ts_input;
236 u16 ts_sample_period_val;
237 u32 ts_pressure_threshold;
240 bool ts_bufferedmeasure;
245 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
247 struct iio_poll_func *pf = p;
248 struct iio_dev *idev = pf->indio_dev;
249 struct at91_adc_state *st = iio_priv(idev);
250 struct iio_chan_spec const *chan;
253 for (i = 0; i < idev->masklength; i++) {
254 if (!test_bit(i, idev->active_scan_mask))
256 chan = idev->channels + i;
257 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
261 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
263 iio_trigger_notify_done(idev->trig);
265 /* Needed to ACK the DRDY interruption */
266 at91_adc_readl(st, AT91_ADC_LCDR);
273 /* Handler for classic adc channel eoc trigger */
274 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
276 struct at91_adc_state *st = iio_priv(idev);
278 if (iio_buffer_enabled(idev)) {
279 disable_irq_nosync(irq);
280 iio_trigger_poll(idev->trig);
282 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
283 /* Needed to ACK the DRDY interruption */
284 at91_adc_readl(st, AT91_ADC_LCDR);
286 wake_up_interruptible(&st->wq_data_avail);
290 static int at91_ts_sample(struct at91_adc_state *st)
292 unsigned int xscale, yscale, reg, z1, z2;
293 unsigned int x, y, pres, xpos, ypos;
294 unsigned int rxp = 1;
295 unsigned int factor = 1000;
296 struct iio_dev *idev = iio_priv_to_dev(st);
298 unsigned int xyz_mask_bits = st->res;
299 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
301 /* calculate position */
302 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
303 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
304 xpos = reg & xyz_mask;
305 x = (xpos << MAX_POS_BITS) - xpos;
306 xscale = (reg >> 16) & xyz_mask;
308 dev_err(&idev->dev, "Error: xscale == 0!\n");
313 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
314 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
315 ypos = reg & xyz_mask;
316 y = (ypos << MAX_POS_BITS) - ypos;
317 yscale = (reg >> 16) & xyz_mask;
319 dev_err(&idev->dev, "Error: yscale == 0!\n");
324 /* calculate the pressure */
325 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
327 z2 = (reg >> 16) & xyz_mask;
330 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
333 pres = st->ts_pressure_threshold; /* no pen contacted */
335 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
336 xpos, xscale, ypos, yscale, z1, z2, pres);
338 if (pres < st->ts_pressure_threshold) {
339 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
340 x, y, pres / factor);
341 input_report_abs(st->ts_input, ABS_X, x);
342 input_report_abs(st->ts_input, ABS_Y, y);
343 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
344 input_report_key(st->ts_input, BTN_TOUCH, 1);
345 input_sync(st->ts_input);
347 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
353 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
355 struct iio_dev *idev = private;
356 struct at91_adc_state *st = iio_priv(idev);
357 u32 status = at91_adc_readl(st, st->registers->status_register);
360 status &= at91_adc_readl(st, AT91_ADC_IMR);
361 if (status & GENMASK(st->num_channels - 1, 0))
362 handle_adc_eoc_trigger(irq, idev);
364 if (status & AT91RL_ADC_IER_PEN) {
365 /* Disabling pen debounce is required to get a NOPEN irq */
366 reg = at91_adc_readl(st, AT91_ADC_MR);
367 reg &= ~AT91_ADC_PENDBC;
368 at91_adc_writel(st, AT91_ADC_MR, reg);
370 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
371 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
373 /* Set up period trigger for sampling */
374 at91_adc_writel(st, st->registers->trigger_register,
375 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
376 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
377 } else if (status & AT91RL_ADC_IER_NOPEN) {
378 reg = at91_adc_readl(st, AT91_ADC_MR);
379 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
380 at91_adc_writel(st, AT91_ADC_MR, reg);
381 at91_adc_writel(st, st->registers->trigger_register,
384 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
386 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
387 st->ts_bufferedmeasure = false;
388 input_report_key(st->ts_input, BTN_TOUCH, 0);
389 input_sync(st->ts_input);
390 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
391 /* Conversion finished and we've a touchscreen */
392 if (st->ts_bufferedmeasure) {
394 * Last measurement is always discarded, since it can
396 * Always report previous measurement
398 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
399 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
400 input_report_key(st->ts_input, BTN_TOUCH, 1);
401 input_sync(st->ts_input);
403 st->ts_bufferedmeasure = true;
405 /* Now make new measurement */
406 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
408 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
410 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
412 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
418 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
420 struct iio_dev *idev = private;
421 struct at91_adc_state *st = iio_priv(idev);
422 u32 status = at91_adc_readl(st, st->registers->status_register);
423 const uint32_t ts_data_irq_mask =
428 if (status & GENMASK(st->num_channels - 1, 0))
429 handle_adc_eoc_trigger(irq, idev);
431 if (status & AT91_ADC_IER_PEN) {
432 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
433 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
435 /* Set up period trigger for sampling */
436 at91_adc_writel(st, st->registers->trigger_register,
437 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
438 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
439 } else if (status & AT91_ADC_IER_NOPEN) {
440 at91_adc_writel(st, st->registers->trigger_register, 0);
441 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
443 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
445 input_report_key(st->ts_input, BTN_TOUCH, 0);
446 input_sync(st->ts_input);
447 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
448 /* Now all touchscreen data is ready */
450 if (status & AT91_ADC_ISR_PENS) {
451 /* validate data by pen contact */
454 /* triggered by event that is no pen contact, just read
455 * them to clean the interrupt and discard all.
457 at91_adc_readl(st, AT91_ADC_TSXPOSR);
458 at91_adc_readl(st, AT91_ADC_TSYPOSR);
459 at91_adc_readl(st, AT91_ADC_TSPRESSR);
466 static int at91_adc_channel_init(struct iio_dev *idev)
468 struct at91_adc_state *st = iio_priv(idev);
469 struct iio_chan_spec *chan_array, *timestamp;
471 unsigned long rsvd_mask = 0;
473 /* If touchscreen is enable, then reserve the adc channels */
474 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
475 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
476 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
477 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
479 /* set up the channel mask to reserve touchscreen channels */
480 st->channels_mask &= ~rsvd_mask;
482 idev->num_channels = bitmap_weight(&st->channels_mask,
483 st->num_channels) + 1;
485 chan_array = devm_kzalloc(&idev->dev,
486 ((idev->num_channels + 1) *
487 sizeof(struct iio_chan_spec)),
493 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
494 struct iio_chan_spec *chan = chan_array + idx;
496 chan->type = IIO_VOLTAGE;
499 chan->scan_index = idx;
500 chan->scan_type.sign = 'u';
501 chan->scan_type.realbits = st->res;
502 chan->scan_type.storagebits = 16;
503 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
504 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
507 timestamp = chan_array + idx;
509 timestamp->type = IIO_TIMESTAMP;
510 timestamp->channel = -1;
511 timestamp->scan_index = idx;
512 timestamp->scan_type.sign = 's';
513 timestamp->scan_type.realbits = 64;
514 timestamp->scan_type.storagebits = 64;
516 idev->channels = chan_array;
517 return idev->num_channels;
520 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
521 struct at91_adc_trigger *triggers,
522 const char *trigger_name)
524 struct at91_adc_state *st = iio_priv(idev);
527 for (i = 0; i < st->trigger_number; i++) {
528 char *name = kasprintf(GFP_KERNEL,
536 if (strcmp(trigger_name, name) == 0) {
538 if (triggers[i].value == 0)
540 return triggers[i].value;
549 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
551 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
552 struct at91_adc_state *st = iio_priv(idev);
553 struct at91_adc_reg_desc *reg = st->registers;
554 u32 status = at91_adc_readl(st, reg->trigger_register);
558 value = at91_adc_get_trigger_value_by_name(idev,
565 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
566 if (st->buffer == NULL)
569 at91_adc_writel(st, reg->trigger_register,
572 for_each_set_bit(bit, idev->active_scan_mask,
574 struct iio_chan_spec const *chan = idev->channels + bit;
575 at91_adc_writel(st, AT91_ADC_CHER,
576 AT91_ADC_CH(chan->channel));
579 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
582 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
584 at91_adc_writel(st, reg->trigger_register,
587 for_each_set_bit(bit, idev->active_scan_mask,
589 struct iio_chan_spec const *chan = idev->channels + bit;
590 at91_adc_writel(st, AT91_ADC_CHDR,
591 AT91_ADC_CH(chan->channel));
599 static const struct iio_trigger_ops at91_adc_trigger_ops = {
600 .owner = THIS_MODULE,
601 .set_trigger_state = &at91_adc_configure_trigger,
604 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
605 struct at91_adc_trigger *trigger)
607 struct iio_trigger *trig;
610 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
611 idev->id, trigger->name);
615 trig->dev.parent = idev->dev.parent;
616 iio_trigger_set_drvdata(trig, idev);
617 trig->ops = &at91_adc_trigger_ops;
619 ret = iio_trigger_register(trig);
626 static int at91_adc_trigger_init(struct iio_dev *idev)
628 struct at91_adc_state *st = iio_priv(idev);
631 st->trig = devm_kzalloc(&idev->dev,
632 st->trigger_number * sizeof(*st->trig),
635 if (st->trig == NULL) {
640 for (i = 0; i < st->trigger_number; i++) {
641 if (st->trigger_list[i].is_external && !(st->use_external))
644 st->trig[i] = at91_adc_allocate_trigger(idev,
645 st->trigger_list + i);
646 if (st->trig[i] == NULL) {
648 "Could not allocate trigger %d\n", i);
657 for (i--; i >= 0; i--) {
658 iio_trigger_unregister(st->trig[i]);
659 iio_trigger_free(st->trig[i]);
665 static void at91_adc_trigger_remove(struct iio_dev *idev)
667 struct at91_adc_state *st = iio_priv(idev);
670 for (i = 0; i < st->trigger_number; i++) {
671 iio_trigger_unregister(st->trig[i]);
672 iio_trigger_free(st->trig[i]);
676 static int at91_adc_buffer_init(struct iio_dev *idev)
678 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
679 &at91_adc_trigger_handler, NULL);
682 static void at91_adc_buffer_remove(struct iio_dev *idev)
684 iio_triggered_buffer_cleanup(idev);
687 static int at91_adc_read_raw(struct iio_dev *idev,
688 struct iio_chan_spec const *chan,
689 int *val, int *val2, long mask)
691 struct at91_adc_state *st = iio_priv(idev);
695 case IIO_CHAN_INFO_RAW:
696 mutex_lock(&st->lock);
698 st->chnb = chan->channel;
699 at91_adc_writel(st, AT91_ADC_CHER,
700 AT91_ADC_CH(chan->channel));
701 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
702 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
704 ret = wait_event_interruptible_timeout(st->wq_data_avail,
706 msecs_to_jiffies(1000));
708 /* Disable interrupts, regardless if adc conversion was
711 at91_adc_writel(st, AT91_ADC_CHDR,
712 AT91_ADC_CH(chan->channel));
713 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
716 /* a valid conversion took place */
717 *val = st->last_value;
721 } else if (ret == 0) {
722 /* conversion timeout */
723 dev_err(&idev->dev, "ADC Channel %d timeout.\n",
728 mutex_unlock(&st->lock);
731 case IIO_CHAN_INFO_SCALE:
733 *val2 = chan->scan_type.realbits;
734 return IIO_VAL_FRACTIONAL_LOG2;
741 static int at91_adc_of_get_resolution(struct at91_adc_state *st,
742 struct platform_device *pdev)
744 struct iio_dev *idev = iio_priv_to_dev(st);
745 struct device_node *np = pdev->dev.of_node;
746 int count, i, ret = 0;
750 count = of_property_count_strings(np, "atmel,adc-res-names");
752 dev_err(&idev->dev, "You must specified at least two resolution names for "
753 "adc-res-names property in the DT\n");
757 resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
761 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
762 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
767 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
768 res_name = "highres";
770 for (i = 0; i < count; i++) {
771 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
774 if (strcmp(res_name, s))
777 st->res = resolutions[i];
778 if (!strcmp(res_name, "lowres"))
783 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
787 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
794 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
797 * Number of ticks needed to cover the startup time of the ADC
798 * as defined in the electrical characteristics of the board,
799 * divided by 8. The formula thus is :
800 * Startup Time = (ticks + 1) * 8 / ADC Clock
802 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
805 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
808 * For sama5d3x and at91sam9x5, the formula changes to:
809 * Startup Time = <lookup_table_value> / ADC Clock
811 const int startup_lookup[] = {
817 int i, size = ARRAY_SIZE(startup_lookup);
820 ticks = startup_time * adc_clk_khz / 1000;
821 for (i = 0; i < size; i++)
822 if (ticks < startup_lookup[i])
827 /* Reach the end of lookup table */
833 static const struct of_device_id at91_adc_dt_ids[];
835 static int at91_adc_probe_dt_ts(struct device_node *node,
836 struct at91_adc_state *st, struct device *dev)
841 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
843 dev_info(dev, "ADC Touch screen is disabled.\n");
850 st->touchscreen_type = prop;
853 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
857 if (!st->caps->has_tsmr)
860 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
861 st->ts_pressure_threshold = prop;
862 if (st->ts_pressure_threshold) {
865 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
870 static int at91_adc_probe_dt(struct at91_adc_state *st,
871 struct platform_device *pdev)
873 struct iio_dev *idev = iio_priv_to_dev(st);
874 struct device_node *node = pdev->dev.of_node;
875 struct device_node *trig_node;
882 st->caps = (struct at91_adc_caps *)
883 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
885 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
887 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
888 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
892 st->channels_mask = prop;
894 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
896 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
897 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
901 st->startup_time = prop;
904 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
905 st->sample_hold_time = prop;
907 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
908 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
914 ret = at91_adc_of_get_resolution(st, pdev);
918 st->registers = &st->caps->registers;
919 st->num_channels = st->caps->num_channels;
920 st->trigger_number = of_get_child_count(node);
921 st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
922 sizeof(struct at91_adc_trigger),
924 if (!st->trigger_list) {
925 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
930 for_each_child_of_node(node, trig_node) {
931 struct at91_adc_trigger *trig = st->trigger_list + i;
934 if (of_property_read_string(trig_node, "trigger-name", &name)) {
935 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
941 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
942 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
947 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
951 /* Check if touchscreen is supported. */
952 if (st->caps->has_ts)
953 return at91_adc_probe_dt_ts(node, st, &idev->dev);
955 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
963 static int at91_adc_probe_pdata(struct at91_adc_state *st,
964 struct platform_device *pdev)
966 struct at91_adc_data *pdata = pdev->dev.platform_data;
971 st->caps = (struct at91_adc_caps *)
972 platform_get_device_id(pdev)->driver_data;
974 st->use_external = pdata->use_external_triggers;
975 st->vref_mv = pdata->vref;
976 st->channels_mask = pdata->channels_used;
977 st->num_channels = st->caps->num_channels;
978 st->startup_time = pdata->startup_time;
979 st->trigger_number = pdata->trigger_number;
980 st->trigger_list = pdata->trigger_list;
981 st->registers = &st->caps->registers;
982 st->touchscreen_type = pdata->touchscreen_type;
987 static const struct iio_info at91_adc_info = {
988 .driver_module = THIS_MODULE,
989 .read_raw = &at91_adc_read_raw,
992 /* Touchscreen related functions */
993 static int atmel_ts_open(struct input_dev *dev)
995 struct at91_adc_state *st = input_get_drvdata(dev);
997 if (st->caps->has_tsmr)
998 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
1000 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
1004 static void atmel_ts_close(struct input_dev *dev)
1006 struct at91_adc_state *st = input_get_drvdata(dev);
1008 if (st->caps->has_tsmr)
1009 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1011 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1014 static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1016 struct iio_dev *idev = iio_priv_to_dev(st);
1021 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1023 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1025 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1028 while (st->ts_pendbc >> ++i)
1029 ; /* Empty! Find the shift offset */
1030 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1033 st->ts_pendbc = i - 1;
1035 if (!st->caps->has_tsmr) {
1036 reg = at91_adc_readl(st, AT91_ADC_MR);
1037 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1039 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1040 at91_adc_writel(st, AT91_ADC_MR, reg);
1042 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1043 at91_adc_writel(st, AT91_ADC_TSR, reg);
1045 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1046 adc_clk_khz / 1000) - 1, 1);
1051 /* Touchscreen Switches Closure time needed for allowing the value to
1053 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
1055 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
1056 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
1057 adc_clk_khz, tssctim);
1059 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1060 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1062 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1064 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
1065 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1066 & AT91_ADC_TSMR_TSAV;
1067 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1068 reg |= AT91_ADC_TSMR_NOTSDMA;
1069 reg |= AT91_ADC_TSMR_PENDET_ENA;
1070 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
1072 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1074 /* Change adc internal resistor value for better pen detection,
1075 * default value is 100 kOhm.
1076 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1077 * option only available on ES2 and higher
1079 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1080 & AT91_ADC_ACR_PENDETSENS);
1082 /* Sample Period Time = (TRGPER + 1) / ADCClock */
1083 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1084 adc_clk_khz / 1000) - 1, 1);
1089 static int at91_ts_register(struct at91_adc_state *st,
1090 struct platform_device *pdev)
1092 struct input_dev *input;
1093 struct iio_dev *idev = iio_priv_to_dev(st);
1096 input = input_allocate_device();
1098 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1102 input->name = DRIVER_NAME;
1103 input->id.bustype = BUS_HOST;
1104 input->dev.parent = &pdev->dev;
1105 input->open = atmel_ts_open;
1106 input->close = atmel_ts_close;
1108 __set_bit(EV_ABS, input->evbit);
1109 __set_bit(EV_KEY, input->evbit);
1110 __set_bit(BTN_TOUCH, input->keybit);
1111 if (st->caps->has_tsmr) {
1112 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1114 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1116 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1118 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1120 "This touchscreen controller only support 4 wires\n");
1125 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1127 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1131 st->ts_input = input;
1132 input_set_drvdata(input, st);
1134 ret = input_register_device(input);
1141 input_free_device(st->ts_input);
1145 static void at91_ts_unregister(struct at91_adc_state *st)
1147 input_unregister_device(st->ts_input);
1150 static int at91_adc_probe(struct platform_device *pdev)
1152 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1154 struct iio_dev *idev;
1155 struct at91_adc_state *st;
1156 struct resource *res;
1159 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1163 st = iio_priv(idev);
1165 if (pdev->dev.of_node)
1166 ret = at91_adc_probe_dt(st, pdev);
1168 ret = at91_adc_probe_pdata(st, pdev);
1171 dev_err(&pdev->dev, "No platform data available.\n");
1175 platform_set_drvdata(pdev, idev);
1177 idev->dev.parent = &pdev->dev;
1178 idev->name = dev_name(&pdev->dev);
1179 idev->modes = INDIO_DIRECT_MODE;
1180 idev->info = &at91_adc_info;
1182 st->irq = platform_get_irq(pdev, 0);
1184 dev_err(&pdev->dev, "No IRQ ID is designated\n");
1188 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1190 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1191 if (IS_ERR(st->reg_base)) {
1192 return PTR_ERR(st->reg_base);
1196 * Disable all IRQs before setting up the handler
1198 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1199 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1201 if (st->caps->has_tsmr)
1202 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1203 pdev->dev.driver->name, idev);
1205 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1206 pdev->dev.driver->name, idev);
1208 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1212 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1213 if (IS_ERR(st->clk)) {
1214 dev_err(&pdev->dev, "Failed to get the clock.\n");
1215 ret = PTR_ERR(st->clk);
1216 goto error_free_irq;
1219 ret = clk_prepare_enable(st->clk);
1222 "Could not prepare or enable the clock.\n");
1223 goto error_free_irq;
1226 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1227 if (IS_ERR(st->adc_clk)) {
1228 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1229 ret = PTR_ERR(st->adc_clk);
1230 goto error_disable_clk;
1233 ret = clk_prepare_enable(st->adc_clk);
1236 "Could not prepare or enable the ADC clock.\n");
1237 goto error_disable_clk;
1241 * Prescaler rate computation using the formula from the Atmel's
1242 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1243 * specified by the electrical characteristics of the board.
1245 mstrclk = clk_get_rate(st->clk);
1246 adc_clk = clk_get_rate(st->adc_clk);
1247 adc_clk_khz = adc_clk / 1000;
1249 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1252 prsc = (mstrclk / (2 * adc_clk)) - 1;
1254 if (!st->startup_time) {
1255 dev_err(&pdev->dev, "No startup time available.\n");
1257 goto error_disable_adc_clk;
1259 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1262 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1263 * the best converted final value between two channels selection
1264 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1266 if (st->sample_hold_time > 0)
1267 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1272 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1273 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1275 reg |= AT91_ADC_LOWRES;
1277 reg |= AT91_ADC_SLEEP;
1278 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1279 at91_adc_writel(st, AT91_ADC_MR, reg);
1281 /* Setup the ADC channels available on the board */
1282 ret = at91_adc_channel_init(idev);
1284 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1285 goto error_disable_adc_clk;
1288 init_waitqueue_head(&st->wq_data_avail);
1289 mutex_init(&st->lock);
1292 * Since touch screen will set trigger register as period trigger. So
1293 * when touch screen is enabled, then we have to disable hardware
1294 * trigger for classic adc.
1296 if (!st->touchscreen_type) {
1297 ret = at91_adc_buffer_init(idev);
1299 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1300 goto error_disable_adc_clk;
1303 ret = at91_adc_trigger_init(idev);
1305 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1306 at91_adc_buffer_remove(idev);
1307 goto error_disable_adc_clk;
1310 ret = at91_ts_register(st, pdev);
1312 goto error_disable_adc_clk;
1314 at91_ts_hw_init(st, adc_clk_khz);
1317 ret = iio_device_register(idev);
1319 dev_err(&pdev->dev, "Couldn't register the device.\n");
1320 goto error_iio_device_register;
1325 error_iio_device_register:
1326 if (!st->touchscreen_type) {
1327 at91_adc_trigger_remove(idev);
1328 at91_adc_buffer_remove(idev);
1330 at91_ts_unregister(st);
1332 error_disable_adc_clk:
1333 clk_disable_unprepare(st->adc_clk);
1335 clk_disable_unprepare(st->clk);
1337 free_irq(st->irq, idev);
1341 static int at91_adc_remove(struct platform_device *pdev)
1343 struct iio_dev *idev = platform_get_drvdata(pdev);
1344 struct at91_adc_state *st = iio_priv(idev);
1346 iio_device_unregister(idev);
1347 if (!st->touchscreen_type) {
1348 at91_adc_trigger_remove(idev);
1349 at91_adc_buffer_remove(idev);
1351 at91_ts_unregister(st);
1353 clk_disable_unprepare(st->adc_clk);
1354 clk_disable_unprepare(st->clk);
1355 free_irq(st->irq, idev);
1360 static struct at91_adc_caps at91sam9260_caps = {
1361 .calc_startup_ticks = calc_startup_ticks_9260,
1364 .channel_base = AT91_ADC_CHR(0),
1365 .drdy_mask = AT91_ADC_DRDY,
1366 .status_register = AT91_ADC_SR,
1367 .trigger_register = AT91_ADC_TRGR_9260,
1368 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1369 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1373 static struct at91_adc_caps at91sam9rl_caps = {
1375 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1378 .channel_base = AT91_ADC_CHR(0),
1379 .drdy_mask = AT91_ADC_DRDY,
1380 .status_register = AT91_ADC_SR,
1381 .trigger_register = AT91_ADC_TRGR_9G45,
1382 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1383 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1387 static struct at91_adc_caps at91sam9g45_caps = {
1389 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1392 .channel_base = AT91_ADC_CHR(0),
1393 .drdy_mask = AT91_ADC_DRDY,
1394 .status_register = AT91_ADC_SR,
1395 .trigger_register = AT91_ADC_TRGR_9G45,
1396 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1397 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1401 static struct at91_adc_caps at91sam9x5_caps = {
1404 .ts_filter_average = 3,
1405 .ts_pen_detect_sensitivity = 2,
1406 .calc_startup_ticks = calc_startup_ticks_9x5,
1409 .channel_base = AT91_ADC_CDR0_9X5,
1410 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1411 .status_register = AT91_ADC_SR_9X5,
1412 .trigger_register = AT91_ADC_TRGR_9X5,
1413 /* prescal mask is same as 9G45 */
1414 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1415 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1419 static const struct of_device_id at91_adc_dt_ids[] = {
1420 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1421 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1422 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1423 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1426 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1428 static const struct platform_device_id at91_adc_ids[] = {
1430 .name = "at91sam9260-adc",
1431 .driver_data = (unsigned long)&at91sam9260_caps,
1433 .name = "at91sam9rl-adc",
1434 .driver_data = (unsigned long)&at91sam9rl_caps,
1436 .name = "at91sam9g45-adc",
1437 .driver_data = (unsigned long)&at91sam9g45_caps,
1439 .name = "at91sam9x5-adc",
1440 .driver_data = (unsigned long)&at91sam9x5_caps,
1445 MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1447 static struct platform_driver at91_adc_driver = {
1448 .probe = at91_adc_probe,
1449 .remove = at91_adc_remove,
1450 .id_table = at91_adc_ids,
1452 .name = DRIVER_NAME,
1453 .of_match_table = of_match_ptr(at91_adc_dt_ids),
1457 module_platform_driver(at91_adc_driver);
1459 MODULE_LICENSE("GPL");
1460 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1461 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");