2 * Driver for the ADC present in the Atmel AT91 evaluation boards.
4 * Copyright 2011 Free Electrons
6 * Licensed under the GPLv2 or later.
9 #include <linux/bitmap.h>
10 #include <linux/bitops.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
14 #include <linux/input.h>
15 #include <linux/interrupt.h>
16 #include <linux/jiffies.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
20 #include <linux/of_device.h>
21 #include <linux/platform_device.h>
22 #include <linux/sched.h>
23 #include <linux/slab.h>
24 #include <linux/wait.h>
26 #include <linux/platform_data/at91_adc.h>
28 #include <linux/iio/iio.h>
29 #include <linux/iio/buffer.h>
30 #include <linux/iio/trigger.h>
31 #include <linux/iio/trigger_consumer.h>
32 #include <linux/iio/triggered_buffer.h>
33 #include <linux/pinctrl/consumer.h>
36 #define AT91_ADC_CR 0x00 /* Control Register */
37 #define AT91_ADC_SWRST (1 << 0) /* Software Reset */
38 #define AT91_ADC_START (1 << 1) /* Start Conversion */
40 #define AT91_ADC_MR 0x04 /* Mode Register */
41 #define AT91_ADC_TSAMOD (3 << 0) /* ADC mode */
42 #define AT91_ADC_TSAMOD_ADC_ONLY_MODE (0 << 0) /* ADC Mode */
43 #define AT91_ADC_TSAMOD_TS_ONLY_MODE (1 << 0) /* Touch Screen Only Mode */
44 #define AT91_ADC_TRGEN (1 << 0) /* Trigger Enable */
45 #define AT91_ADC_TRGSEL (7 << 1) /* Trigger Selection */
46 #define AT91_ADC_TRGSEL_TC0 (0 << 1)
47 #define AT91_ADC_TRGSEL_TC1 (1 << 1)
48 #define AT91_ADC_TRGSEL_TC2 (2 << 1)
49 #define AT91_ADC_TRGSEL_EXTERNAL (6 << 1)
50 #define AT91_ADC_LOWRES (1 << 4) /* Low Resolution */
51 #define AT91_ADC_SLEEP (1 << 5) /* Sleep Mode */
52 #define AT91_ADC_PENDET (1 << 6) /* Pen contact detection enable */
53 #define AT91_ADC_PRESCAL_9260 (0x3f << 8) /* Prescalar Rate Selection */
54 #define AT91_ADC_PRESCAL_9G45 (0xff << 8)
55 #define AT91_ADC_PRESCAL_(x) ((x) << 8)
56 #define AT91_ADC_STARTUP_9260 (0x1f << 16) /* Startup Up Time */
57 #define AT91_ADC_STARTUP_9G45 (0x7f << 16)
58 #define AT91_ADC_STARTUP_9X5 (0xf << 16)
59 #define AT91_ADC_STARTUP_(x) ((x) << 16)
60 #define AT91_ADC_SHTIM (0xf << 24) /* Sample & Hold Time */
61 #define AT91_ADC_SHTIM_(x) ((x) << 24)
62 #define AT91_ADC_PENDBC (0x0f << 28) /* Pen Debounce time */
63 #define AT91_ADC_PENDBC_(x) ((x) << 28)
65 #define AT91_ADC_TSR 0x0C
66 #define AT91_ADC_TSR_SHTIM (0xf << 24) /* Sample & Hold Time */
67 #define AT91_ADC_TSR_SHTIM_(x) ((x) << 24)
69 #define AT91_ADC_CHER 0x10 /* Channel Enable Register */
70 #define AT91_ADC_CHDR 0x14 /* Channel Disable Register */
71 #define AT91_ADC_CHSR 0x18 /* Channel Status Register */
72 #define AT91_ADC_CH(n) (1 << (n)) /* Channel Number */
74 #define AT91_ADC_SR 0x1C /* Status Register */
75 #define AT91_ADC_EOC(n) (1 << (n)) /* End of Conversion on Channel N */
76 #define AT91_ADC_OVRE(n) (1 << ((n) + 8))/* Overrun Error on Channel N */
77 #define AT91_ADC_DRDY (1 << 16) /* Data Ready */
78 #define AT91_ADC_GOVRE (1 << 17) /* General Overrun Error */
79 #define AT91_ADC_ENDRX (1 << 18) /* End of RX Buffer */
80 #define AT91_ADC_RXFUFF (1 << 19) /* RX Buffer Full */
82 #define AT91_ADC_SR_9X5 0x30 /* Status Register for 9x5 */
83 #define AT91_ADC_SR_DRDY_9X5 (1 << 24) /* Data Ready */
85 #define AT91_ADC_LCDR 0x20 /* Last Converted Data Register */
86 #define AT91_ADC_LDATA (0x3ff)
88 #define AT91_ADC_IER 0x24 /* Interrupt Enable Register */
89 #define AT91_ADC_IDR 0x28 /* Interrupt Disable Register */
90 #define AT91_ADC_IMR 0x2C /* Interrupt Mask Register */
91 #define AT91RL_ADC_IER_PEN (1 << 20)
92 #define AT91RL_ADC_IER_NOPEN (1 << 21)
93 #define AT91_ADC_IER_PEN (1 << 29)
94 #define AT91_ADC_IER_NOPEN (1 << 30)
95 #define AT91_ADC_IER_XRDY (1 << 20)
96 #define AT91_ADC_IER_YRDY (1 << 21)
97 #define AT91_ADC_IER_PRDY (1 << 22)
98 #define AT91_ADC_ISR_PENS (1 << 31)
100 #define AT91_ADC_CHR(n) (0x30 + ((n) * 4)) /* Channel Data Register N */
101 #define AT91_ADC_DATA (0x3ff)
103 #define AT91_ADC_CDR0_9X5 (0x50) /* Channel Data Register 0 for 9X5 */
105 #define AT91_ADC_ACR 0x94 /* Analog Control Register */
106 #define AT91_ADC_ACR_PENDETSENS (0x3 << 0) /* pull-up resistor */
108 #define AT91_ADC_TSMR 0xB0
109 #define AT91_ADC_TSMR_TSMODE (3 << 0) /* Touch Screen Mode */
110 #define AT91_ADC_TSMR_TSMODE_NONE (0 << 0)
111 #define AT91_ADC_TSMR_TSMODE_4WIRE_NO_PRESS (1 << 0)
112 #define AT91_ADC_TSMR_TSMODE_4WIRE_PRESS (2 << 0)
113 #define AT91_ADC_TSMR_TSMODE_5WIRE (3 << 0)
114 #define AT91_ADC_TSMR_TSAV (3 << 4) /* Averages samples */
115 #define AT91_ADC_TSMR_TSAV_(x) ((x) << 4)
116 #define AT91_ADC_TSMR_SCTIM (0x0f << 16) /* Switch closure time */
117 #define AT91_ADC_TSMR_SCTIM_(x) ((x) << 16)
118 #define AT91_ADC_TSMR_PENDBC (0x0f << 28) /* Pen Debounce time */
119 #define AT91_ADC_TSMR_PENDBC_(x) ((x) << 28)
120 #define AT91_ADC_TSMR_NOTSDMA (1 << 22) /* No Touchscreen DMA */
121 #define AT91_ADC_TSMR_PENDET_DIS (0 << 24) /* Pen contact detection disable */
122 #define AT91_ADC_TSMR_PENDET_ENA (1 << 24) /* Pen contact detection enable */
124 #define AT91_ADC_TSXPOSR 0xB4
125 #define AT91_ADC_TSYPOSR 0xB8
126 #define AT91_ADC_TSPRESSR 0xBC
128 #define AT91_ADC_TRGR_9260 AT91_ADC_MR
129 #define AT91_ADC_TRGR_9G45 0x08
130 #define AT91_ADC_TRGR_9X5 0xC0
132 /* Trigger Register bit field */
133 #define AT91_ADC_TRGR_TRGPER (0xffff << 16)
134 #define AT91_ADC_TRGR_TRGPER_(x) ((x) << 16)
135 #define AT91_ADC_TRGR_TRGMOD (0x7 << 0)
136 #define AT91_ADC_TRGR_NONE (0 << 0)
137 #define AT91_ADC_TRGR_MOD_PERIOD_TRIG (5 << 0)
139 #define AT91_ADC_CHAN(st, ch) \
140 (st->registers->channel_base + (ch * 4))
141 #define at91_adc_readl(st, reg) \
142 (readl_relaxed(st->reg_base + reg))
143 #define at91_adc_writel(st, reg, val) \
144 (writel_relaxed(val, st->reg_base + reg))
146 #define DRIVER_NAME "at91_adc"
147 #define MAX_POS_BITS 12
149 #define TOUCH_SAMPLE_PERIOD_US 2000 /* 2ms */
150 #define TOUCH_PEN_DETECT_DEBOUNCE_US 200
152 #define MAX_RLPOS_BITS 10
153 #define TOUCH_SAMPLE_PERIOD_US_RL 10000 /* 10ms, the SoC can't keep up with 2ms */
154 #define TOUCH_SHTIM 0xa
155 #define TOUCH_SCTIM_US 10 /* 10us for the Touchscreen Switches Closure Time */
158 * struct at91_adc_reg_desc - Various informations relative to registers
159 * @channel_base: Base offset for the channel data registers
160 * @drdy_mask: Mask of the DRDY field in the relevant registers
161 (Interruptions registers mostly)
162 * @status_register: Offset of the Interrupt Status Register
163 * @trigger_register: Offset of the Trigger setup register
164 * @mr_prescal_mask: Mask of the PRESCAL field in the adc MR register
165 * @mr_startup_mask: Mask of the STARTUP field in the adc MR register
167 struct at91_adc_reg_desc {
176 struct at91_adc_caps {
177 bool has_ts; /* Support touch screen */
178 bool has_tsmr; /* only at91sam9x5, sama5d3 have TSMR reg */
180 * Numbers of sampling data will be averaged. Can be 0~3.
181 * Hardware can average (2 ^ ts_filter_average) sample data.
183 u8 ts_filter_average;
184 /* Pen Detection input pull-up resistor, can be 0~3 */
185 u8 ts_pen_detect_sensitivity;
187 /* startup time calculate function */
188 u32 (*calc_startup_ticks)(u32 startup_time, u32 adc_clk_khz);
191 struct at91_adc_reg_desc registers;
194 struct at91_adc_state {
197 unsigned long channels_mask;
205 void __iomem *reg_base;
206 struct at91_adc_reg_desc *registers;
210 struct iio_trigger **trig;
211 struct at91_adc_trigger *trigger_list;
215 u32 res; /* resolution used for convertions */
216 bool low_res; /* the resolution corresponds to the lowest one */
217 wait_queue_head_t wq_data_avail;
218 struct at91_adc_caps *caps;
221 * Following ADC channels are shared by touchscreen:
223 * CH0 -- Touch screen XP/UL
224 * CH1 -- Touch screen XM/UR
225 * CH2 -- Touch screen YP/LL
226 * CH3 -- Touch screen YM/Sense
227 * CH4 -- Touch screen LR(5-wire only)
229 * The bitfields below represents the reserved channel in the
232 #define CHAN_MASK_TOUCHSCREEN_4WIRE (0xf << 0)
233 #define CHAN_MASK_TOUCHSCREEN_5WIRE (0x1f << 0)
234 enum atmel_adc_ts_type touchscreen_type;
235 struct input_dev *ts_input;
237 u16 ts_sample_period_val;
238 u32 ts_pressure_threshold;
241 bool ts_bufferedmeasure;
246 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
248 struct iio_poll_func *pf = p;
249 struct iio_dev *idev = pf->indio_dev;
250 struct at91_adc_state *st = iio_priv(idev);
251 struct iio_chan_spec const *chan;
254 for (i = 0; i < idev->masklength; i++) {
255 if (!test_bit(i, idev->active_scan_mask))
257 chan = idev->channels + i;
258 st->buffer[j] = at91_adc_readl(st, AT91_ADC_CHAN(st, chan->channel));
262 iio_push_to_buffers_with_timestamp(idev, st->buffer, pf->timestamp);
264 iio_trigger_notify_done(idev->trig);
266 /* Needed to ACK the DRDY interruption */
267 at91_adc_readl(st, AT91_ADC_LCDR);
274 /* Handler for classic adc channel eoc trigger */
275 static void handle_adc_eoc_trigger(int irq, struct iio_dev *idev)
277 struct at91_adc_state *st = iio_priv(idev);
279 if (iio_buffer_enabled(idev)) {
280 disable_irq_nosync(irq);
281 iio_trigger_poll(idev->trig);
283 st->last_value = at91_adc_readl(st, AT91_ADC_CHAN(st, st->chnb));
284 /* Needed to ACK the DRDY interruption */
285 at91_adc_readl(st, AT91_ADC_LCDR);
287 wake_up_interruptible(&st->wq_data_avail);
291 static int at91_ts_sample(struct at91_adc_state *st)
293 unsigned int xscale, yscale, reg, z1, z2;
294 unsigned int x, y, pres, xpos, ypos;
295 unsigned int rxp = 1;
296 unsigned int factor = 1000;
297 struct iio_dev *idev = iio_priv_to_dev(st);
299 unsigned int xyz_mask_bits = st->res;
300 unsigned int xyz_mask = (1 << xyz_mask_bits) - 1;
302 /* calculate position */
303 /* x position = (x / xscale) * max, max = 2^MAX_POS_BITS - 1 */
304 reg = at91_adc_readl(st, AT91_ADC_TSXPOSR);
305 xpos = reg & xyz_mask;
306 x = (xpos << MAX_POS_BITS) - xpos;
307 xscale = (reg >> 16) & xyz_mask;
309 dev_err(&idev->dev, "Error: xscale == 0!\n");
314 /* y position = (y / yscale) * max, max = 2^MAX_POS_BITS - 1 */
315 reg = at91_adc_readl(st, AT91_ADC_TSYPOSR);
316 ypos = reg & xyz_mask;
317 y = (ypos << MAX_POS_BITS) - ypos;
318 yscale = (reg >> 16) & xyz_mask;
320 dev_err(&idev->dev, "Error: yscale == 0!\n");
325 /* calculate the pressure */
326 reg = at91_adc_readl(st, AT91_ADC_TSPRESSR);
328 z2 = (reg >> 16) & xyz_mask;
331 pres = rxp * (x * factor / 1024) * (z2 * factor / z1 - factor)
334 pres = st->ts_pressure_threshold; /* no pen contacted */
336 dev_dbg(&idev->dev, "xpos = %d, xscale = %d, ypos = %d, yscale = %d, z1 = %d, z2 = %d, press = %d\n",
337 xpos, xscale, ypos, yscale, z1, z2, pres);
339 if (pres < st->ts_pressure_threshold) {
340 dev_dbg(&idev->dev, "x = %d, y = %d, pressure = %d\n",
341 x, y, pres / factor);
342 input_report_abs(st->ts_input, ABS_X, x);
343 input_report_abs(st->ts_input, ABS_Y, y);
344 input_report_abs(st->ts_input, ABS_PRESSURE, pres);
345 input_report_key(st->ts_input, BTN_TOUCH, 1);
346 input_sync(st->ts_input);
348 dev_dbg(&idev->dev, "pressure too low: not reporting\n");
354 static irqreturn_t at91_adc_rl_interrupt(int irq, void *private)
356 struct iio_dev *idev = private;
357 struct at91_adc_state *st = iio_priv(idev);
358 u32 status = at91_adc_readl(st, st->registers->status_register);
361 status &= at91_adc_readl(st, AT91_ADC_IMR);
362 if (status & GENMASK(st->num_channels - 1, 0))
363 handle_adc_eoc_trigger(irq, idev);
365 if (status & AT91RL_ADC_IER_PEN) {
366 /* Disabling pen debounce is required to get a NOPEN irq */
367 reg = at91_adc_readl(st, AT91_ADC_MR);
368 reg &= ~AT91_ADC_PENDBC;
369 at91_adc_writel(st, AT91_ADC_MR, reg);
371 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
372 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_NOPEN
374 /* Set up period trigger for sampling */
375 at91_adc_writel(st, st->registers->trigger_register,
376 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
377 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
378 } else if (status & AT91RL_ADC_IER_NOPEN) {
379 reg = at91_adc_readl(st, AT91_ADC_MR);
380 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
381 at91_adc_writel(st, AT91_ADC_MR, reg);
382 at91_adc_writel(st, st->registers->trigger_register,
385 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_NOPEN
387 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
388 st->ts_bufferedmeasure = false;
389 input_report_key(st->ts_input, BTN_TOUCH, 0);
390 input_sync(st->ts_input);
391 } else if (status & AT91_ADC_EOC(3) && st->ts_input) {
392 /* Conversion finished and we've a touchscreen */
393 if (st->ts_bufferedmeasure) {
395 * Last measurement is always discarded, since it can
397 * Always report previous measurement
399 input_report_abs(st->ts_input, ABS_X, st->ts_prev_absx);
400 input_report_abs(st->ts_input, ABS_Y, st->ts_prev_absy);
401 input_report_key(st->ts_input, BTN_TOUCH, 1);
402 input_sync(st->ts_input);
404 st->ts_bufferedmeasure = true;
406 /* Now make new measurement */
407 st->ts_prev_absx = at91_adc_readl(st, AT91_ADC_CHAN(st, 3))
409 st->ts_prev_absx /= at91_adc_readl(st, AT91_ADC_CHAN(st, 2));
411 st->ts_prev_absy = at91_adc_readl(st, AT91_ADC_CHAN(st, 1))
413 st->ts_prev_absy /= at91_adc_readl(st, AT91_ADC_CHAN(st, 0));
419 static irqreturn_t at91_adc_9x5_interrupt(int irq, void *private)
421 struct iio_dev *idev = private;
422 struct at91_adc_state *st = iio_priv(idev);
423 u32 status = at91_adc_readl(st, st->registers->status_register);
424 const uint32_t ts_data_irq_mask =
429 if (status & GENMASK(st->num_channels - 1, 0))
430 handle_adc_eoc_trigger(irq, idev);
432 if (status & AT91_ADC_IER_PEN) {
433 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
434 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_NOPEN |
436 /* Set up period trigger for sampling */
437 at91_adc_writel(st, st->registers->trigger_register,
438 AT91_ADC_TRGR_MOD_PERIOD_TRIG |
439 AT91_ADC_TRGR_TRGPER_(st->ts_sample_period_val));
440 } else if (status & AT91_ADC_IER_NOPEN) {
441 at91_adc_writel(st, st->registers->trigger_register, 0);
442 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_NOPEN |
444 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
446 input_report_key(st->ts_input, BTN_TOUCH, 0);
447 input_sync(st->ts_input);
448 } else if ((status & ts_data_irq_mask) == ts_data_irq_mask) {
449 /* Now all touchscreen data is ready */
451 if (status & AT91_ADC_ISR_PENS) {
452 /* validate data by pen contact */
455 /* triggered by event that is no pen contact, just read
456 * them to clean the interrupt and discard all.
458 at91_adc_readl(st, AT91_ADC_TSXPOSR);
459 at91_adc_readl(st, AT91_ADC_TSYPOSR);
460 at91_adc_readl(st, AT91_ADC_TSPRESSR);
467 static int at91_adc_channel_init(struct iio_dev *idev)
469 struct at91_adc_state *st = iio_priv(idev);
470 struct iio_chan_spec *chan_array, *timestamp;
472 unsigned long rsvd_mask = 0;
474 /* If touchscreen is enable, then reserve the adc channels */
475 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
476 rsvd_mask = CHAN_MASK_TOUCHSCREEN_4WIRE;
477 else if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_5WIRE)
478 rsvd_mask = CHAN_MASK_TOUCHSCREEN_5WIRE;
480 /* set up the channel mask to reserve touchscreen channels */
481 st->channels_mask &= ~rsvd_mask;
483 idev->num_channels = bitmap_weight(&st->channels_mask,
484 st->num_channels) + 1;
486 chan_array = devm_kzalloc(&idev->dev,
487 ((idev->num_channels + 1) *
488 sizeof(struct iio_chan_spec)),
494 for_each_set_bit(bit, &st->channels_mask, st->num_channels) {
495 struct iio_chan_spec *chan = chan_array + idx;
497 chan->type = IIO_VOLTAGE;
500 chan->scan_index = idx;
501 chan->scan_type.sign = 'u';
502 chan->scan_type.realbits = st->res;
503 chan->scan_type.storagebits = 16;
504 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE);
505 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
508 timestamp = chan_array + idx;
510 timestamp->type = IIO_TIMESTAMP;
511 timestamp->channel = -1;
512 timestamp->scan_index = idx;
513 timestamp->scan_type.sign = 's';
514 timestamp->scan_type.realbits = 64;
515 timestamp->scan_type.storagebits = 64;
517 idev->channels = chan_array;
518 return idev->num_channels;
521 static int at91_adc_get_trigger_value_by_name(struct iio_dev *idev,
522 struct at91_adc_trigger *triggers,
523 const char *trigger_name)
525 struct at91_adc_state *st = iio_priv(idev);
528 for (i = 0; i < st->trigger_number; i++) {
529 char *name = kasprintf(GFP_KERNEL,
537 if (strcmp(trigger_name, name) == 0) {
539 if (triggers[i].value == 0)
541 return triggers[i].value;
550 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
552 struct iio_dev *idev = iio_trigger_get_drvdata(trig);
553 struct at91_adc_state *st = iio_priv(idev);
554 struct at91_adc_reg_desc *reg = st->registers;
555 u32 status = at91_adc_readl(st, reg->trigger_register);
559 value = at91_adc_get_trigger_value_by_name(idev,
566 st->buffer = kmalloc(idev->scan_bytes, GFP_KERNEL);
567 if (st->buffer == NULL)
570 at91_adc_writel(st, reg->trigger_register,
573 for_each_set_bit(bit, idev->active_scan_mask,
575 struct iio_chan_spec const *chan = idev->channels + bit;
576 at91_adc_writel(st, AT91_ADC_CHER,
577 AT91_ADC_CH(chan->channel));
580 at91_adc_writel(st, AT91_ADC_IER, reg->drdy_mask);
583 at91_adc_writel(st, AT91_ADC_IDR, reg->drdy_mask);
585 at91_adc_writel(st, reg->trigger_register,
588 for_each_set_bit(bit, idev->active_scan_mask,
590 struct iio_chan_spec const *chan = idev->channels + bit;
591 at91_adc_writel(st, AT91_ADC_CHDR,
592 AT91_ADC_CH(chan->channel));
600 static const struct iio_trigger_ops at91_adc_trigger_ops = {
601 .owner = THIS_MODULE,
602 .set_trigger_state = &at91_adc_configure_trigger,
605 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *idev,
606 struct at91_adc_trigger *trigger)
608 struct iio_trigger *trig;
611 trig = iio_trigger_alloc("%s-dev%d-%s", idev->name,
612 idev->id, trigger->name);
616 trig->dev.parent = idev->dev.parent;
617 iio_trigger_set_drvdata(trig, idev);
618 trig->ops = &at91_adc_trigger_ops;
620 ret = iio_trigger_register(trig);
627 static int at91_adc_trigger_init(struct iio_dev *idev)
629 struct at91_adc_state *st = iio_priv(idev);
632 st->trig = devm_kzalloc(&idev->dev,
633 st->trigger_number * sizeof(*st->trig),
636 if (st->trig == NULL) {
641 for (i = 0; i < st->trigger_number; i++) {
642 if (st->trigger_list[i].is_external && !(st->use_external))
645 st->trig[i] = at91_adc_allocate_trigger(idev,
646 st->trigger_list + i);
647 if (st->trig[i] == NULL) {
649 "Could not allocate trigger %d\n", i);
658 for (i--; i >= 0; i--) {
659 iio_trigger_unregister(st->trig[i]);
660 iio_trigger_free(st->trig[i]);
666 static void at91_adc_trigger_remove(struct iio_dev *idev)
668 struct at91_adc_state *st = iio_priv(idev);
671 for (i = 0; i < st->trigger_number; i++) {
672 iio_trigger_unregister(st->trig[i]);
673 iio_trigger_free(st->trig[i]);
677 static int at91_adc_buffer_init(struct iio_dev *idev)
679 return iio_triggered_buffer_setup(idev, &iio_pollfunc_store_time,
680 &at91_adc_trigger_handler, NULL);
683 static void at91_adc_buffer_remove(struct iio_dev *idev)
685 iio_triggered_buffer_cleanup(idev);
688 static int at91_adc_read_raw(struct iio_dev *idev,
689 struct iio_chan_spec const *chan,
690 int *val, int *val2, long mask)
692 struct at91_adc_state *st = iio_priv(idev);
696 case IIO_CHAN_INFO_RAW:
697 mutex_lock(&st->lock);
699 st->chnb = chan->channel;
700 at91_adc_writel(st, AT91_ADC_CHER,
701 AT91_ADC_CH(chan->channel));
702 at91_adc_writel(st, AT91_ADC_IER, BIT(chan->channel));
703 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_START);
705 ret = wait_event_interruptible_timeout(st->wq_data_avail,
707 msecs_to_jiffies(1000));
709 /* Disable interrupts, regardless if adc conversion was
712 at91_adc_writel(st, AT91_ADC_CHDR,
713 AT91_ADC_CH(chan->channel));
714 at91_adc_writel(st, AT91_ADC_IDR, BIT(chan->channel));
717 /* a valid conversion took place */
718 *val = st->last_value;
722 } else if (ret == 0) {
723 /* conversion timeout */
724 dev_err(&idev->dev, "ADC Channel %d timeout.\n",
729 mutex_unlock(&st->lock);
732 case IIO_CHAN_INFO_SCALE:
734 *val2 = chan->scan_type.realbits;
735 return IIO_VAL_FRACTIONAL_LOG2;
742 static int at91_adc_of_get_resolution(struct at91_adc_state *st,
743 struct platform_device *pdev)
745 struct iio_dev *idev = iio_priv_to_dev(st);
746 struct device_node *np = pdev->dev.of_node;
747 int count, i, ret = 0;
751 count = of_property_count_strings(np, "atmel,adc-res-names");
753 dev_err(&idev->dev, "You must specified at least two resolution names for "
754 "adc-res-names property in the DT\n");
758 resolutions = kmalloc_array(count, sizeof(*resolutions), GFP_KERNEL);
762 if (of_property_read_u32_array(np, "atmel,adc-res", resolutions, count)) {
763 dev_err(&idev->dev, "Missing adc-res property in the DT.\n");
768 if (of_property_read_string(np, "atmel,adc-use-res", (const char **)&res_name))
769 res_name = "highres";
771 for (i = 0; i < count; i++) {
772 if (of_property_read_string_index(np, "atmel,adc-res-names", i, (const char **)&s))
775 if (strcmp(res_name, s))
778 st->res = resolutions[i];
779 if (!strcmp(res_name, "lowres"))
784 dev_info(&idev->dev, "Resolution used: %u bits\n", st->res);
788 dev_err(&idev->dev, "There is no resolution for %s\n", res_name);
795 static u32 calc_startup_ticks_9260(u32 startup_time, u32 adc_clk_khz)
798 * Number of ticks needed to cover the startup time of the ADC
799 * as defined in the electrical characteristics of the board,
800 * divided by 8. The formula thus is :
801 * Startup Time = (ticks + 1) * 8 / ADC Clock
803 return round_up((startup_time * adc_clk_khz / 1000) - 1, 8) / 8;
806 static u32 calc_startup_ticks_9x5(u32 startup_time, u32 adc_clk_khz)
809 * For sama5d3x and at91sam9x5, the formula changes to:
810 * Startup Time = <lookup_table_value> / ADC Clock
812 static const int startup_lookup[] = {
818 int i, size = ARRAY_SIZE(startup_lookup);
821 ticks = startup_time * adc_clk_khz / 1000;
822 for (i = 0; i < size; i++)
823 if (ticks < startup_lookup[i])
828 /* Reach the end of lookup table */
834 static const struct of_device_id at91_adc_dt_ids[];
836 static int at91_adc_probe_dt_ts(struct device_node *node,
837 struct at91_adc_state *st, struct device *dev)
842 ret = of_property_read_u32(node, "atmel,adc-ts-wires", &prop);
844 dev_info(dev, "ADC Touch screen is disabled.\n");
851 st->touchscreen_type = prop;
854 dev_err(dev, "Unsupported number of touchscreen wires (%d). Should be 4 or 5.\n", prop);
858 if (!st->caps->has_tsmr)
861 of_property_read_u32(node, "atmel,adc-ts-pressure-threshold", &prop);
862 st->ts_pressure_threshold = prop;
863 if (st->ts_pressure_threshold) {
866 dev_err(dev, "Invalid pressure threshold for the touchscreen\n");
871 static int at91_adc_probe_dt(struct at91_adc_state *st,
872 struct platform_device *pdev)
874 struct iio_dev *idev = iio_priv_to_dev(st);
875 struct device_node *node = pdev->dev.of_node;
876 struct device_node *trig_node;
883 st->caps = (struct at91_adc_caps *)
884 of_match_device(at91_adc_dt_ids, &pdev->dev)->data;
886 st->use_external = of_property_read_bool(node, "atmel,adc-use-external-triggers");
888 if (of_property_read_u32(node, "atmel,adc-channels-used", &prop)) {
889 dev_err(&idev->dev, "Missing adc-channels-used property in the DT.\n");
893 st->channels_mask = prop;
895 st->sleep_mode = of_property_read_bool(node, "atmel,adc-sleep-mode");
897 if (of_property_read_u32(node, "atmel,adc-startup-time", &prop)) {
898 dev_err(&idev->dev, "Missing adc-startup-time property in the DT.\n");
902 st->startup_time = prop;
905 of_property_read_u32(node, "atmel,adc-sample-hold-time", &prop);
906 st->sample_hold_time = prop;
908 if (of_property_read_u32(node, "atmel,adc-vref", &prop)) {
909 dev_err(&idev->dev, "Missing adc-vref property in the DT.\n");
915 ret = at91_adc_of_get_resolution(st, pdev);
919 st->registers = &st->caps->registers;
920 st->num_channels = st->caps->num_channels;
921 st->trigger_number = of_get_child_count(node);
922 st->trigger_list = devm_kzalloc(&idev->dev, st->trigger_number *
923 sizeof(struct at91_adc_trigger),
925 if (!st->trigger_list) {
926 dev_err(&idev->dev, "Could not allocate trigger list memory.\n");
931 for_each_child_of_node(node, trig_node) {
932 struct at91_adc_trigger *trig = st->trigger_list + i;
935 if (of_property_read_string(trig_node, "trigger-name", &name)) {
936 dev_err(&idev->dev, "Missing trigger-name property in the DT.\n");
942 if (of_property_read_u32(trig_node, "trigger-value", &prop)) {
943 dev_err(&idev->dev, "Missing trigger-value property in the DT.\n");
948 trig->is_external = of_property_read_bool(trig_node, "trigger-external");
952 /* Check if touchscreen is supported. */
953 if (st->caps->has_ts)
954 return at91_adc_probe_dt_ts(node, st, &idev->dev);
956 dev_info(&idev->dev, "not support touchscreen in the adc compatible string.\n");
964 static int at91_adc_probe_pdata(struct at91_adc_state *st,
965 struct platform_device *pdev)
967 struct at91_adc_data *pdata = pdev->dev.platform_data;
972 st->caps = (struct at91_adc_caps *)
973 platform_get_device_id(pdev)->driver_data;
975 st->use_external = pdata->use_external_triggers;
976 st->vref_mv = pdata->vref;
977 st->channels_mask = pdata->channels_used;
978 st->num_channels = st->caps->num_channels;
979 st->startup_time = pdata->startup_time;
980 st->trigger_number = pdata->trigger_number;
981 st->trigger_list = pdata->trigger_list;
982 st->registers = &st->caps->registers;
983 st->touchscreen_type = pdata->touchscreen_type;
988 static const struct iio_info at91_adc_info = {
989 .driver_module = THIS_MODULE,
990 .read_raw = &at91_adc_read_raw,
993 /* Touchscreen related functions */
994 static int atmel_ts_open(struct input_dev *dev)
996 struct at91_adc_state *st = input_get_drvdata(dev);
998 if (st->caps->has_tsmr)
999 at91_adc_writel(st, AT91_ADC_IER, AT91_ADC_IER_PEN);
1001 at91_adc_writel(st, AT91_ADC_IER, AT91RL_ADC_IER_PEN);
1005 static void atmel_ts_close(struct input_dev *dev)
1007 struct at91_adc_state *st = input_get_drvdata(dev);
1009 if (st->caps->has_tsmr)
1010 at91_adc_writel(st, AT91_ADC_IDR, AT91_ADC_IER_PEN);
1012 at91_adc_writel(st, AT91_ADC_IDR, AT91RL_ADC_IER_PEN);
1015 static int at91_ts_hw_init(struct at91_adc_state *st, u32 adc_clk_khz)
1017 struct iio_dev *idev = iio_priv_to_dev(st);
1022 /* a Pen Detect Debounce Time is necessary for the ADC Touch to avoid
1024 * The formula is : Pen Detect Debounce Time = (2 ^ pendbc) / ADCClock
1026 st->ts_pendbc = round_up(TOUCH_PEN_DETECT_DEBOUNCE_US * adc_clk_khz /
1029 while (st->ts_pendbc >> ++i)
1030 ; /* Empty! Find the shift offset */
1031 if (abs(st->ts_pendbc - (1 << i)) < abs(st->ts_pendbc - (1 << (i - 1))))
1034 st->ts_pendbc = i - 1;
1036 if (!st->caps->has_tsmr) {
1037 reg = at91_adc_readl(st, AT91_ADC_MR);
1038 reg |= AT91_ADC_TSAMOD_TS_ONLY_MODE | AT91_ADC_PENDET;
1040 reg |= AT91_ADC_PENDBC_(st->ts_pendbc) & AT91_ADC_PENDBC;
1041 at91_adc_writel(st, AT91_ADC_MR, reg);
1043 reg = AT91_ADC_TSR_SHTIM_(TOUCH_SHTIM) & AT91_ADC_TSR_SHTIM;
1044 at91_adc_writel(st, AT91_ADC_TSR, reg);
1046 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US_RL *
1047 adc_clk_khz / 1000) - 1, 1);
1052 /* Touchscreen Switches Closure time needed for allowing the value to
1054 * Switch Closure Time = (TSSCTIM * 4) ADCClock periods
1056 tssctim = DIV_ROUND_UP(TOUCH_SCTIM_US * adc_clk_khz / 1000, 4);
1057 dev_dbg(&idev->dev, "adc_clk at: %d KHz, tssctim at: %d\n",
1058 adc_clk_khz, tssctim);
1060 if (st->touchscreen_type == ATMEL_ADC_TOUCHSCREEN_4WIRE)
1061 reg = AT91_ADC_TSMR_TSMODE_4WIRE_PRESS;
1063 reg = AT91_ADC_TSMR_TSMODE_5WIRE;
1065 reg |= AT91_ADC_TSMR_SCTIM_(tssctim) & AT91_ADC_TSMR_SCTIM;
1066 reg |= AT91_ADC_TSMR_TSAV_(st->caps->ts_filter_average)
1067 & AT91_ADC_TSMR_TSAV;
1068 reg |= AT91_ADC_TSMR_PENDBC_(st->ts_pendbc) & AT91_ADC_TSMR_PENDBC;
1069 reg |= AT91_ADC_TSMR_NOTSDMA;
1070 reg |= AT91_ADC_TSMR_PENDET_ENA;
1071 reg |= 0x03 << 8; /* TSFREQ, needs to be bigger than TSAV */
1073 at91_adc_writel(st, AT91_ADC_TSMR, reg);
1075 /* Change adc internal resistor value for better pen detection,
1076 * default value is 100 kOhm.
1077 * 0 = 200 kOhm, 1 = 150 kOhm, 2 = 100 kOhm, 3 = 50 kOhm
1078 * option only available on ES2 and higher
1080 at91_adc_writel(st, AT91_ADC_ACR, st->caps->ts_pen_detect_sensitivity
1081 & AT91_ADC_ACR_PENDETSENS);
1083 /* Sample Period Time = (TRGPER + 1) / ADCClock */
1084 st->ts_sample_period_val = round_up((TOUCH_SAMPLE_PERIOD_US *
1085 adc_clk_khz / 1000) - 1, 1);
1090 static int at91_ts_register(struct at91_adc_state *st,
1091 struct platform_device *pdev)
1093 struct input_dev *input;
1094 struct iio_dev *idev = iio_priv_to_dev(st);
1097 input = input_allocate_device();
1099 dev_err(&idev->dev, "Failed to allocate TS device!\n");
1103 input->name = DRIVER_NAME;
1104 input->id.bustype = BUS_HOST;
1105 input->dev.parent = &pdev->dev;
1106 input->open = atmel_ts_open;
1107 input->close = atmel_ts_close;
1109 __set_bit(EV_ABS, input->evbit);
1110 __set_bit(EV_KEY, input->evbit);
1111 __set_bit(BTN_TOUCH, input->keybit);
1112 if (st->caps->has_tsmr) {
1113 input_set_abs_params(input, ABS_X, 0, (1 << MAX_POS_BITS) - 1,
1115 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_POS_BITS) - 1,
1117 input_set_abs_params(input, ABS_PRESSURE, 0, 0xffffff, 0, 0);
1119 if (st->touchscreen_type != ATMEL_ADC_TOUCHSCREEN_4WIRE) {
1121 "This touchscreen controller only support 4 wires\n");
1126 input_set_abs_params(input, ABS_X, 0, (1 << MAX_RLPOS_BITS) - 1,
1128 input_set_abs_params(input, ABS_Y, 0, (1 << MAX_RLPOS_BITS) - 1,
1132 st->ts_input = input;
1133 input_set_drvdata(input, st);
1135 ret = input_register_device(input);
1142 input_free_device(st->ts_input);
1146 static void at91_ts_unregister(struct at91_adc_state *st)
1148 input_unregister_device(st->ts_input);
1151 static int at91_adc_probe(struct platform_device *pdev)
1153 unsigned int prsc, mstrclk, ticks, adc_clk, adc_clk_khz, shtim;
1155 struct iio_dev *idev;
1156 struct at91_adc_state *st;
1157 struct resource *res;
1160 idev = devm_iio_device_alloc(&pdev->dev, sizeof(struct at91_adc_state));
1164 st = iio_priv(idev);
1166 if (pdev->dev.of_node)
1167 ret = at91_adc_probe_dt(st, pdev);
1169 ret = at91_adc_probe_pdata(st, pdev);
1172 dev_err(&pdev->dev, "No platform data available.\n");
1176 platform_set_drvdata(pdev, idev);
1178 idev->dev.parent = &pdev->dev;
1179 idev->name = dev_name(&pdev->dev);
1180 idev->modes = INDIO_DIRECT_MODE;
1181 idev->info = &at91_adc_info;
1183 st->irq = platform_get_irq(pdev, 0);
1185 dev_err(&pdev->dev, "No IRQ ID is designated\n");
1189 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1191 st->reg_base = devm_ioremap_resource(&pdev->dev, res);
1192 if (IS_ERR(st->reg_base)) {
1193 return PTR_ERR(st->reg_base);
1197 * Disable all IRQs before setting up the handler
1199 at91_adc_writel(st, AT91_ADC_CR, AT91_ADC_SWRST);
1200 at91_adc_writel(st, AT91_ADC_IDR, 0xFFFFFFFF);
1202 if (st->caps->has_tsmr)
1203 ret = request_irq(st->irq, at91_adc_9x5_interrupt, 0,
1204 pdev->dev.driver->name, idev);
1206 ret = request_irq(st->irq, at91_adc_rl_interrupt, 0,
1207 pdev->dev.driver->name, idev);
1209 dev_err(&pdev->dev, "Failed to allocate IRQ.\n");
1213 st->clk = devm_clk_get(&pdev->dev, "adc_clk");
1214 if (IS_ERR(st->clk)) {
1215 dev_err(&pdev->dev, "Failed to get the clock.\n");
1216 ret = PTR_ERR(st->clk);
1217 goto error_free_irq;
1220 ret = clk_prepare_enable(st->clk);
1223 "Could not prepare or enable the clock.\n");
1224 goto error_free_irq;
1227 st->adc_clk = devm_clk_get(&pdev->dev, "adc_op_clk");
1228 if (IS_ERR(st->adc_clk)) {
1229 dev_err(&pdev->dev, "Failed to get the ADC clock.\n");
1230 ret = PTR_ERR(st->adc_clk);
1231 goto error_disable_clk;
1234 ret = clk_prepare_enable(st->adc_clk);
1237 "Could not prepare or enable the ADC clock.\n");
1238 goto error_disable_clk;
1242 * Prescaler rate computation using the formula from the Atmel's
1243 * datasheet : ADC Clock = MCK / ((Prescaler + 1) * 2), ADC Clock being
1244 * specified by the electrical characteristics of the board.
1246 mstrclk = clk_get_rate(st->clk);
1247 adc_clk = clk_get_rate(st->adc_clk);
1248 adc_clk_khz = adc_clk / 1000;
1250 dev_dbg(&pdev->dev, "Master clock is set as: %d Hz, adc_clk should set as: %d Hz\n",
1253 prsc = (mstrclk / (2 * adc_clk)) - 1;
1255 if (!st->startup_time) {
1256 dev_err(&pdev->dev, "No startup time available.\n");
1258 goto error_disable_adc_clk;
1260 ticks = (*st->caps->calc_startup_ticks)(st->startup_time, adc_clk_khz);
1263 * a minimal Sample and Hold Time is necessary for the ADC to guarantee
1264 * the best converted final value between two channels selection
1265 * The formula thus is : Sample and Hold Time = (shtim + 1) / ADCClock
1267 if (st->sample_hold_time > 0)
1268 shtim = round_up((st->sample_hold_time * adc_clk_khz / 1000)
1273 reg = AT91_ADC_PRESCAL_(prsc) & st->registers->mr_prescal_mask;
1274 reg |= AT91_ADC_STARTUP_(ticks) & st->registers->mr_startup_mask;
1276 reg |= AT91_ADC_LOWRES;
1278 reg |= AT91_ADC_SLEEP;
1279 reg |= AT91_ADC_SHTIM_(shtim) & AT91_ADC_SHTIM;
1280 at91_adc_writel(st, AT91_ADC_MR, reg);
1282 /* Setup the ADC channels available on the board */
1283 ret = at91_adc_channel_init(idev);
1285 dev_err(&pdev->dev, "Couldn't initialize the channels.\n");
1286 goto error_disable_adc_clk;
1289 init_waitqueue_head(&st->wq_data_avail);
1290 mutex_init(&st->lock);
1293 * Since touch screen will set trigger register as period trigger. So
1294 * when touch screen is enabled, then we have to disable hardware
1295 * trigger for classic adc.
1297 if (!st->touchscreen_type) {
1298 ret = at91_adc_buffer_init(idev);
1300 dev_err(&pdev->dev, "Couldn't initialize the buffer.\n");
1301 goto error_disable_adc_clk;
1304 ret = at91_adc_trigger_init(idev);
1306 dev_err(&pdev->dev, "Couldn't setup the triggers.\n");
1307 at91_adc_buffer_remove(idev);
1308 goto error_disable_adc_clk;
1311 ret = at91_ts_register(st, pdev);
1313 goto error_disable_adc_clk;
1315 at91_ts_hw_init(st, adc_clk_khz);
1318 ret = iio_device_register(idev);
1320 dev_err(&pdev->dev, "Couldn't register the device.\n");
1321 goto error_iio_device_register;
1326 error_iio_device_register:
1327 if (!st->touchscreen_type) {
1328 at91_adc_trigger_remove(idev);
1329 at91_adc_buffer_remove(idev);
1331 at91_ts_unregister(st);
1333 error_disable_adc_clk:
1334 clk_disable_unprepare(st->adc_clk);
1336 clk_disable_unprepare(st->clk);
1338 free_irq(st->irq, idev);
1342 static int at91_adc_remove(struct platform_device *pdev)
1344 struct iio_dev *idev = platform_get_drvdata(pdev);
1345 struct at91_adc_state *st = iio_priv(idev);
1347 iio_device_unregister(idev);
1348 if (!st->touchscreen_type) {
1349 at91_adc_trigger_remove(idev);
1350 at91_adc_buffer_remove(idev);
1352 at91_ts_unregister(st);
1354 clk_disable_unprepare(st->adc_clk);
1355 clk_disable_unprepare(st->clk);
1356 free_irq(st->irq, idev);
1361 #ifdef CONFIG_PM_SLEEP
1362 static int at91_adc_suspend(struct device *dev)
1364 struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1365 struct at91_adc_state *st = iio_priv(idev);
1367 pinctrl_pm_select_sleep_state(dev);
1368 clk_disable_unprepare(st->clk);
1373 static int at91_adc_resume(struct device *dev)
1375 struct iio_dev *idev = platform_get_drvdata(to_platform_device(dev));
1376 struct at91_adc_state *st = iio_priv(idev);
1378 clk_prepare_enable(st->clk);
1379 pinctrl_pm_select_default_state(dev);
1385 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
1387 static struct at91_adc_caps at91sam9260_caps = {
1388 .calc_startup_ticks = calc_startup_ticks_9260,
1391 .channel_base = AT91_ADC_CHR(0),
1392 .drdy_mask = AT91_ADC_DRDY,
1393 .status_register = AT91_ADC_SR,
1394 .trigger_register = AT91_ADC_TRGR_9260,
1395 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1396 .mr_startup_mask = AT91_ADC_STARTUP_9260,
1400 static struct at91_adc_caps at91sam9rl_caps = {
1402 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1405 .channel_base = AT91_ADC_CHR(0),
1406 .drdy_mask = AT91_ADC_DRDY,
1407 .status_register = AT91_ADC_SR,
1408 .trigger_register = AT91_ADC_TRGR_9G45,
1409 .mr_prescal_mask = AT91_ADC_PRESCAL_9260,
1410 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1414 static struct at91_adc_caps at91sam9g45_caps = {
1416 .calc_startup_ticks = calc_startup_ticks_9260, /* same as 9260 */
1419 .channel_base = AT91_ADC_CHR(0),
1420 .drdy_mask = AT91_ADC_DRDY,
1421 .status_register = AT91_ADC_SR,
1422 .trigger_register = AT91_ADC_TRGR_9G45,
1423 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1424 .mr_startup_mask = AT91_ADC_STARTUP_9G45,
1428 static struct at91_adc_caps at91sam9x5_caps = {
1431 .ts_filter_average = 3,
1432 .ts_pen_detect_sensitivity = 2,
1433 .calc_startup_ticks = calc_startup_ticks_9x5,
1436 .channel_base = AT91_ADC_CDR0_9X5,
1437 .drdy_mask = AT91_ADC_SR_DRDY_9X5,
1438 .status_register = AT91_ADC_SR_9X5,
1439 .trigger_register = AT91_ADC_TRGR_9X5,
1440 /* prescal mask is same as 9G45 */
1441 .mr_prescal_mask = AT91_ADC_PRESCAL_9G45,
1442 .mr_startup_mask = AT91_ADC_STARTUP_9X5,
1446 static const struct of_device_id at91_adc_dt_ids[] = {
1447 { .compatible = "atmel,at91sam9260-adc", .data = &at91sam9260_caps },
1448 { .compatible = "atmel,at91sam9rl-adc", .data = &at91sam9rl_caps },
1449 { .compatible = "atmel,at91sam9g45-adc", .data = &at91sam9g45_caps },
1450 { .compatible = "atmel,at91sam9x5-adc", .data = &at91sam9x5_caps },
1453 MODULE_DEVICE_TABLE(of, at91_adc_dt_ids);
1455 static const struct platform_device_id at91_adc_ids[] = {
1457 .name = "at91sam9260-adc",
1458 .driver_data = (unsigned long)&at91sam9260_caps,
1460 .name = "at91sam9rl-adc",
1461 .driver_data = (unsigned long)&at91sam9rl_caps,
1463 .name = "at91sam9g45-adc",
1464 .driver_data = (unsigned long)&at91sam9g45_caps,
1466 .name = "at91sam9x5-adc",
1467 .driver_data = (unsigned long)&at91sam9x5_caps,
1472 MODULE_DEVICE_TABLE(platform, at91_adc_ids);
1474 static struct platform_driver at91_adc_driver = {
1475 .probe = at91_adc_probe,
1476 .remove = at91_adc_remove,
1477 .id_table = at91_adc_ids,
1479 .name = DRIVER_NAME,
1480 .of_match_table = of_match_ptr(at91_adc_dt_ids),
1481 .pm = &at91_adc_pm_ops,
1485 module_platform_driver(at91_adc_driver);
1487 MODULE_LICENSE("GPL");
1488 MODULE_DESCRIPTION("Atmel AT91 ADC Driver");
1489 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");