drivers/iio/adc/at91-sama5d2_adc.c

   1 /*
   2  * Atmel ADC driver for SAMA5D2 devices and compatible.
   3  *
   4  * Copyright (C) 2015 Atmel,
   5  *               2015 Ludovic Desroches <ludovic.desroches@atmel.com>
   6  *
   7  * This software is licensed under the terms of the GNU General Public
   8  * License version 2, as published by the Free Software Foundation, and
   9  * may be copied, distributed, and modified under those terms.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/bitops.h>
  18 #include <linux/clk.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/of_device.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/sched.h>
  25 #include <linux/wait.h>
  26 #include <linux/iio/iio.h>
  27 #include <linux/iio/sysfs.h>
  28 #include <linux/iio/buffer.h>
  29 #include <linux/iio/trigger.h>
  30 #include <linux/iio/trigger_consumer.h>
  31 #include <linux/iio/triggered_buffer.h>
  32 #include <linux/pinctrl/consumer.h>
  33 #include <linux/regulator/consumer.h>
  34
  35 /* Control Register */
  36 #define AT91_SAMA5D2_CR         0x00
  37 /* Software Reset */
  38 #define AT91_SAMA5D2_CR_SWRST           BIT(0)
  39 /* Start Conversion */
  40 #define AT91_SAMA5D2_CR_START           BIT(1)
  41 /* Touchscreen Calibration */
  42 #define AT91_SAMA5D2_CR_TSCALIB         BIT(2)
  43 /* Comparison Restart */
  44 #define AT91_SAMA5D2_CR_CMPRST          BIT(4)
  45
  46 /* Mode Register */
  47 #define AT91_SAMA5D2_MR         0x04
  48 /* Trigger Selection */
  49 #define AT91_SAMA5D2_MR_TRGSEL(v)       ((v) << 1)
  50 /* ADTRG */
  51 #define AT91_SAMA5D2_MR_TRGSEL_TRIG0    0
  52 /* TIOA0 */
  53 #define AT91_SAMA5D2_MR_TRGSEL_TRIG1    1
  54 /* TIOA1 */
  55 #define AT91_SAMA5D2_MR_TRGSEL_TRIG2    2
  56 /* TIOA2 */
  57 #define AT91_SAMA5D2_MR_TRGSEL_TRIG3    3
  58 /* PWM event line 0 */
  59 #define AT91_SAMA5D2_MR_TRGSEL_TRIG4    4
  60 /* PWM event line 1 */
  61 #define AT91_SAMA5D2_MR_TRGSEL_TRIG5    5
  62 /* TIOA3 */
  63 #define AT91_SAMA5D2_MR_TRGSEL_TRIG6    6
  64 /* RTCOUT0 */
  65 #define AT91_SAMA5D2_MR_TRGSEL_TRIG7    7
  66 /* Sleep Mode */
  67 #define AT91_SAMA5D2_MR_SLEEP           BIT(5)
  68 /* Fast Wake Up */
  69 #define AT91_SAMA5D2_MR_FWUP            BIT(6)
  70 /* Prescaler Rate Selection */
  71 #define AT91_SAMA5D2_MR_PRESCAL(v)      ((v) << AT91_SAMA5D2_MR_PRESCAL_OFFSET)
  72 #define AT91_SAMA5D2_MR_PRESCAL_OFFSET  8
  73 #define AT91_SAMA5D2_MR_PRESCAL_MAX     0xff
  74 #define AT91_SAMA5D2_MR_PRESCAL_MASK    GENMASK(15, 8)
  75 /* Startup Time */
  76 #define AT91_SAMA5D2_MR_STARTUP(v)      ((v) << 16)
  77 #define AT91_SAMA5D2_MR_STARTUP_MASK    GENMASK(19, 16)
  78 /* Analog Change */
  79 #define AT91_SAMA5D2_MR_ANACH           BIT(23)
  80 /* Tracking Time */
  81 #define AT91_SAMA5D2_MR_TRACKTIM(v)     ((v) << 24)
  82 #define AT91_SAMA5D2_MR_TRACKTIM_MAX    0xff
  83 /* Transfer Time */
  84 #define AT91_SAMA5D2_MR_TRANSFER(v)     ((v) << 28)
  85 #define AT91_SAMA5D2_MR_TRANSFER_MAX    0x3
  86 /* Use Sequence Enable */
  87 #define AT91_SAMA5D2_MR_USEQ            BIT(31)
  88
  89 /* Channel Sequence Register 1 */
  90 #define AT91_SAMA5D2_SEQR1      0x08
  91 /* Channel Sequence Register 2 */
  92 #define AT91_SAMA5D2_SEQR2      0x0c
  93 /* Channel Enable Register */
  94 #define AT91_SAMA5D2_CHER       0x10
  95 /* Channel Disable Register */
  96 #define AT91_SAMA5D2_CHDR       0x14
  97 /* Channel Status Register */
  98 #define AT91_SAMA5D2_CHSR       0x18
  99 /* Last Converted Data Register */
 100 #define AT91_SAMA5D2_LCDR       0x20
 101 /* Interrupt Enable Register */
 102 #define AT91_SAMA5D2_IER        0x24
 103 /* Interrupt Disable Register */
 104 #define AT91_SAMA5D2_IDR        0x28
 105 /* Interrupt Mask Register */
 106 #define AT91_SAMA5D2_IMR        0x2c
 107 /* Interrupt Status Register */
 108 #define AT91_SAMA5D2_ISR        0x30
 109 /* Last Channel Trigger Mode Register */
 110 #define AT91_SAMA5D2_LCTMR      0x34
 111 /* Last Channel Compare Window Register */
 112 #define AT91_SAMA5D2_LCCWR      0x38
 113 /* Overrun Status Register */
 114 #define AT91_SAMA5D2_OVER       0x3c
 115 /* Extended Mode Register */
 116 #define AT91_SAMA5D2_EMR        0x40
 117 /* Compare Window Register */
 118 #define AT91_SAMA5D2_CWR        0x44
 119 /* Channel Gain Register */
 120 #define AT91_SAMA5D2_CGR        0x48
 121
 122 /* Channel Offset Register */
 123 #define AT91_SAMA5D2_COR        0x4c
 124 #define AT91_SAMA5D2_COR_DIFF_OFFSET    16
 125
 126 /* Channel Data Register 0 */
 127 #define AT91_SAMA5D2_CDR0       0x50
 128 /* Analog Control Register */
 129 #define AT91_SAMA5D2_ACR        0x94
 130 /* Touchscreen Mode Register */
 131 #define AT91_SAMA5D2_TSMR       0xb0
 132 /* Touchscreen X Position Register */
 133 #define AT91_SAMA5D2_XPOSR      0xb4
 134 /* Touchscreen Y Position Register */
 135 #define AT91_SAMA5D2_YPOSR      0xb8
 136 /* Touchscreen Pressure Register */
 137 #define AT91_SAMA5D2_PRESSR     0xbc
 138 /* Trigger Register */
 139 #define AT91_SAMA5D2_TRGR       0xc0
 140 /* Mask for TRGMOD field of TRGR register */
 141 #define AT91_SAMA5D2_TRGR_TRGMOD_MASK GENMASK(2, 0)
 142 /* No trigger, only software trigger can start conversions */
 143 #define AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER 0
 144 /* Trigger Mode external trigger rising edge */
 145 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE 1
 146 /* Trigger Mode external trigger falling edge */
 147 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL 2
 148 /* Trigger Mode external trigger any edge */
 149 #define AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY 3
 150
 151 /* Correction Select Register */
 152 #define AT91_SAMA5D2_COSR       0xd0
 153 /* Correction Value Register */
 154 #define AT91_SAMA5D2_CVR        0xd4
 155 /* Channel Error Correction Register */
 156 #define AT91_SAMA5D2_CECR       0xd8
 157 /* Write Protection Mode Register */
 158 #define AT91_SAMA5D2_WPMR       0xe4
 159 /* Write Protection Status Register */
 160 #define AT91_SAMA5D2_WPSR       0xe8
 161 /* Version Register */
 162 #define AT91_SAMA5D2_VERSION    0xfc
 163
 164 #define AT91_SAMA5D2_HW_TRIG_CNT 3
 165 #define AT91_SAMA5D2_SINGLE_CHAN_CNT 12
 166 #define AT91_SAMA5D2_DIFF_CHAN_CNT 6
 167
 168 /*
 169  * Maximum number of bytes to hold conversion from all channels
 170  * plus the timestamp
 171  */
 172 #define AT91_BUFFER_MAX_BYTES ((AT91_SAMA5D2_SINGLE_CHAN_CNT +          \
 173                                 AT91_SAMA5D2_DIFF_CHAN_CNT) * 2 + 8)
 174
 175 #define AT91_BUFFER_MAX_HWORDS (AT91_BUFFER_MAX_BYTES / 2)
 176
 177 #define AT91_SAMA5D2_CHAN_SINGLE(num, addr)                             \
 178         {                                                               \
 179                 .type = IIO_VOLTAGE,                                    \
 180                 .channel = num,                                         \
 181                 .address = addr,                                        \
 182                 .scan_index = num,                                      \
 183                 .scan_type = {                                          \
 184                         .sign = 'u',                                    \
 185                         .realbits = 12,                                 \
 186                         .storagebits = 16,                              \
 187                 },                                                      \
 188                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 189                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 190                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 191                 .datasheet_name = "CH"#num,                             \
 192                 .indexed = 1,                                           \
 193         }
 194
 195 #define AT91_SAMA5D2_CHAN_DIFF(num, num2, addr)                         \
 196         {                                                               \
 197                 .type = IIO_VOLTAGE,                                    \
 198                 .differential = 1,                                      \
 199                 .channel = num,                                         \
 200                 .channel2 = num2,                                       \
 201                 .address = addr,                                        \
 202                 .scan_index = num + AT91_SAMA5D2_SINGLE_CHAN_CNT,       \
 203                 .scan_type = {                                          \
 204                         .sign = 's',                                    \
 205                         .realbits = 12,                                 \
 206                         .storagebits = 16,                              \
 207                 },                                                      \
 208                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),           \
 209                 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE),   \
 210                 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SAMP_FREQ),\
 211                 .datasheet_name = "CH"#num"-CH"#num2,                   \
 212                 .indexed = 1,                                           \
 213         }
 214
 215 #define at91_adc_readl(st, reg)         readl_relaxed(st->base + reg)
 216 #define at91_adc_writel(st, reg, val)   writel_relaxed(val, st->base + reg)
 217
 218 struct at91_adc_soc_info {
 219         unsigned                        startup_time;
 220         unsigned                        min_sample_rate;
 221         unsigned                        max_sample_rate;
 222 };
 223
 224 struct at91_adc_trigger {
 225         char                            *name;
 226         unsigned int                    trgmod_value;
 227         unsigned int                    edge_type;
 228         bool                            hw_trig;
 229 };
 230
 231 struct at91_adc_state {
 232         void __iomem                    *base;
 233         int                             irq;
 234         struct clk                      *per_clk;
 235         struct regulator                *reg;
 236         struct regulator                *vref;
 237         int                             vref_uv;
 238         struct iio_trigger              *trig;
 239         const struct at91_adc_trigger   *selected_trig;
 240         const struct iio_chan_spec      *chan;
 241         bool                            conversion_done;
 242         u32                             conversion_value;
 243         struct at91_adc_soc_info        soc_info;
 244         wait_queue_head_t               wq_data_available;
 245         u16                             buffer[AT91_BUFFER_MAX_HWORDS];
 246         /*
 247          * lock to prevent concurrent 'single conversion' requests through
 248          * sysfs.
 249          */
 250         struct mutex                    lock;
 251 };
 252
 253 static const struct at91_adc_trigger at91_adc_trigger_list[] = {
 254         {
 255                 .name = "external_rising",
 256                 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_RISE,
 257                 .edge_type = IRQ_TYPE_EDGE_RISING,
 258                 .hw_trig = true,
 259         },
 260         {
 261                 .name = "external_falling",
 262                 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_FALL,
 263                 .edge_type = IRQ_TYPE_EDGE_FALLING,
 264                 .hw_trig = true,
 265         },
 266         {
 267                 .name = "external_any",
 268                 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_EXT_TRIG_ANY,
 269                 .edge_type = IRQ_TYPE_EDGE_BOTH,
 270                 .hw_trig = true,
 271         },
 272         {
 273                 .name = "software",
 274                 .trgmod_value = AT91_SAMA5D2_TRGR_TRGMOD_NO_TRIGGER,
 275                 .edge_type = IRQ_TYPE_NONE,
 276                 .hw_trig = false,
 277         },
 278 };
 279
 280 static const struct iio_chan_spec at91_adc_channels[] = {
 281         AT91_SAMA5D2_CHAN_SINGLE(0, 0x50),
 282         AT91_SAMA5D2_CHAN_SINGLE(1, 0x54),
 283         AT91_SAMA5D2_CHAN_SINGLE(2, 0x58),
 284         AT91_SAMA5D2_CHAN_SINGLE(3, 0x5c),
 285         AT91_SAMA5D2_CHAN_SINGLE(4, 0x60),
 286         AT91_SAMA5D2_CHAN_SINGLE(5, 0x64),
 287         AT91_SAMA5D2_CHAN_SINGLE(6, 0x68),
 288         AT91_SAMA5D2_CHAN_SINGLE(7, 0x6c),
 289         AT91_SAMA5D2_CHAN_SINGLE(8, 0x70),
 290         AT91_SAMA5D2_CHAN_SINGLE(9, 0x74),
 291         AT91_SAMA5D2_CHAN_SINGLE(10, 0x78),
 292         AT91_SAMA5D2_CHAN_SINGLE(11, 0x7c),
 293         AT91_SAMA5D2_CHAN_DIFF(0, 1, 0x50),
 294         AT91_SAMA5D2_CHAN_DIFF(2, 3, 0x58),
 295         AT91_SAMA5D2_CHAN_DIFF(4, 5, 0x60),
 296         AT91_SAMA5D2_CHAN_DIFF(6, 7, 0x68),
 297         AT91_SAMA5D2_CHAN_DIFF(8, 9, 0x70),
 298         AT91_SAMA5D2_CHAN_DIFF(10, 11, 0x78),
 299         IIO_CHAN_SOFT_TIMESTAMP(AT91_SAMA5D2_SINGLE_CHAN_CNT
 300                                 + AT91_SAMA5D2_DIFF_CHAN_CNT + 1),
 301 };
 302
 303 static int at91_adc_chan_xlate(struct iio_dev *indio_dev, int chan)
 304 {
 305         int i;
 306
 307         for (i = 0; i < indio_dev->num_channels; i++) {
 308                 if (indio_dev->channels[i].scan_index == chan)
 309                         return i;
 310         }
 311         return -EINVAL;
 312 }
 313
 314 static inline struct iio_chan_spec const *
 315 at91_adc_chan_get(struct iio_dev *indio_dev, int chan)
 316 {
 317         int index = at91_adc_chan_xlate(indio_dev, chan);
 318
 319         if (index < 0)
 320                 return NULL;
 321         return indio_dev->channels + index;
 322 }
 323
 324 static int at91_adc_configure_trigger(struct iio_trigger *trig, bool state)
 325 {
 326         struct iio_dev *indio = iio_trigger_get_drvdata(trig);
 327         struct at91_adc_state *st = iio_priv(indio);
 328         u32 status = at91_adc_readl(st, AT91_SAMA5D2_TRGR);
 329         u8 bit;
 330
 331         /* clear TRGMOD */
 332         status &= ~AT91_SAMA5D2_TRGR_TRGMOD_MASK;
 333
 334         if (state)
 335                 status |= st->selected_trig->trgmod_value;
 336
 337         /* set/unset hw trigger */
 338         at91_adc_writel(st, AT91_SAMA5D2_TRGR, status);
 339
 340         for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
 341                 struct iio_chan_spec const *chan = at91_adc_chan_get(indio, bit);
 342                 u32 cor;
 343
 344                 if (!chan)
 345                         continue;
 346                 if (state) {
 347                         cor = at91_adc_readl(st, AT91_SAMA5D2_COR);
 348
 349                         if (chan->differential)
 350                                 cor |= (BIT(chan->channel) |
 351                                         BIT(chan->channel2)) <<
 352                                         AT91_SAMA5D2_COR_DIFF_OFFSET;
 353                         else
 354                                 cor &= ~(BIT(chan->channel) <<
 355                                        AT91_SAMA5D2_COR_DIFF_OFFSET);
 356
 357                         at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
 358                 }
 359
 360                 if (state) {
 361                         at91_adc_writel(st, AT91_SAMA5D2_CHER,
 362                                         BIT(chan->channel));
 363                         at91_adc_writel(st, AT91_SAMA5D2_IER,
 364                                         BIT(chan->channel));
 365                 } else {
 366                         at91_adc_writel(st, AT91_SAMA5D2_IDR,
 367                                         BIT(chan->channel));
 368                         at91_adc_writel(st, AT91_SAMA5D2_CHDR,
 369                                         BIT(chan->channel));
 370                 }
 371         }
 372
 373         return 0;
 374 }
 375
 376 static int at91_adc_reenable_trigger(struct iio_trigger *trig)
 377 {
 378         struct iio_dev *indio = iio_trigger_get_drvdata(trig);
 379         struct at91_adc_state *st = iio_priv(indio);
 380
 381         enable_irq(st->irq);
 382
 383         /* Needed to ACK the DRDY interruption */
 384         at91_adc_readl(st, AT91_SAMA5D2_LCDR);
 385         return 0;
 386 }
 387
 388 static const struct iio_trigger_ops at91_adc_trigger_ops = {
 389         .owner = THIS_MODULE,
 390         .set_trigger_state = &at91_adc_configure_trigger,
 391         .try_reenable = &at91_adc_reenable_trigger,
 392 };
 393
 394 static struct iio_trigger *at91_adc_allocate_trigger(struct iio_dev *indio,
 395                                                      char *trigger_name)
 396 {
 397         struct iio_trigger *trig;
 398         int ret;
 399
 400         trig = devm_iio_trigger_alloc(&indio->dev, "%s-dev%d-%s", indio->name,
 401                                       indio->id, trigger_name);
 402         if (!trig)
 403                 return NULL;
 404
 405         trig->dev.parent = indio->dev.parent;
 406         iio_trigger_set_drvdata(trig, indio);
 407         trig->ops = &at91_adc_trigger_ops;
 408
 409         ret = devm_iio_trigger_register(&indio->dev, trig);
 410         if (ret)
 411                 return ERR_PTR(ret);
 412
 413         return trig;
 414 }
 415
 416 static int at91_adc_trigger_init(struct iio_dev *indio)
 417 {
 418         struct at91_adc_state *st = iio_priv(indio);
 419
 420         st->trig = at91_adc_allocate_trigger(indio, st->selected_trig->name);
 421         if (IS_ERR(st->trig)) {
 422                 dev_err(&indio->dev,
 423                         "could not allocate trigger\n");
 424                 return PTR_ERR(st->trig);
 425         }
 426
 427         return 0;
 428 }
 429
 430 static irqreturn_t at91_adc_trigger_handler(int irq, void *p)
 431 {
 432         struct iio_poll_func *pf = p;
 433         struct iio_dev *indio = pf->indio_dev;
 434         struct at91_adc_state *st = iio_priv(indio);
 435         int i = 0;
 436         u8 bit;
 437
 438         for_each_set_bit(bit, indio->active_scan_mask, indio->num_channels) {
 439                 struct iio_chan_spec const *chan =
 440                                         at91_adc_chan_get(indio, bit);
 441
 442                 if (!chan)
 443                         continue;
 444                 st->buffer[i] = at91_adc_readl(st, chan->address);
 445                 i++;
 446         }
 447
 448         iio_push_to_buffers_with_timestamp(indio, st->buffer, pf->timestamp);
 449
 450         iio_trigger_notify_done(indio->trig);
 451
 452         return IRQ_HANDLED;
 453 }
 454
 455 static int at91_adc_buffer_init(struct iio_dev *indio)
 456 {
 457         return devm_iio_triggered_buffer_setup(&indio->dev, indio,
 458                         &iio_pollfunc_store_time,
 459                         &at91_adc_trigger_handler, NULL);
 460 }
 461
 462 static unsigned at91_adc_startup_time(unsigned startup_time_min,
 463                                       unsigned adc_clk_khz)
 464 {
 465         static const unsigned int startup_lookup[] = {
 466                   0,   8,  16,  24,
 467                  64,  80,  96, 112,
 468                 512, 576, 640, 704,
 469                 768, 832, 896, 960
 470                 };
 471         unsigned ticks_min, i;
 472
 473         /*
 474          * Since the adc frequency is checked before, there is no reason
 475          * to not meet the startup time constraint.
 476          */
 477
 478         ticks_min = startup_time_min * adc_clk_khz / 1000;
 479         for (i = 0; i < ARRAY_SIZE(startup_lookup); i++)
 480                 if (startup_lookup[i] > ticks_min)
 481                         break;
 482
 483         return i;
 484 }
 485
 486 static void at91_adc_setup_samp_freq(struct at91_adc_state *st, unsigned freq)
 487 {
 488         struct iio_dev *indio_dev = iio_priv_to_dev(st);
 489         unsigned f_per, prescal, startup, mr;
 490
 491         f_per = clk_get_rate(st->per_clk);
 492         prescal = (f_per / (2 * freq)) - 1;
 493
 494         startup = at91_adc_startup_time(st->soc_info.startup_time,
 495                                         freq / 1000);
 496
 497         mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
 498         mr &= ~(AT91_SAMA5D2_MR_STARTUP_MASK | AT91_SAMA5D2_MR_PRESCAL_MASK);
 499         mr |= AT91_SAMA5D2_MR_STARTUP(startup);
 500         mr |= AT91_SAMA5D2_MR_PRESCAL(prescal);
 501         at91_adc_writel(st, AT91_SAMA5D2_MR, mr);
 502
 503         dev_dbg(&indio_dev->dev, "freq: %u, startup: %u, prescal: %u\n",
 504                 freq, startup, prescal);
 505 }
 506
 507 static unsigned at91_adc_get_sample_freq(struct at91_adc_state *st)
 508 {
 509         unsigned f_adc, f_per = clk_get_rate(st->per_clk);
 510         unsigned mr, prescal;
 511
 512         mr = at91_adc_readl(st, AT91_SAMA5D2_MR);
 513         prescal = (mr >> AT91_SAMA5D2_MR_PRESCAL_OFFSET)
 514                   & AT91_SAMA5D2_MR_PRESCAL_MAX;
 515         f_adc = f_per / (2 * (prescal + 1));
 516
 517         return f_adc;
 518 }
 519
 520 static irqreturn_t at91_adc_interrupt(int irq, void *private)
 521 {
 522         struct iio_dev *indio = private;
 523         struct at91_adc_state *st = iio_priv(indio);
 524         u32 status = at91_adc_readl(st, AT91_SAMA5D2_ISR);
 525         u32 imr = at91_adc_readl(st, AT91_SAMA5D2_IMR);
 526
 527         if (!(status & imr))
 528                 return IRQ_NONE;
 529
 530         if (iio_buffer_enabled(indio)) {
 531                 disable_irq_nosync(irq);
 532                 iio_trigger_poll(indio->trig);
 533         } else {
 534                 st->conversion_value = at91_adc_readl(st, st->chan->address);
 535                 st->conversion_done = true;
 536                 wake_up_interruptible(&st->wq_data_available);
 537         }
 538         return IRQ_HANDLED;
 539 }
 540
 541 static int at91_adc_read_raw(struct iio_dev *indio_dev,
 542                              struct iio_chan_spec const *chan,
 543                              int *val, int *val2, long mask)
 544 {
 545         struct at91_adc_state *st = iio_priv(indio_dev);
 546         u32 cor = 0;
 547         int ret;
 548
 549         switch (mask) {
 550         case IIO_CHAN_INFO_RAW:
 551                 /* we cannot use software trigger if hw trigger enabled */
 552                 ret = iio_device_claim_direct_mode(indio_dev);
 553                 if (ret)
 554                         return ret;
 555
 556                 mutex_lock(&st->lock);
 557
 558                 st->chan = chan;
 559
 560                 if (chan->differential)
 561                         cor = (BIT(chan->channel) | BIT(chan->channel2)) <<
 562                               AT91_SAMA5D2_COR_DIFF_OFFSET;
 563
 564                 at91_adc_writel(st, AT91_SAMA5D2_COR, cor);
 565                 at91_adc_writel(st, AT91_SAMA5D2_CHER, BIT(chan->channel));
 566                 at91_adc_writel(st, AT91_SAMA5D2_IER, BIT(chan->channel));
 567                 at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_START);
 568
 569                 ret = wait_event_interruptible_timeout(st->wq_data_available,
 570                                                        st->conversion_done,
 571                                                        msecs_to_jiffies(1000));
 572                 if (ret == 0)
 573                         ret = -ETIMEDOUT;
 574
 575                 if (ret > 0) {
 576                         *val = st->conversion_value;
 577                         if (chan->scan_type.sign == 's')
 578                                 *val = sign_extend32(*val, 11);
 579                         ret = IIO_VAL_INT;
 580                         st->conversion_done = false;
 581                 }
 582
 583                 at91_adc_writel(st, AT91_SAMA5D2_IDR, BIT(chan->channel));
 584                 at91_adc_writel(st, AT91_SAMA5D2_CHDR, BIT(chan->channel));
 585
 586                 mutex_unlock(&st->lock);
 587
 588                 iio_device_release_direct_mode(indio_dev);
 589                 return ret;
 590
 591         case IIO_CHAN_INFO_SCALE:
 592                 *val = st->vref_uv / 1000;
 593                 if (chan->differential)
 594                         *val *= 2;
 595                 *val2 = chan->scan_type.realbits;
 596                 return IIO_VAL_FRACTIONAL_LOG2;
 597
 598         case IIO_CHAN_INFO_SAMP_FREQ:
 599                 *val = at91_adc_get_sample_freq(st);
 600                 return IIO_VAL_INT;
 601
 602         default:
 603                 return -EINVAL;
 604         }
 605 }
 606
 607 static int at91_adc_write_raw(struct iio_dev *indio_dev,
 608                               struct iio_chan_spec const *chan,
 609                               int val, int val2, long mask)
 610 {
 611         struct at91_adc_state *st = iio_priv(indio_dev);
 612
 613         if (mask != IIO_CHAN_INFO_SAMP_FREQ)
 614                 return -EINVAL;
 615
 616         if (val < st->soc_info.min_sample_rate ||
 617             val > st->soc_info.max_sample_rate)
 618                 return -EINVAL;
 619
 620         at91_adc_setup_samp_freq(st, val);
 621
 622         return 0;
 623 }
 624
 625 static const struct iio_info at91_adc_info = {
 626         .read_raw = &at91_adc_read_raw,
 627         .write_raw = &at91_adc_write_raw,
 628         .driver_module = THIS_MODULE,
 629 };
 630
 631 static void at91_adc_hw_init(struct at91_adc_state *st)
 632 {
 633         at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
 634         at91_adc_writel(st, AT91_SAMA5D2_IDR, 0xffffffff);
 635         /*
 636          * Transfer field must be set to 2 according to the datasheet and
 637          * allows different analog settings for each channel.
 638          */
 639         at91_adc_writel(st, AT91_SAMA5D2_MR,
 640                         AT91_SAMA5D2_MR_TRANSFER(2) | AT91_SAMA5D2_MR_ANACH);
 641
 642         at91_adc_setup_samp_freq(st, st->soc_info.min_sample_rate);
 643 }
 644
 645 static int at91_adc_probe(struct platform_device *pdev)
 646 {
 647         struct iio_dev *indio_dev;
 648         struct at91_adc_state *st;
 649         struct resource *res;
 650         int ret, i;
 651         u32 edge_type = IRQ_TYPE_NONE;
 652
 653         indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
 654         if (!indio_dev)
 655                 return -ENOMEM;
 656
 657         indio_dev->dev.parent = &pdev->dev;
 658         indio_dev->name = dev_name(&pdev->dev);
 659         indio_dev->modes = INDIO_DIRECT_MODE;
 660         indio_dev->info = &at91_adc_info;
 661         indio_dev->channels = at91_adc_channels;
 662         indio_dev->num_channels = ARRAY_SIZE(at91_adc_channels);
 663
 664         st = iio_priv(indio_dev);
 665
 666         ret = of_property_read_u32(pdev->dev.of_node,
 667                                    "atmel,min-sample-rate-hz",
 668                                    &st->soc_info.min_sample_rate);
 669         if (ret) {
 670                 dev_err(&pdev->dev,
 671                         "invalid or missing value for atmel,min-sample-rate-hz\n");
 672                 return ret;
 673         }
 674
 675         ret = of_property_read_u32(pdev->dev.of_node,
 676                                    "atmel,max-sample-rate-hz",
 677                                    &st->soc_info.max_sample_rate);
 678         if (ret) {
 679                 dev_err(&pdev->dev,
 680                         "invalid or missing value for atmel,max-sample-rate-hz\n");
 681                 return ret;
 682         }
 683
 684         ret = of_property_read_u32(pdev->dev.of_node, "atmel,startup-time-ms",
 685                                    &st->soc_info.startup_time);
 686         if (ret) {
 687                 dev_err(&pdev->dev,
 688                         "invalid or missing value for atmel,startup-time-ms\n");
 689                 return ret;
 690         }
 691
 692         ret = of_property_read_u32(pdev->dev.of_node,
 693                                    "atmel,trigger-edge-type", &edge_type);
 694         if (ret) {
 695                 dev_dbg(&pdev->dev,
 696                         "atmel,trigger-edge-type not specified, only software trigger available\n");
 697         }
 698
 699         st->selected_trig = NULL;
 700
 701         /* find the right trigger, or no trigger at all */
 702         for (i = 0; i < AT91_SAMA5D2_HW_TRIG_CNT + 1; i++)
 703                 if (at91_adc_trigger_list[i].edge_type == edge_type) {
 704                         st->selected_trig = &at91_adc_trigger_list[i];
 705                         break;
 706                 }
 707
 708         if (!st->selected_trig) {
 709                 dev_err(&pdev->dev, "invalid external trigger edge value\n");
 710                 return -EINVAL;
 711         }
 712
 713         init_waitqueue_head(&st->wq_data_available);
 714         mutex_init(&st->lock);
 715
 716         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 717         if (!res)
 718                 return -EINVAL;
 719
 720         st->base = devm_ioremap_resource(&pdev->dev, res);
 721         if (IS_ERR(st->base))
 722                 return PTR_ERR(st->base);
 723
 724         st->irq = platform_get_irq(pdev, 0);
 725         if (st->irq <= 0) {
 726                 if (!st->irq)
 727                         st->irq = -ENXIO;
 728
 729                 return st->irq;
 730         }
 731
 732         st->per_clk = devm_clk_get(&pdev->dev, "adc_clk");
 733         if (IS_ERR(st->per_clk))
 734                 return PTR_ERR(st->per_clk);
 735
 736         st->reg = devm_regulator_get(&pdev->dev, "vddana");
 737         if (IS_ERR(st->reg))
 738                 return PTR_ERR(st->reg);
 739
 740         st->vref = devm_regulator_get(&pdev->dev, "vref");
 741         if (IS_ERR(st->vref))
 742                 return PTR_ERR(st->vref);
 743
 744         ret = devm_request_irq(&pdev->dev, st->irq, at91_adc_interrupt, 0,
 745                                pdev->dev.driver->name, indio_dev);
 746         if (ret)
 747                 return ret;
 748
 749         ret = regulator_enable(st->reg);
 750         if (ret)
 751                 return ret;
 752
 753         ret = regulator_enable(st->vref);
 754         if (ret)
 755                 goto reg_disable;
 756
 757         st->vref_uv = regulator_get_voltage(st->vref);
 758         if (st->vref_uv <= 0) {
 759                 ret = -EINVAL;
 760                 goto vref_disable;
 761         }
 762
 763         at91_adc_hw_init(st);
 764
 765         ret = clk_prepare_enable(st->per_clk);
 766         if (ret)
 767                 goto vref_disable;
 768
 769         platform_set_drvdata(pdev, indio_dev);
 770
 771         if (st->selected_trig->hw_trig) {
 772                 ret = at91_adc_buffer_init(indio_dev);
 773                 if (ret < 0) {
 774                         dev_err(&pdev->dev, "couldn't initialize the buffer.\n");
 775                         goto per_clk_disable_unprepare;
 776                 }
 777
 778                 ret = at91_adc_trigger_init(indio_dev);
 779                 if (ret < 0) {
 780                         dev_err(&pdev->dev, "couldn't setup the triggers.\n");
 781                         goto per_clk_disable_unprepare;
 782                 }
 783         }
 784
 785         ret = iio_device_register(indio_dev);
 786         if (ret < 0)
 787                 goto per_clk_disable_unprepare;
 788
 789         if (st->selected_trig->hw_trig)
 790                 dev_info(&pdev->dev, "setting up trigger as %s\n",
 791                          st->selected_trig->name);
 792
 793         dev_info(&pdev->dev, "version: %x\n",
 794                  readl_relaxed(st->base + AT91_SAMA5D2_VERSION));
 795
 796         return 0;
 797
 798 per_clk_disable_unprepare:
 799         clk_disable_unprepare(st->per_clk);
 800 vref_disable:
 801         regulator_disable(st->vref);
 802 reg_disable:
 803         regulator_disable(st->reg);
 804         return ret;
 805 }
 806
 807 static int at91_adc_remove(struct platform_device *pdev)
 808 {
 809         struct iio_dev *indio_dev = platform_get_drvdata(pdev);
 810         struct at91_adc_state *st = iio_priv(indio_dev);
 811
 812         iio_device_unregister(indio_dev);
 813
 814         clk_disable_unprepare(st->per_clk);
 815
 816         regulator_disable(st->vref);
 817         regulator_disable(st->reg);
 818
 819         return 0;
 820 }
 821
 822 static __maybe_unused int at91_adc_suspend(struct device *dev)
 823 {
 824         struct iio_dev *indio_dev =
 825                         platform_get_drvdata(to_platform_device(dev));
 826         struct at91_adc_state *st = iio_priv(indio_dev);
 827
 828         /*
 829          * Do a sofware reset of the ADC before we go to suspend.
 830          * this will ensure that all pins are free from being muxed by the ADC
 831          * and can be used by for other devices.
 832          * Otherwise, ADC will hog them and we can't go to suspend mode.
 833          */
 834         at91_adc_writel(st, AT91_SAMA5D2_CR, AT91_SAMA5D2_CR_SWRST);
 835
 836         clk_disable_unprepare(st->per_clk);
 837         regulator_disable(st->vref);
 838         regulator_disable(st->reg);
 839
 840         return pinctrl_pm_select_sleep_state(dev);
 841 }
 842
 843 static __maybe_unused int at91_adc_resume(struct device *dev)
 844 {
 845         struct iio_dev *indio_dev =
 846                         platform_get_drvdata(to_platform_device(dev));
 847         struct at91_adc_state *st = iio_priv(indio_dev);
 848         int ret;
 849
 850         ret = pinctrl_pm_select_default_state(dev);
 851         if (ret)
 852                 goto resume_failed;
 853
 854         ret = regulator_enable(st->reg);
 855         if (ret)
 856                 goto resume_failed;
 857
 858         ret = regulator_enable(st->vref);
 859         if (ret)
 860                 goto reg_disable_resume;
 861
 862         ret = clk_prepare_enable(st->per_clk);
 863         if (ret)
 864                 goto vref_disable_resume;
 865
 866         at91_adc_hw_init(st);
 867
 868         /* reconfiguring trigger hardware state */
 869         if (iio_buffer_enabled(indio_dev))
 870                 at91_adc_configure_trigger(st->trig, true);
 871
 872         return 0;
 873
 874 vref_disable_resume:
 875         regulator_disable(st->vref);
 876 reg_disable_resume:
 877         regulator_disable(st->reg);
 878 resume_failed:
 879         dev_err(&indio_dev->dev, "failed to resume\n");
 880         return ret;
 881 }
 882
 883 static SIMPLE_DEV_PM_OPS(at91_adc_pm_ops, at91_adc_suspend, at91_adc_resume);
 884
 885 static const struct of_device_id at91_adc_dt_match[] = {
 886         {
 887                 .compatible = "atmel,sama5d2-adc",
 888         }, {
 889                 /* sentinel */
 890         }
 891 };
 892 MODULE_DEVICE_TABLE(of, at91_adc_dt_match);
 893
 894 static struct platform_driver at91_adc_driver = {
 895         .probe = at91_adc_probe,
 896         .remove = at91_adc_remove,
 897         .driver = {
 898                 .name = "at91-sama5d2_adc",
 899                 .of_match_table = at91_adc_dt_match,
 900                 .pm = &at91_adc_pm_ops,
 901         },
 902 };
 903 module_platform_driver(at91_adc_driver)
 904
 905 MODULE_AUTHOR("Ludovic Desroches <ludovic.desroches@atmel.com>");
 906 MODULE_DESCRIPTION("Atmel AT91 SAMA5D2 ADC");
 907 MODULE_LICENSE("GPL v2");