1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices Generic AXI ADC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
6 * Copyright 2012-2020 Analog Devices Inc.
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/regmap.h>
18 #include <linux/slab.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
22 #include <linux/iio/buffer.h>
23 #include <linux/iio/buffer-dmaengine.h>
25 #include <linux/fpga/adi-axi-common.h>
26 #include <linux/iio/adc/adi-axi-adc.h>
29 * Register definitions:
30 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
35 #define ADI_AXI_REG_RSTN 0x0040
36 #define ADI_AXI_REG_RSTN_CE_N BIT(2)
37 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
38 #define ADI_AXI_REG_RSTN_RSTN BIT(0)
40 /* ADC Channel controls */
42 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
43 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
44 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
45 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
46 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
47 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
48 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
49 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
50 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
51 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
53 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
54 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
55 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
56 ADI_AXI_REG_CHAN_CTRL_ENABLE)
58 struct adi_axi_adc_core_info {
62 struct adi_axi_adc_state {
65 struct adi_axi_adc_client *client;
66 struct regmap *regmap;
69 struct adi_axi_adc_client {
70 struct list_head entry;
71 struct adi_axi_adc_conv conv;
72 struct adi_axi_adc_state *state;
74 const struct adi_axi_adc_core_info *info;
77 static LIST_HEAD(registered_clients);
78 static DEFINE_MUTEX(registered_clients_lock);
80 static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
82 return container_of(conv, struct adi_axi_adc_client, conv);
85 void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
87 struct adi_axi_adc_client *cl = conv_to_client(conv);
89 return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client),
92 EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI);
94 static int adi_axi_adc_config_dma_buffer(struct device *dev,
95 struct iio_dev *indio_dev)
99 if (!device_property_present(dev, "dmas"))
102 if (device_property_read_string(dev, "dma-names", &dma_name))
105 return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent,
106 indio_dev, dma_name);
109 static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
110 struct iio_chan_spec const *chan,
111 int *val, int *val2, long mask)
113 struct adi_axi_adc_state *st = iio_priv(indio_dev);
114 struct adi_axi_adc_conv *conv = &st->client->conv;
119 return conv->read_raw(conv, chan, val, val2, mask);
122 static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
123 struct iio_chan_spec const *chan,
124 int val, int val2, long mask)
126 struct adi_axi_adc_state *st = iio_priv(indio_dev);
127 struct adi_axi_adc_conv *conv = &st->client->conv;
129 if (!conv->write_raw)
132 return conv->write_raw(conv, chan, val, val2, mask);
135 static int adi_axi_adc_read_avail(struct iio_dev *indio_dev,
136 struct iio_chan_spec const *chan,
137 const int **vals, int *type, int *length,
140 struct adi_axi_adc_state *st = iio_priv(indio_dev);
141 struct adi_axi_adc_conv *conv = &st->client->conv;
143 if (!conv->read_avail)
146 return conv->read_avail(conv, chan, vals, type, length, mask);
149 static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
150 const unsigned long *scan_mask)
152 struct adi_axi_adc_state *st = iio_priv(indio_dev);
153 struct adi_axi_adc_conv *conv = &st->client->conv;
157 for (i = 0; i < conv->chip_info->num_channels; i++) {
158 if (test_bit(i, scan_mask))
159 ret = regmap_set_bits(st->regmap,
160 ADI_AXI_REG_CHAN_CTRL(i),
161 ADI_AXI_REG_CHAN_CTRL_ENABLE);
163 ret = regmap_clear_bits(st->regmap,
164 ADI_AXI_REG_CHAN_CTRL(i),
165 ADI_AXI_REG_CHAN_CTRL_ENABLE);
173 static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
176 struct adi_axi_adc_client *cl;
179 alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN);
181 alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN);
183 cl = kzalloc(alloc_size, GFP_KERNEL);
185 return ERR_PTR(-ENOMEM);
187 mutex_lock(®istered_clients_lock);
189 cl->dev = get_device(dev);
191 list_add_tail(&cl->entry, ®istered_clients);
193 mutex_unlock(®istered_clients_lock);
198 static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
200 struct adi_axi_adc_client *cl = conv_to_client(conv);
202 mutex_lock(®istered_clients_lock);
204 list_del(&cl->entry);
207 mutex_unlock(®istered_clients_lock);
212 static void devm_adi_axi_adc_conv_release(void *conv)
214 adi_axi_adc_conv_unregister(conv);
217 struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
220 struct adi_axi_adc_conv *conv;
223 conv = adi_axi_adc_conv_register(dev, sizeof_priv);
227 ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release,
234 EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI);
236 static const struct iio_info adi_axi_adc_info = {
237 .read_raw = &adi_axi_adc_read_raw,
238 .write_raw = &adi_axi_adc_write_raw,
239 .update_scan_mode = &adi_axi_adc_update_scan_mode,
240 .read_avail = &adi_axi_adc_read_avail,
243 static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
244 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
247 static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
249 const struct adi_axi_adc_core_info *info;
250 struct adi_axi_adc_client *cl;
251 struct device_node *cln;
253 info = of_device_get_match_data(dev);
255 return ERR_PTR(-ENODEV);
257 cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
259 dev_err(dev, "No 'adi,adc-dev' node defined\n");
260 return ERR_PTR(-ENODEV);
263 mutex_lock(®istered_clients_lock);
265 list_for_each_entry(cl, ®istered_clients, entry) {
269 if (cl->dev->of_node != cln)
272 if (!try_module_get(cl->dev->driver->owner)) {
273 mutex_unlock(®istered_clients_lock);
275 return ERR_PTR(-ENODEV);
280 mutex_unlock(®istered_clients_lock);
285 mutex_unlock(®istered_clients_lock);
288 return ERR_PTR(-EPROBE_DEFER);
291 static int adi_axi_adc_setup_channels(struct device *dev,
292 struct adi_axi_adc_state *st)
294 struct adi_axi_adc_conv *conv = &st->client->conv;
297 if (conv->preenable_setup) {
298 ret = conv->preenable_setup(conv);
303 for (i = 0; i < conv->chip_info->num_channels; i++) {
304 ret = regmap_write(st->regmap, ADI_AXI_REG_CHAN_CTRL(i),
305 ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
313 static int axi_adc_reset(struct adi_axi_adc_state *st)
317 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN, 0);
322 ret = regmap_write(st->regmap, ADI_AXI_REG_RSTN,
323 ADI_AXI_REG_RSTN_MMCM_RSTN);
328 return regmap_write(st->regmap, ADI_AXI_REG_RSTN,
329 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
332 static void adi_axi_adc_cleanup(void *data)
334 struct adi_axi_adc_client *cl = data;
337 module_put(cl->dev->driver->owner);
340 static const struct regmap_config axi_adc_regmap_config = {
344 .max_register = 0x0800,
347 static int adi_axi_adc_probe(struct platform_device *pdev)
349 struct adi_axi_adc_conv *conv;
350 struct iio_dev *indio_dev;
351 struct adi_axi_adc_client *cl;
352 struct adi_axi_adc_state *st;
357 cl = adi_axi_adc_attach_client(&pdev->dev);
361 ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
365 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
366 if (indio_dev == NULL)
369 st = iio_priv(indio_dev);
372 mutex_init(&st->lock);
374 base = devm_platform_ioremap_resource(pdev, 0);
376 return PTR_ERR(base);
378 st->regmap = devm_regmap_init_mmio(&pdev->dev, base,
379 &axi_adc_regmap_config);
380 if (IS_ERR(st->regmap))
381 return PTR_ERR(st->regmap);
383 conv = &st->client->conv;
385 ret = axi_adc_reset(st);
389 ret = regmap_read(st->regmap, ADI_AXI_REG_VERSION, &ver);
393 if (cl->info->version > ver) {
395 "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
396 ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
397 ADI_AXI_PCORE_VER_MINOR(cl->info->version),
398 ADI_AXI_PCORE_VER_PATCH(cl->info->version),
399 ADI_AXI_PCORE_VER_MAJOR(ver),
400 ADI_AXI_PCORE_VER_MINOR(ver),
401 ADI_AXI_PCORE_VER_PATCH(ver));
405 indio_dev->info = &adi_axi_adc_info;
406 indio_dev->name = "adi-axi-adc";
407 indio_dev->modes = INDIO_DIRECT_MODE;
408 indio_dev->num_channels = conv->chip_info->num_channels;
409 indio_dev->channels = conv->chip_info->channels;
411 ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
415 ret = adi_axi_adc_setup_channels(&pdev->dev, st);
419 ret = devm_iio_device_register(&pdev->dev, indio_dev);
423 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
424 ADI_AXI_PCORE_VER_MAJOR(ver),
425 ADI_AXI_PCORE_VER_MINOR(ver),
426 ADI_AXI_PCORE_VER_PATCH(ver));
431 /* Match table for of_platform binding */
432 static const struct of_device_id adi_axi_adc_of_match[] = {
433 { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
434 { /* end of list */ }
436 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
438 static struct platform_driver adi_axi_adc_driver = {
440 .name = KBUILD_MODNAME,
441 .of_match_table = adi_axi_adc_of_match,
443 .probe = adi_axi_adc_probe,
445 module_platform_driver(adi_axi_adc_driver);
447 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
448 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
449 MODULE_LICENSE("GPL v2");