1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices Generic AXI ADC IP core
4 * Link: https://wiki.analog.com/resources/fpga/docs/axi_adc_ip
6 * Copyright 2012-2020 Analog Devices Inc.
9 #include <linux/bitfield.h>
10 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/property.h>
17 #include <linux/slab.h>
19 #include <linux/iio/iio.h>
20 #include <linux/iio/sysfs.h>
21 #include <linux/iio/buffer.h>
22 #include <linux/iio/buffer-dmaengine.h>
24 #include <linux/fpga/adi-axi-common.h>
25 #include <linux/iio/adc/adi-axi-adc.h>
28 * Register definitions:
29 * https://wiki.analog.com/resources/fpga/docs/axi_adc_ip#register_map
34 #define ADI_AXI_REG_RSTN 0x0040
35 #define ADI_AXI_REG_RSTN_CE_N BIT(2)
36 #define ADI_AXI_REG_RSTN_MMCM_RSTN BIT(1)
37 #define ADI_AXI_REG_RSTN_RSTN BIT(0)
39 /* ADC Channel controls */
41 #define ADI_AXI_REG_CHAN_CTRL(c) (0x0400 + (c) * 0x40)
42 #define ADI_AXI_REG_CHAN_CTRL_LB_OWR BIT(11)
43 #define ADI_AXI_REG_CHAN_CTRL_PN_SEL_OWR BIT(10)
44 #define ADI_AXI_REG_CHAN_CTRL_IQCOR_EN BIT(9)
45 #define ADI_AXI_REG_CHAN_CTRL_DCFILT_EN BIT(8)
46 #define ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT BIT(6)
47 #define ADI_AXI_REG_CHAN_CTRL_FMT_TYPE BIT(5)
48 #define ADI_AXI_REG_CHAN_CTRL_FMT_EN BIT(4)
49 #define ADI_AXI_REG_CHAN_CTRL_PN_TYPE_OWR BIT(1)
50 #define ADI_AXI_REG_CHAN_CTRL_ENABLE BIT(0)
52 #define ADI_AXI_REG_CHAN_CTRL_DEFAULTS \
53 (ADI_AXI_REG_CHAN_CTRL_FMT_SIGNEXT | \
54 ADI_AXI_REG_CHAN_CTRL_FMT_EN | \
55 ADI_AXI_REG_CHAN_CTRL_ENABLE)
57 struct adi_axi_adc_core_info {
61 struct adi_axi_adc_state {
64 struct adi_axi_adc_client *client;
68 struct adi_axi_adc_client {
69 struct list_head entry;
70 struct adi_axi_adc_conv conv;
71 struct adi_axi_adc_state *state;
73 const struct adi_axi_adc_core_info *info;
76 static LIST_HEAD(registered_clients);
77 static DEFINE_MUTEX(registered_clients_lock);
79 static struct adi_axi_adc_client *conv_to_client(struct adi_axi_adc_conv *conv)
81 return container_of(conv, struct adi_axi_adc_client, conv);
84 void *adi_axi_adc_conv_priv(struct adi_axi_adc_conv *conv)
86 struct adi_axi_adc_client *cl = conv_to_client(conv);
88 return (char *)cl + ALIGN(sizeof(struct adi_axi_adc_client),
91 EXPORT_SYMBOL_NS_GPL(adi_axi_adc_conv_priv, IIO_ADI_AXI);
93 static void adi_axi_adc_write(struct adi_axi_adc_state *st,
97 iowrite32(val, st->regs + reg);
100 static unsigned int adi_axi_adc_read(struct adi_axi_adc_state *st,
103 return ioread32(st->regs + reg);
106 static int adi_axi_adc_config_dma_buffer(struct device *dev,
107 struct iio_dev *indio_dev)
109 const char *dma_name;
111 if (!device_property_present(dev, "dmas"))
114 if (device_property_read_string(dev, "dma-names", &dma_name))
117 return devm_iio_dmaengine_buffer_setup(indio_dev->dev.parent,
118 indio_dev, dma_name);
121 static int adi_axi_adc_read_raw(struct iio_dev *indio_dev,
122 struct iio_chan_spec const *chan,
123 int *val, int *val2, long mask)
125 struct adi_axi_adc_state *st = iio_priv(indio_dev);
126 struct adi_axi_adc_conv *conv = &st->client->conv;
131 return conv->read_raw(conv, chan, val, val2, mask);
134 static int adi_axi_adc_write_raw(struct iio_dev *indio_dev,
135 struct iio_chan_spec const *chan,
136 int val, int val2, long mask)
138 struct adi_axi_adc_state *st = iio_priv(indio_dev);
139 struct adi_axi_adc_conv *conv = &st->client->conv;
141 if (!conv->write_raw)
144 return conv->write_raw(conv, chan, val, val2, mask);
147 static int adi_axi_adc_read_avail(struct iio_dev *indio_dev,
148 struct iio_chan_spec const *chan,
149 const int **vals, int *type, int *length,
152 struct adi_axi_adc_state *st = iio_priv(indio_dev);
153 struct adi_axi_adc_conv *conv = &st->client->conv;
155 if (!conv->read_avail)
158 return conv->read_avail(conv, chan, vals, type, length, mask);
161 static int adi_axi_adc_update_scan_mode(struct iio_dev *indio_dev,
162 const unsigned long *scan_mask)
164 struct adi_axi_adc_state *st = iio_priv(indio_dev);
165 struct adi_axi_adc_conv *conv = &st->client->conv;
166 unsigned int i, ctrl;
168 for (i = 0; i < conv->chip_info->num_channels; i++) {
169 ctrl = adi_axi_adc_read(st, ADI_AXI_REG_CHAN_CTRL(i));
171 if (test_bit(i, scan_mask))
172 ctrl |= ADI_AXI_REG_CHAN_CTRL_ENABLE;
174 ctrl &= ~ADI_AXI_REG_CHAN_CTRL_ENABLE;
176 adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i), ctrl);
182 static struct adi_axi_adc_conv *adi_axi_adc_conv_register(struct device *dev,
185 struct adi_axi_adc_client *cl;
188 alloc_size = ALIGN(sizeof(struct adi_axi_adc_client), IIO_DMA_MINALIGN);
190 alloc_size += ALIGN(sizeof_priv, IIO_DMA_MINALIGN);
192 cl = kzalloc(alloc_size, GFP_KERNEL);
194 return ERR_PTR(-ENOMEM);
196 mutex_lock(®istered_clients_lock);
198 cl->dev = get_device(dev);
200 list_add_tail(&cl->entry, ®istered_clients);
202 mutex_unlock(®istered_clients_lock);
207 static void adi_axi_adc_conv_unregister(struct adi_axi_adc_conv *conv)
209 struct adi_axi_adc_client *cl = conv_to_client(conv);
211 mutex_lock(®istered_clients_lock);
213 list_del(&cl->entry);
216 mutex_unlock(®istered_clients_lock);
221 static void devm_adi_axi_adc_conv_release(void *conv)
223 adi_axi_adc_conv_unregister(conv);
226 struct adi_axi_adc_conv *devm_adi_axi_adc_conv_register(struct device *dev,
229 struct adi_axi_adc_conv *conv;
232 conv = adi_axi_adc_conv_register(dev, sizeof_priv);
236 ret = devm_add_action_or_reset(dev, devm_adi_axi_adc_conv_release,
243 EXPORT_SYMBOL_NS_GPL(devm_adi_axi_adc_conv_register, IIO_ADI_AXI);
245 static const struct iio_info adi_axi_adc_info = {
246 .read_raw = &adi_axi_adc_read_raw,
247 .write_raw = &adi_axi_adc_write_raw,
248 .update_scan_mode = &adi_axi_adc_update_scan_mode,
249 .read_avail = &adi_axi_adc_read_avail,
252 static const struct adi_axi_adc_core_info adi_axi_adc_10_0_a_info = {
253 .version = ADI_AXI_PCORE_VER(10, 0, 'a'),
256 static struct adi_axi_adc_client *adi_axi_adc_attach_client(struct device *dev)
258 const struct adi_axi_adc_core_info *info;
259 struct adi_axi_adc_client *cl;
260 struct device_node *cln;
262 info = of_device_get_match_data(dev);
264 return ERR_PTR(-ENODEV);
266 cln = of_parse_phandle(dev->of_node, "adi,adc-dev", 0);
268 dev_err(dev, "No 'adi,adc-dev' node defined\n");
269 return ERR_PTR(-ENODEV);
272 mutex_lock(®istered_clients_lock);
274 list_for_each_entry(cl, ®istered_clients, entry) {
278 if (cl->dev->of_node != cln)
281 if (!try_module_get(cl->dev->driver->owner)) {
282 mutex_unlock(®istered_clients_lock);
284 return ERR_PTR(-ENODEV);
289 mutex_unlock(®istered_clients_lock);
294 mutex_unlock(®istered_clients_lock);
297 return ERR_PTR(-EPROBE_DEFER);
300 static int adi_axi_adc_setup_channels(struct device *dev,
301 struct adi_axi_adc_state *st)
303 struct adi_axi_adc_conv *conv = &st->client->conv;
306 if (conv->preenable_setup) {
307 ret = conv->preenable_setup(conv);
312 for (i = 0; i < conv->chip_info->num_channels; i++) {
313 adi_axi_adc_write(st, ADI_AXI_REG_CHAN_CTRL(i),
314 ADI_AXI_REG_CHAN_CTRL_DEFAULTS);
320 static void axi_adc_reset(struct adi_axi_adc_state *st)
322 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, 0);
324 adi_axi_adc_write(st, ADI_AXI_REG_RSTN, ADI_AXI_REG_RSTN_MMCM_RSTN);
326 adi_axi_adc_write(st, ADI_AXI_REG_RSTN,
327 ADI_AXI_REG_RSTN_RSTN | ADI_AXI_REG_RSTN_MMCM_RSTN);
330 static void adi_axi_adc_cleanup(void *data)
332 struct adi_axi_adc_client *cl = data;
335 module_put(cl->dev->driver->owner);
338 static int adi_axi_adc_probe(struct platform_device *pdev)
340 struct adi_axi_adc_conv *conv;
341 struct iio_dev *indio_dev;
342 struct adi_axi_adc_client *cl;
343 struct adi_axi_adc_state *st;
347 cl = adi_axi_adc_attach_client(&pdev->dev);
351 ret = devm_add_action_or_reset(&pdev->dev, adi_axi_adc_cleanup, cl);
355 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*st));
356 if (indio_dev == NULL)
359 st = iio_priv(indio_dev);
362 mutex_init(&st->lock);
364 st->regs = devm_platform_ioremap_resource(pdev, 0);
365 if (IS_ERR(st->regs))
366 return PTR_ERR(st->regs);
368 conv = &st->client->conv;
372 ver = adi_axi_adc_read(st, ADI_AXI_REG_VERSION);
374 if (cl->info->version > ver) {
376 "IP core version is too old. Expected %d.%.2d.%c, Reported %d.%.2d.%c\n",
377 ADI_AXI_PCORE_VER_MAJOR(cl->info->version),
378 ADI_AXI_PCORE_VER_MINOR(cl->info->version),
379 ADI_AXI_PCORE_VER_PATCH(cl->info->version),
380 ADI_AXI_PCORE_VER_MAJOR(ver),
381 ADI_AXI_PCORE_VER_MINOR(ver),
382 ADI_AXI_PCORE_VER_PATCH(ver));
386 indio_dev->info = &adi_axi_adc_info;
387 indio_dev->name = "adi-axi-adc";
388 indio_dev->modes = INDIO_DIRECT_MODE;
389 indio_dev->num_channels = conv->chip_info->num_channels;
390 indio_dev->channels = conv->chip_info->channels;
392 ret = adi_axi_adc_config_dma_buffer(&pdev->dev, indio_dev);
396 ret = adi_axi_adc_setup_channels(&pdev->dev, st);
400 ret = devm_iio_device_register(&pdev->dev, indio_dev);
404 dev_info(&pdev->dev, "AXI ADC IP core (%d.%.2d.%c) probed\n",
405 ADI_AXI_PCORE_VER_MAJOR(ver),
406 ADI_AXI_PCORE_VER_MINOR(ver),
407 ADI_AXI_PCORE_VER_PATCH(ver));
412 /* Match table for of_platform binding */
413 static const struct of_device_id adi_axi_adc_of_match[] = {
414 { .compatible = "adi,axi-adc-10.0.a", .data = &adi_axi_adc_10_0_a_info },
415 { /* end of list */ }
417 MODULE_DEVICE_TABLE(of, adi_axi_adc_of_match);
419 static struct platform_driver adi_axi_adc_driver = {
421 .name = KBUILD_MODNAME,
422 .of_match_table = adi_axi_adc_of_match,
424 .probe = adi_axi_adc_probe,
426 module_platform_driver(adi_axi_adc_driver);
428 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
429 MODULE_DESCRIPTION("Analog Devices Generic AXI ADC IP core driver");
430 MODULE_LICENSE("GPL v2");