1 // SPDX-License-Identifier: GPL-2.0-only
3 * Analog Devices AD9467 SPI ADC driver
5 * Copyright 2012-2020 Analog Devices Inc.
7 #include <linux/cleanup.h>
8 #include <linux/module.h>
9 #include <linux/mutex.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/spi/spi.h>
14 #include <linux/err.h>
15 #include <linux/delay.h>
16 #include <linux/gpio/consumer.h>
20 #include <linux/iio/iio.h>
21 #include <linux/iio/sysfs.h>
23 #include <linux/clk.h>
25 #include <linux/iio/adc/adi-axi-adc.h>
28 * ADI High-Speed ADC common spi interface registers
29 * See Application-Note AN-877:
30 * https://www.analog.com/media/en/technical-documentation/application-notes/AN-877.pdf
33 #define AN877_ADC_REG_CHIP_PORT_CONF 0x00
34 #define AN877_ADC_REG_CHIP_ID 0x01
35 #define AN877_ADC_REG_CHIP_GRADE 0x02
36 #define AN877_ADC_REG_CHAN_INDEX 0x05
37 #define AN877_ADC_REG_TRANSFER 0xFF
38 #define AN877_ADC_REG_MODES 0x08
39 #define AN877_ADC_REG_TEST_IO 0x0D
40 #define AN877_ADC_REG_ADC_INPUT 0x0F
41 #define AN877_ADC_REG_OFFSET 0x10
42 #define AN877_ADC_REG_OUTPUT_MODE 0x14
43 #define AN877_ADC_REG_OUTPUT_ADJUST 0x15
44 #define AN877_ADC_REG_OUTPUT_PHASE 0x16
45 #define AN877_ADC_REG_OUTPUT_DELAY 0x17
46 #define AN877_ADC_REG_VREF 0x18
47 #define AN877_ADC_REG_ANALOG_INPUT 0x2C
49 /* AN877_ADC_REG_TEST_IO */
50 #define AN877_ADC_TESTMODE_OFF 0x0
51 #define AN877_ADC_TESTMODE_MIDSCALE_SHORT 0x1
52 #define AN877_ADC_TESTMODE_POS_FULLSCALE 0x2
53 #define AN877_ADC_TESTMODE_NEG_FULLSCALE 0x3
54 #define AN877_ADC_TESTMODE_ALT_CHECKERBOARD 0x4
55 #define AN877_ADC_TESTMODE_PN23_SEQ 0x5
56 #define AN877_ADC_TESTMODE_PN9_SEQ 0x6
57 #define AN877_ADC_TESTMODE_ONE_ZERO_TOGGLE 0x7
58 #define AN877_ADC_TESTMODE_USER 0x8
59 #define AN877_ADC_TESTMODE_BIT_TOGGLE 0x9
60 #define AN877_ADC_TESTMODE_SYNC 0xA
61 #define AN877_ADC_TESTMODE_ONE_BIT_HIGH 0xB
62 #define AN877_ADC_TESTMODE_MIXED_BIT_FREQUENCY 0xC
63 #define AN877_ADC_TESTMODE_RAMP 0xF
65 /* AN877_ADC_REG_TRANSFER */
66 #define AN877_ADC_TRANSFER_SYNC 0x1
68 /* AN877_ADC_REG_OUTPUT_MODE */
69 #define AN877_ADC_OUTPUT_MODE_OFFSET_BINARY 0x0
70 #define AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT 0x1
71 #define AN877_ADC_OUTPUT_MODE_GRAY_CODE 0x2
73 /* AN877_ADC_REG_OUTPUT_PHASE */
74 #define AN877_ADC_OUTPUT_EVEN_ODD_MODE_EN 0x20
75 #define AN877_ADC_INVERT_DCO_CLK 0x80
77 /* AN877_ADC_REG_OUTPUT_DELAY */
78 #define AN877_ADC_DCO_DELAY_ENABLE 0x80
81 * Analog Devices AD9265 16-Bit, 125/105/80 MSPS ADC
84 #define CHIPID_AD9265 0x64
85 #define AD9265_DEF_OUTPUT_MODE 0x40
86 #define AD9265_REG_VREF_MASK 0xC0
89 * Analog Devices AD9434 12-Bit, 370/500 MSPS ADC
92 #define CHIPID_AD9434 0x6A
93 #define AD9434_DEF_OUTPUT_MODE 0x00
94 #define AD9434_REG_VREF_MASK 0xC0
97 * Analog Devices AD9467 16-Bit, 200/250 MSPS ADC
100 #define CHIPID_AD9467 0x50
101 #define AD9467_DEF_OUTPUT_MODE 0x08
102 #define AD9467_REG_VREF_MASK 0x0F
104 struct ad9467_chip_info {
105 struct adi_axi_adc_chip_info axi_adc_info;
106 unsigned int default_output_mode;
107 unsigned int vref_mask;
110 #define to_ad9467_chip_info(_info) \
111 container_of(_info, struct ad9467_chip_info, axi_adc_info)
113 struct ad9467_state {
114 struct spi_device *spi;
116 unsigned int output_mode;
117 unsigned int (*scales)[2];
119 struct gpio_desc *pwrdown_gpio;
120 /* ensure consistent state obtained on multiple related accesses */
124 static int ad9467_spi_read(struct spi_device *spi, unsigned int reg)
126 unsigned char tbuf[2], rbuf[1];
129 tbuf[0] = 0x80 | (reg >> 8);
130 tbuf[1] = reg & 0xFF;
132 ret = spi_write_then_read(spi,
133 tbuf, ARRAY_SIZE(tbuf),
134 rbuf, ARRAY_SIZE(rbuf));
142 static int ad9467_spi_write(struct spi_device *spi, unsigned int reg,
145 unsigned char buf[3];
151 return spi_write(spi, buf, ARRAY_SIZE(buf));
154 static int ad9467_reg_access(struct adi_axi_adc_conv *conv, unsigned int reg,
155 unsigned int writeval, unsigned int *readval)
157 struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
158 struct spi_device *spi = st->spi;
162 guard(mutex)(&st->lock);
163 ret = ad9467_spi_write(spi, reg, writeval);
166 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
167 AN877_ADC_TRANSFER_SYNC);
170 ret = ad9467_spi_read(spi, reg);
178 static const unsigned int ad9265_scale_table[][2] = {
179 {1250, 0x00}, {1500, 0x40}, {1750, 0x80}, {2000, 0xC0},
182 static const unsigned int ad9434_scale_table[][2] = {
183 {1600, 0x1C}, {1580, 0x1D}, {1550, 0x1E}, {1520, 0x1F}, {1500, 0x00},
184 {1470, 0x01}, {1440, 0x02}, {1420, 0x03}, {1390, 0x04}, {1360, 0x05},
185 {1340, 0x06}, {1310, 0x07}, {1280, 0x08}, {1260, 0x09}, {1230, 0x0A},
186 {1200, 0x0B}, {1180, 0x0C},
189 static const unsigned int ad9467_scale_table[][2] = {
190 {2000, 0}, {2100, 6}, {2200, 7},
191 {2300, 8}, {2400, 9}, {2500, 10},
194 static void __ad9467_get_scale(struct adi_axi_adc_conv *conv, int index,
195 unsigned int *val, unsigned int *val2)
197 const struct adi_axi_adc_chip_info *info = conv->chip_info;
198 const struct iio_chan_spec *chan = &info->channels[0];
201 tmp = (info->scale_table[index][0] * 1000000ULL) >>
202 chan->scan_type.realbits;
203 *val = tmp / 1000000;
204 *val2 = tmp % 1000000;
207 #define AD9467_CHAN(_chan, _si, _bits, _sign) \
209 .type = IIO_VOLTAGE, \
212 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
213 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
214 .info_mask_shared_by_type_available = BIT(IIO_CHAN_INFO_SCALE), \
223 static const struct iio_chan_spec ad9434_channels[] = {
224 AD9467_CHAN(0, 0, 12, 'S'),
227 static const struct iio_chan_spec ad9467_channels[] = {
228 AD9467_CHAN(0, 0, 16, 'S'),
231 static const struct ad9467_chip_info ad9467_chip_tbl = {
235 .max_rate = 250000000UL,
236 .scale_table = ad9467_scale_table,
237 .num_scales = ARRAY_SIZE(ad9467_scale_table),
238 .channels = ad9467_channels,
239 .num_channels = ARRAY_SIZE(ad9467_channels),
241 .default_output_mode = AD9467_DEF_OUTPUT_MODE,
242 .vref_mask = AD9467_REG_VREF_MASK,
245 static const struct ad9467_chip_info ad9434_chip_tbl = {
249 .max_rate = 500000000UL,
250 .scale_table = ad9434_scale_table,
251 .num_scales = ARRAY_SIZE(ad9434_scale_table),
252 .channels = ad9434_channels,
253 .num_channels = ARRAY_SIZE(ad9434_channels),
255 .default_output_mode = AD9434_DEF_OUTPUT_MODE,
256 .vref_mask = AD9434_REG_VREF_MASK,
259 static const struct ad9467_chip_info ad9265_chip_tbl = {
263 .max_rate = 125000000UL,
264 .scale_table = ad9265_scale_table,
265 .num_scales = ARRAY_SIZE(ad9265_scale_table),
266 .channels = ad9467_channels,
267 .num_channels = ARRAY_SIZE(ad9467_channels),
269 .default_output_mode = AD9265_DEF_OUTPUT_MODE,
270 .vref_mask = AD9265_REG_VREF_MASK,
273 static int ad9467_get_scale(struct adi_axi_adc_conv *conv, int *val, int *val2)
275 const struct adi_axi_adc_chip_info *info = conv->chip_info;
276 const struct ad9467_chip_info *info1 = to_ad9467_chip_info(info);
277 struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
278 unsigned int i, vref_val;
281 ret = ad9467_spi_read(st->spi, AN877_ADC_REG_VREF);
285 vref_val = ret & info1->vref_mask;
287 for (i = 0; i < info->num_scales; i++) {
288 if (vref_val == info->scale_table[i][1])
292 if (i == info->num_scales)
295 __ad9467_get_scale(conv, i, val, val2);
297 return IIO_VAL_INT_PLUS_MICRO;
300 static int ad9467_set_scale(struct adi_axi_adc_conv *conv, int val, int val2)
302 const struct adi_axi_adc_chip_info *info = conv->chip_info;
303 struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
304 unsigned int scale_val[2];
311 for (i = 0; i < info->num_scales; i++) {
312 __ad9467_get_scale(conv, i, &scale_val[0], &scale_val[1]);
313 if (scale_val[0] != val || scale_val[1] != val2)
316 guard(mutex)(&st->lock);
317 ret = ad9467_spi_write(st->spi, AN877_ADC_REG_VREF,
318 info->scale_table[i][1]);
322 return ad9467_spi_write(st->spi, AN877_ADC_REG_TRANSFER,
323 AN877_ADC_TRANSFER_SYNC);
329 static int ad9467_read_raw(struct adi_axi_adc_conv *conv,
330 struct iio_chan_spec const *chan,
331 int *val, int *val2, long m)
333 struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
336 case IIO_CHAN_INFO_SCALE:
337 return ad9467_get_scale(conv, val, val2);
338 case IIO_CHAN_INFO_SAMP_FREQ:
339 *val = clk_get_rate(st->clk);
347 static int ad9467_write_raw(struct adi_axi_adc_conv *conv,
348 struct iio_chan_spec const *chan,
349 int val, int val2, long mask)
351 const struct adi_axi_adc_chip_info *info = conv->chip_info;
352 struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
356 case IIO_CHAN_INFO_SCALE:
357 return ad9467_set_scale(conv, val, val2);
358 case IIO_CHAN_INFO_SAMP_FREQ:
359 r_clk = clk_round_rate(st->clk, val);
360 if (r_clk < 0 || r_clk > info->max_rate) {
361 dev_warn(&st->spi->dev,
362 "Error setting ADC sample rate %ld", r_clk);
366 return clk_set_rate(st->clk, r_clk);
372 static int ad9467_read_avail(struct adi_axi_adc_conv *conv,
373 struct iio_chan_spec const *chan,
374 const int **vals, int *type, int *length,
377 const struct adi_axi_adc_chip_info *info = conv->chip_info;
378 struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
381 case IIO_CHAN_INFO_SCALE:
382 *vals = (const int *)st->scales;
383 *type = IIO_VAL_INT_PLUS_MICRO;
384 /* Values are stored in a 2D matrix */
385 *length = info->num_scales * 2;
386 return IIO_AVAIL_LIST;
392 static int ad9467_outputmode_set(struct spi_device *spi, unsigned int mode)
396 ret = ad9467_spi_write(spi, AN877_ADC_REG_OUTPUT_MODE, mode);
400 return ad9467_spi_write(spi, AN877_ADC_REG_TRANSFER,
401 AN877_ADC_TRANSFER_SYNC);
404 static int ad9467_scale_fill(struct adi_axi_adc_conv *conv)
406 const struct adi_axi_adc_chip_info *info = conv->chip_info;
407 struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
408 unsigned int i, val1, val2;
410 st->scales = devm_kmalloc_array(&st->spi->dev, info->num_scales,
411 sizeof(*st->scales), GFP_KERNEL);
415 for (i = 0; i < info->num_scales; i++) {
416 __ad9467_get_scale(conv, i, &val1, &val2);
417 st->scales[i][0] = val1;
418 st->scales[i][1] = val2;
424 static int ad9467_preenable_setup(struct adi_axi_adc_conv *conv)
426 struct ad9467_state *st = adi_axi_adc_conv_priv(conv);
428 return ad9467_outputmode_set(st->spi, st->output_mode);
431 static int ad9467_reset(struct device *dev)
433 struct gpio_desc *gpio;
435 gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
436 if (IS_ERR_OR_NULL(gpio))
437 return PTR_ERR_OR_ZERO(gpio);
440 gpiod_set_value_cansleep(gpio, 0);
441 fsleep(10 * USEC_PER_MSEC);
446 static int ad9467_probe(struct spi_device *spi)
448 const struct ad9467_chip_info *info;
449 struct adi_axi_adc_conv *conv;
450 struct ad9467_state *st;
454 info = spi_get_device_match_data(spi);
458 conv = devm_adi_axi_adc_conv_register(&spi->dev, sizeof(*st));
460 return PTR_ERR(conv);
462 st = adi_axi_adc_conv_priv(conv);
465 st->clk = devm_clk_get_enabled(&spi->dev, "adc-clk");
467 return PTR_ERR(st->clk);
469 st->pwrdown_gpio = devm_gpiod_get_optional(&spi->dev, "powerdown",
471 if (IS_ERR(st->pwrdown_gpio))
472 return PTR_ERR(st->pwrdown_gpio);
474 ret = ad9467_reset(&spi->dev);
478 conv->chip_info = &info->axi_adc_info;
480 ret = ad9467_scale_fill(conv);
484 id = ad9467_spi_read(spi, AN877_ADC_REG_CHIP_ID);
485 if (id != conv->chip_info->id) {
486 dev_err(&spi->dev, "Mismatch CHIP_ID, got 0x%X, expected 0x%X\n",
487 id, conv->chip_info->id);
491 conv->reg_access = ad9467_reg_access;
492 conv->write_raw = ad9467_write_raw;
493 conv->read_raw = ad9467_read_raw;
494 conv->read_avail = ad9467_read_avail;
495 conv->preenable_setup = ad9467_preenable_setup;
497 st->output_mode = info->default_output_mode |
498 AN877_ADC_OUTPUT_MODE_TWOS_COMPLEMENT;
503 static const struct of_device_id ad9467_of_match[] = {
504 { .compatible = "adi,ad9265", .data = &ad9265_chip_tbl, },
505 { .compatible = "adi,ad9434", .data = &ad9434_chip_tbl, },
506 { .compatible = "adi,ad9467", .data = &ad9467_chip_tbl, },
509 MODULE_DEVICE_TABLE(of, ad9467_of_match);
511 static const struct spi_device_id ad9467_ids[] = {
512 { "ad9265", (kernel_ulong_t)&ad9265_chip_tbl },
513 { "ad9434", (kernel_ulong_t)&ad9434_chip_tbl },
514 { "ad9467", (kernel_ulong_t)&ad9467_chip_tbl },
517 MODULE_DEVICE_TABLE(spi, ad9467_ids);
519 static struct spi_driver ad9467_driver = {
522 .of_match_table = ad9467_of_match,
524 .probe = ad9467_probe,
525 .id_table = ad9467_ids,
527 module_spi_driver(ad9467_driver);
529 MODULE_AUTHOR("Michael Hennerich <michael.hennerich@analog.com>");
530 MODULE_DESCRIPTION("Analog Devices AD9467 ADC driver");
531 MODULE_LICENSE("GPL v2");
532 MODULE_IMPORT_NS(IIO_ADI_AXI);