2 * AD7785/AD7792/AD7793/AD7794/AD7795 SPI ADC driver
4 * Copyright 2011-2012 Analog Devices Inc.
6 * Licensed under the GPL-2.
9 #include <linux/interrupt.h>
10 #include <linux/device.h>
11 #include <linux/kernel.h>
12 #include <linux/slab.h>
13 #include <linux/sysfs.h>
14 #include <linux/spi/spi.h>
15 #include <linux/regulator/consumer.h>
16 #include <linux/err.h>
17 #include <linux/sched.h>
18 #include <linux/delay.h>
19 #include <linux/module.h>
21 #include <linux/iio/iio.h>
22 #include <linux/iio/sysfs.h>
23 #include <linux/iio/buffer.h>
24 #include <linux/iio/trigger.h>
25 #include <linux/iio/trigger_consumer.h>
26 #include <linux/iio/triggered_buffer.h>
27 #include <linux/iio/adc/ad_sigma_delta.h>
28 #include <linux/platform_data/ad7793.h>
31 #define AD7793_REG_COMM 0 /* Communications Register (WO, 8-bit) */
32 #define AD7793_REG_STAT 0 /* Status Register (RO, 8-bit) */
33 #define AD7793_REG_MODE 1 /* Mode Register (RW, 16-bit */
34 #define AD7793_REG_CONF 2 /* Configuration Register (RW, 16-bit) */
35 #define AD7793_REG_DATA 3 /* Data Register (RO, 16-/24-bit) */
36 #define AD7793_REG_ID 4 /* ID Register (RO, 8-bit) */
37 #define AD7793_REG_IO 5 /* IO Register (RO, 8-bit) */
38 #define AD7793_REG_OFFSET 6 /* Offset Register (RW, 16-bit
39 * (AD7792)/24-bit (AD7793)) */
40 #define AD7793_REG_FULLSALE 7 /* Full-Scale Register
41 * (RW, 16-bit (AD7792)/24-bit (AD7793)) */
43 /* Communications Register Bit Designations (AD7793_REG_COMM) */
44 #define AD7793_COMM_WEN (1 << 7) /* Write Enable */
45 #define AD7793_COMM_WRITE (0 << 6) /* Write Operation */
46 #define AD7793_COMM_READ (1 << 6) /* Read Operation */
47 #define AD7793_COMM_ADDR(x) (((x) & 0x7) << 3) /* Register Address */
48 #define AD7793_COMM_CREAD (1 << 2) /* Continuous Read of Data Register */
50 /* Status Register Bit Designations (AD7793_REG_STAT) */
51 #define AD7793_STAT_RDY (1 << 7) /* Ready */
52 #define AD7793_STAT_ERR (1 << 6) /* Error (Overrange, Underrange) */
53 #define AD7793_STAT_CH3 (1 << 2) /* Channel 3 */
54 #define AD7793_STAT_CH2 (1 << 1) /* Channel 2 */
55 #define AD7793_STAT_CH1 (1 << 0) /* Channel 1 */
57 /* Mode Register Bit Designations (AD7793_REG_MODE) */
58 #define AD7793_MODE_SEL(x) (((x) & 0x7) << 13) /* Operation Mode Select */
59 #define AD7793_MODE_SEL_MASK (0x7 << 13) /* Operation Mode Select mask */
60 #define AD7793_MODE_CLKSRC(x) (((x) & 0x3) << 6) /* ADC Clock Source Select */
61 #define AD7793_MODE_RATE(x) ((x) & 0xF) /* Filter Update Rate Select */
63 #define AD7793_MODE_CONT 0 /* Continuous Conversion Mode */
64 #define AD7793_MODE_SINGLE 1 /* Single Conversion Mode */
65 #define AD7793_MODE_IDLE 2 /* Idle Mode */
66 #define AD7793_MODE_PWRDN 3 /* Power-Down Mode */
67 #define AD7793_MODE_CAL_INT_ZERO 4 /* Internal Zero-Scale Calibration */
68 #define AD7793_MODE_CAL_INT_FULL 5 /* Internal Full-Scale Calibration */
69 #define AD7793_MODE_CAL_SYS_ZERO 6 /* System Zero-Scale Calibration */
70 #define AD7793_MODE_CAL_SYS_FULL 7 /* System Full-Scale Calibration */
72 #define AD7793_CLK_INT 0 /* Internal 64 kHz Clock not
73 * available at the CLK pin */
74 #define AD7793_CLK_INT_CO 1 /* Internal 64 kHz Clock available
76 #define AD7793_CLK_EXT 2 /* External 64 kHz Clock */
77 #define AD7793_CLK_EXT_DIV2 3 /* External Clock divided by 2 */
79 /* Configuration Register Bit Designations (AD7793_REG_CONF) */
80 #define AD7793_CONF_VBIAS(x) (((x) & 0x3) << 14) /* Bias Voltage
82 #define AD7793_CONF_BO_EN (1 << 13) /* Burnout Current Enable */
83 #define AD7793_CONF_UNIPOLAR (1 << 12) /* Unipolar/Bipolar Enable */
84 #define AD7793_CONF_BOOST (1 << 11) /* Boost Enable */
85 #define AD7793_CONF_GAIN(x) (((x) & 0x7) << 8) /* Gain Select */
86 #define AD7793_CONF_REFSEL(x) ((x) << 6) /* INT/EXT Reference Select */
87 #define AD7793_CONF_BUF (1 << 4) /* Buffered Mode Enable */
88 #define AD7793_CONF_CHAN(x) ((x) & 0xf) /* Channel select */
89 #define AD7793_CONF_CHAN_MASK 0xf /* Channel select mask */
91 #define AD7793_CH_AIN1P_AIN1M 0 /* AIN1(+) - AIN1(-) */
92 #define AD7793_CH_AIN2P_AIN2M 1 /* AIN2(+) - AIN2(-) */
93 #define AD7793_CH_AIN3P_AIN3M 2 /* AIN3(+) - AIN3(-) */
94 #define AD7793_CH_AIN1M_AIN1M 3 /* AIN1(-) - AIN1(-) */
95 #define AD7793_CH_TEMP 6 /* Temp Sensor */
96 #define AD7793_CH_AVDD_MONITOR 7 /* AVDD Monitor */
98 #define AD7795_CH_AIN4P_AIN4M 4 /* AIN4(+) - AIN4(-) */
99 #define AD7795_CH_AIN5P_AIN5M 5 /* AIN5(+) - AIN5(-) */
100 #define AD7795_CH_AIN6P_AIN6M 6 /* AIN6(+) - AIN6(-) */
101 #define AD7795_CH_AIN1M_AIN1M 8 /* AIN1(-) - AIN1(-) */
103 /* ID Register Bit Designations (AD7793_REG_ID) */
104 #define AD7785_ID 0x3
105 #define AD7792_ID 0xA
106 #define AD7793_ID 0xB
107 #define AD7794_ID 0xF
108 #define AD7795_ID 0xF
109 #define AD7796_ID 0xA
110 #define AD7797_ID 0xB
111 #define AD7798_ID 0x8
112 #define AD7799_ID 0x9
113 #define AD7793_ID_MASK 0xF
115 /* IO (Excitation Current Sources) Register Bit Designations (AD7793_REG_IO) */
116 #define AD7793_IO_IEXC1_IOUT1_IEXC2_IOUT2 0 /* IEXC1 connect to IOUT1,
117 * IEXC2 connect to IOUT2 */
118 #define AD7793_IO_IEXC1_IOUT2_IEXC2_IOUT1 1 /* IEXC1 connect to IOUT2,
119 * IEXC2 connect to IOUT1 */
120 #define AD7793_IO_IEXC1_IEXC2_IOUT1 2 /* Both current sources
121 * IEXC1,2 connect to IOUT1 */
122 #define AD7793_IO_IEXC1_IEXC2_IOUT2 3 /* Both current sources
123 * IEXC1,2 connect to IOUT2 */
125 #define AD7793_IO_IXCEN_10uA (1 << 0) /* Excitation Current 10uA */
126 #define AD7793_IO_IXCEN_210uA (2 << 0) /* Excitation Current 210uA */
127 #define AD7793_IO_IXCEN_1mA (3 << 0) /* Excitation Current 1mA */
130 * The AD7792/AD7793 features a dual use data out ready DOUT/RDY output.
131 * In order to avoid contentions on the SPI bus, it's therefore necessary
132 * to use spi bus locking.
134 * The DOUT/RDY output must also be wired to an interrupt capable GPIO.
137 #define AD7793_FLAG_HAS_CLKSEL BIT(0)
138 #define AD7793_FLAG_HAS_REFSEL BIT(1)
139 #define AD7793_FLAG_HAS_VBIAS BIT(2)
140 #define AD7793_HAS_EXITATION_CURRENT BIT(3)
141 #define AD7793_FLAG_HAS_GAIN BIT(4)
142 #define AD7793_FLAG_HAS_BUFFER BIT(5)
144 struct ad7793_chip_info {
146 const struct iio_chan_spec *channels;
147 unsigned int num_channels;
150 const struct iio_info *iio_info;
151 const u16 *sample_freq_avail;
154 struct ad7793_state {
155 const struct ad7793_chip_info *chip_info;
156 struct regulator *reg;
160 u32 scale_avail[8][2];
162 struct ad_sigma_delta sd;
166 enum ad7793_supported_device_ids {
178 static struct ad7793_state *ad_sigma_delta_to_ad7793(struct ad_sigma_delta *sd)
180 return container_of(sd, struct ad7793_state, sd);
183 static int ad7793_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
185 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
187 st->conf &= ~AD7793_CONF_CHAN_MASK;
188 st->conf |= AD7793_CONF_CHAN(channel);
190 return ad_sd_write_reg(&st->sd, AD7793_REG_CONF, 2, st->conf);
193 static int ad7793_set_mode(struct ad_sigma_delta *sd,
194 enum ad_sigma_delta_mode mode)
196 struct ad7793_state *st = ad_sigma_delta_to_ad7793(sd);
198 st->mode &= ~AD7793_MODE_SEL_MASK;
199 st->mode |= AD7793_MODE_SEL(mode);
201 return ad_sd_write_reg(&st->sd, AD7793_REG_MODE, 2, st->mode);
204 static const struct ad_sigma_delta_info ad7793_sigma_delta_info = {
205 .set_channel = ad7793_set_channel,
206 .set_mode = ad7793_set_mode,
207 .has_registers = true,
212 static const struct ad_sd_calib_data ad7793_calib_arr[6] = {
213 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN1P_AIN1M},
214 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN1P_AIN1M},
215 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN2P_AIN2M},
216 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN2P_AIN2M},
217 {AD7793_MODE_CAL_INT_ZERO, AD7793_CH_AIN3P_AIN3M},
218 {AD7793_MODE_CAL_INT_FULL, AD7793_CH_AIN3P_AIN3M}
221 static int ad7793_calibrate_all(struct ad7793_state *st)
223 return ad_sd_calibrate_all(&st->sd, ad7793_calib_arr,
224 ARRAY_SIZE(ad7793_calib_arr));
227 static int ad7793_check_platform_data(struct ad7793_state *st,
228 const struct ad7793_platform_data *pdata)
230 if ((pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT1 ||
231 pdata->current_source_direction == AD7793_IEXEC1_IEXEC2_IOUT2) &&
232 ((pdata->exitation_current != AD7793_IX_10uA) &&
233 (pdata->exitation_current != AD7793_IX_210uA)))
236 if (!(st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL) &&
237 pdata->clock_src != AD7793_CLK_SRC_INT)
240 if (!(st->chip_info->flags & AD7793_FLAG_HAS_REFSEL) &&
241 pdata->refsel != AD7793_REFSEL_REFIN1)
244 if (!(st->chip_info->flags & AD7793_FLAG_HAS_VBIAS) &&
245 pdata->bias_voltage != AD7793_BIAS_VOLTAGE_DISABLED)
248 if (!(st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) &&
249 pdata->exitation_current != AD7793_IX_DISABLED)
255 static int ad7793_setup(struct iio_dev *indio_dev,
256 const struct ad7793_platform_data *pdata,
257 unsigned int vref_mv)
259 struct ad7793_state *st = iio_priv(indio_dev);
261 unsigned long long scale_uv;
264 ret = ad7793_check_platform_data(st, pdata);
268 /* reset the serial interface */
269 ret = ad_sd_reset(&st->sd, 32);
272 usleep_range(500, 2000); /* Wait for at least 500us */
274 /* write/read test for device presence */
275 ret = ad_sd_read_reg(&st->sd, AD7793_REG_ID, 1, &id);
279 id &= AD7793_ID_MASK;
281 if (id != st->chip_info->id) {
283 dev_err(&st->sd.spi->dev, "device ID query failed\n");
287 st->mode = AD7793_MODE_RATE(1);
290 if (st->chip_info->flags & AD7793_FLAG_HAS_CLKSEL)
291 st->mode |= AD7793_MODE_CLKSRC(pdata->clock_src);
292 if (st->chip_info->flags & AD7793_FLAG_HAS_REFSEL)
293 st->conf |= AD7793_CONF_REFSEL(pdata->refsel);
294 if (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS)
295 st->conf |= AD7793_CONF_VBIAS(pdata->bias_voltage);
296 if (pdata->buffered || !(st->chip_info->flags & AD7793_FLAG_HAS_BUFFER))
297 st->conf |= AD7793_CONF_BUF;
298 if (pdata->boost_enable &&
299 (st->chip_info->flags & AD7793_FLAG_HAS_VBIAS))
300 st->conf |= AD7793_CONF_BOOST;
301 if (pdata->burnout_current)
302 st->conf |= AD7793_CONF_BO_EN;
304 st->conf |= AD7793_CONF_UNIPOLAR;
306 if (!(st->chip_info->flags & AD7793_FLAG_HAS_GAIN))
307 st->conf |= AD7793_CONF_GAIN(7);
309 ret = ad7793_set_mode(&st->sd, AD_SD_MODE_IDLE);
313 ret = ad7793_set_channel(&st->sd, 0);
317 if (st->chip_info->flags & AD7793_HAS_EXITATION_CURRENT) {
318 ret = ad_sd_write_reg(&st->sd, AD7793_REG_IO, 1,
319 pdata->exitation_current |
320 (pdata->current_source_direction << 2));
325 ret = ad7793_calibrate_all(st);
329 /* Populate available ADC input ranges */
330 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) {
331 scale_uv = ((u64)vref_mv * 100000000)
332 >> (st->chip_info->channels[0].scan_type.realbits -
333 (!!(st->conf & AD7793_CONF_UNIPOLAR) ? 0 : 1));
336 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10;
337 st->scale_avail[i][0] = scale_uv;
342 dev_err(&st->sd.spi->dev, "setup failed\n");
346 static const u16 ad7793_sample_freq_avail[16] = {0, 470, 242, 123, 62, 50, 39,
347 33, 19, 17, 16, 12, 10, 8, 6, 4};
349 static const u16 ad7797_sample_freq_avail[16] = {0, 0, 0, 123, 62, 50, 0,
350 33, 0, 17, 16, 12, 10, 8, 6, 4};
352 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
353 "470 242 123 62 50 39 33 19 17 16 12 10 8 6 4");
355 static IIO_CONST_ATTR_NAMED(sampling_frequency_available_ad7797,
356 sampling_frequency_available, "123 62 50 33 17 16 12 10 8 6 4");
358 static ssize_t ad7793_show_scale_available(struct device *dev,
359 struct device_attribute *attr, char *buf)
361 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
362 struct ad7793_state *st = iio_priv(indio_dev);
365 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
366 len += sprintf(buf + len, "%d.%09u ", st->scale_avail[i][0],
367 st->scale_avail[i][1]);
369 len += sprintf(buf + len, "\n");
374 static IIO_DEVICE_ATTR_NAMED(in_m_in_scale_available,
375 in_voltage-voltage_scale_available, S_IRUGO,
376 ad7793_show_scale_available, NULL, 0);
378 static struct attribute *ad7793_attributes[] = {
379 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
380 &iio_dev_attr_in_m_in_scale_available.dev_attr.attr,
384 static const struct attribute_group ad7793_attribute_group = {
385 .attrs = ad7793_attributes,
388 static struct attribute *ad7797_attributes[] = {
389 &iio_const_attr_sampling_frequency_available_ad7797.dev_attr.attr,
393 static const struct attribute_group ad7797_attribute_group = {
394 .attrs = ad7797_attributes,
397 static int ad7793_read_raw(struct iio_dev *indio_dev,
398 struct iio_chan_spec const *chan,
403 struct ad7793_state *st = iio_priv(indio_dev);
405 unsigned long long scale_uv;
406 bool unipolar = !!(st->conf & AD7793_CONF_UNIPOLAR);
409 case IIO_CHAN_INFO_RAW:
410 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
416 case IIO_CHAN_INFO_SCALE:
417 switch (chan->type) {
419 if (chan->differential) {
421 scale_avail[(st->conf >> 8) & 0x7][0];
423 scale_avail[(st->conf >> 8) & 0x7][1];
424 return IIO_VAL_INT_PLUS_NANO;
426 /* 1170mV / 2^23 * 6 */
427 scale_uv = (1170ULL * 1000000000ULL * 6ULL);
430 /* 1170mV / 0.81 mV/C / 2^23 */
431 scale_uv = 1444444444444444ULL;
437 scale_uv >>= (chan->scan_type.realbits - (unipolar ? 0 : 1));
440 return IIO_VAL_INT_PLUS_NANO;
441 case IIO_CHAN_INFO_OFFSET:
443 *val = -(1 << (chan->scan_type.realbits - 1));
447 /* Kelvin to Celsius */
448 if (chan->type == IIO_TEMP) {
449 unsigned long long offset;
452 shift = chan->scan_type.realbits - (unipolar ? 0 : 1);
453 offset = 273ULL << shift;
454 do_div(offset, 1444);
458 case IIO_CHAN_INFO_SAMP_FREQ:
460 ->sample_freq_avail[AD7793_MODE_RATE(st->mode)];
466 static int ad7793_write_raw(struct iio_dev *indio_dev,
467 struct iio_chan_spec const *chan,
472 struct ad7793_state *st = iio_priv(indio_dev);
476 ret = iio_device_claim_direct_mode(indio_dev);
481 case IIO_CHAN_INFO_SCALE:
483 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++)
484 if (val2 == st->scale_avail[i][1]) {
487 st->conf &= ~AD7793_CONF_GAIN(-1);
488 st->conf |= AD7793_CONF_GAIN(i);
493 ad_sd_write_reg(&st->sd, AD7793_REG_CONF,
494 sizeof(st->conf), st->conf);
495 ad7793_calibrate_all(st);
499 case IIO_CHAN_INFO_SAMP_FREQ:
505 for (i = 0; i < 16; i++)
506 if (val == st->chip_info->sample_freq_avail[i])
514 st->mode &= ~AD7793_MODE_RATE(-1);
515 st->mode |= AD7793_MODE_RATE(i);
516 ad_sd_write_reg(&st->sd, AD7793_REG_MODE, sizeof(st->mode),
523 iio_device_release_direct_mode(indio_dev);
527 static int ad7793_write_raw_get_fmt(struct iio_dev *indio_dev,
528 struct iio_chan_spec const *chan,
531 return IIO_VAL_INT_PLUS_NANO;
534 static const struct iio_info ad7793_info = {
535 .read_raw = &ad7793_read_raw,
536 .write_raw = &ad7793_write_raw,
537 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
538 .attrs = &ad7793_attribute_group,
539 .validate_trigger = ad_sd_validate_trigger,
540 .driver_module = THIS_MODULE,
543 static const struct iio_info ad7797_info = {
544 .read_raw = &ad7793_read_raw,
545 .write_raw = &ad7793_write_raw,
546 .write_raw_get_fmt = &ad7793_write_raw_get_fmt,
547 .attrs = &ad7797_attribute_group,
548 .validate_trigger = ad_sd_validate_trigger,
549 .driver_module = THIS_MODULE,
552 #define DECLARE_AD7793_CHANNELS(_name, _b, _sb, _s) \
553 const struct iio_chan_spec _name##_channels[] = { \
554 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), (_s)), \
555 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), (_s)), \
556 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), (_s)), \
557 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), (_s)), \
558 AD_SD_TEMP_CHANNEL(4, AD7793_CH_TEMP, (_b), (_sb), (_s)), \
559 AD_SD_SUPPLY_CHANNEL(5, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), (_s)), \
560 IIO_CHAN_SOFT_TIMESTAMP(6), \
563 #define DECLARE_AD7795_CHANNELS(_name, _b, _sb) \
564 const struct iio_chan_spec _name##_channels[] = { \
565 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
566 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
567 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
568 AD_SD_DIFF_CHANNEL(3, 3, 3, AD7795_CH_AIN4P_AIN4M, (_b), (_sb), 0), \
569 AD_SD_DIFF_CHANNEL(4, 4, 4, AD7795_CH_AIN5P_AIN5M, (_b), (_sb), 0), \
570 AD_SD_DIFF_CHANNEL(5, 5, 5, AD7795_CH_AIN6P_AIN6M, (_b), (_sb), 0), \
571 AD_SD_SHORTED_CHANNEL(6, 0, AD7795_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
572 AD_SD_TEMP_CHANNEL(7, AD7793_CH_TEMP, (_b), (_sb), 0), \
573 AD_SD_SUPPLY_CHANNEL(8, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
574 IIO_CHAN_SOFT_TIMESTAMP(9), \
577 #define DECLARE_AD7797_CHANNELS(_name, _b, _sb) \
578 const struct iio_chan_spec _name##_channels[] = { \
579 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
580 AD_SD_SHORTED_CHANNEL(1, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
581 AD_SD_TEMP_CHANNEL(2, AD7793_CH_TEMP, (_b), (_sb), 0), \
582 AD_SD_SUPPLY_CHANNEL(3, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
583 IIO_CHAN_SOFT_TIMESTAMP(4), \
586 #define DECLARE_AD7799_CHANNELS(_name, _b, _sb) \
587 const struct iio_chan_spec _name##_channels[] = { \
588 AD_SD_DIFF_CHANNEL(0, 0, 0, AD7793_CH_AIN1P_AIN1M, (_b), (_sb), 0), \
589 AD_SD_DIFF_CHANNEL(1, 1, 1, AD7793_CH_AIN2P_AIN2M, (_b), (_sb), 0), \
590 AD_SD_DIFF_CHANNEL(2, 2, 2, AD7793_CH_AIN3P_AIN3M, (_b), (_sb), 0), \
591 AD_SD_SHORTED_CHANNEL(3, 0, AD7793_CH_AIN1M_AIN1M, (_b), (_sb), 0), \
592 AD_SD_SUPPLY_CHANNEL(4, 3, AD7793_CH_AVDD_MONITOR, (_b), (_sb), 0), \
593 IIO_CHAN_SOFT_TIMESTAMP(5), \
596 static DECLARE_AD7793_CHANNELS(ad7785, 20, 32, 4);
597 static DECLARE_AD7793_CHANNELS(ad7792, 16, 32, 0);
598 static DECLARE_AD7793_CHANNELS(ad7793, 24, 32, 0);
599 static DECLARE_AD7795_CHANNELS(ad7794, 16, 32);
600 static DECLARE_AD7795_CHANNELS(ad7795, 24, 32);
601 static DECLARE_AD7797_CHANNELS(ad7796, 16, 16);
602 static DECLARE_AD7797_CHANNELS(ad7797, 24, 32);
603 static DECLARE_AD7799_CHANNELS(ad7798, 16, 16);
604 static DECLARE_AD7799_CHANNELS(ad7799, 24, 32);
606 static const struct ad7793_chip_info ad7793_chip_info_tbl[] = {
609 .channels = ad7785_channels,
610 .num_channels = ARRAY_SIZE(ad7785_channels),
611 .iio_info = &ad7793_info,
612 .sample_freq_avail = ad7793_sample_freq_avail,
613 .flags = AD7793_FLAG_HAS_CLKSEL |
614 AD7793_FLAG_HAS_REFSEL |
615 AD7793_FLAG_HAS_VBIAS |
616 AD7793_HAS_EXITATION_CURRENT |
617 AD7793_FLAG_HAS_GAIN |
618 AD7793_FLAG_HAS_BUFFER,
622 .channels = ad7792_channels,
623 .num_channels = ARRAY_SIZE(ad7792_channels),
624 .iio_info = &ad7793_info,
625 .sample_freq_avail = ad7793_sample_freq_avail,
626 .flags = AD7793_FLAG_HAS_CLKSEL |
627 AD7793_FLAG_HAS_REFSEL |
628 AD7793_FLAG_HAS_VBIAS |
629 AD7793_HAS_EXITATION_CURRENT |
630 AD7793_FLAG_HAS_GAIN |
631 AD7793_FLAG_HAS_BUFFER,
635 .channels = ad7793_channels,
636 .num_channels = ARRAY_SIZE(ad7793_channels),
637 .iio_info = &ad7793_info,
638 .sample_freq_avail = ad7793_sample_freq_avail,
639 .flags = AD7793_FLAG_HAS_CLKSEL |
640 AD7793_FLAG_HAS_REFSEL |
641 AD7793_FLAG_HAS_VBIAS |
642 AD7793_HAS_EXITATION_CURRENT |
643 AD7793_FLAG_HAS_GAIN |
644 AD7793_FLAG_HAS_BUFFER,
648 .channels = ad7794_channels,
649 .num_channels = ARRAY_SIZE(ad7794_channels),
650 .iio_info = &ad7793_info,
651 .sample_freq_avail = ad7793_sample_freq_avail,
652 .flags = AD7793_FLAG_HAS_CLKSEL |
653 AD7793_FLAG_HAS_REFSEL |
654 AD7793_FLAG_HAS_VBIAS |
655 AD7793_HAS_EXITATION_CURRENT |
656 AD7793_FLAG_HAS_GAIN |
657 AD7793_FLAG_HAS_BUFFER,
661 .channels = ad7795_channels,
662 .num_channels = ARRAY_SIZE(ad7795_channels),
663 .iio_info = &ad7793_info,
664 .sample_freq_avail = ad7793_sample_freq_avail,
665 .flags = AD7793_FLAG_HAS_CLKSEL |
666 AD7793_FLAG_HAS_REFSEL |
667 AD7793_FLAG_HAS_VBIAS |
668 AD7793_HAS_EXITATION_CURRENT |
669 AD7793_FLAG_HAS_GAIN |
670 AD7793_FLAG_HAS_BUFFER,
674 .channels = ad7796_channels,
675 .num_channels = ARRAY_SIZE(ad7796_channels),
676 .iio_info = &ad7797_info,
677 .sample_freq_avail = ad7797_sample_freq_avail,
678 .flags = AD7793_FLAG_HAS_CLKSEL,
682 .channels = ad7797_channels,
683 .num_channels = ARRAY_SIZE(ad7797_channels),
684 .iio_info = &ad7797_info,
685 .sample_freq_avail = ad7797_sample_freq_avail,
686 .flags = AD7793_FLAG_HAS_CLKSEL,
690 .channels = ad7798_channels,
691 .num_channels = ARRAY_SIZE(ad7798_channels),
692 .iio_info = &ad7793_info,
693 .sample_freq_avail = ad7793_sample_freq_avail,
694 .flags = AD7793_FLAG_HAS_GAIN |
695 AD7793_FLAG_HAS_BUFFER,
699 .channels = ad7799_channels,
700 .num_channels = ARRAY_SIZE(ad7799_channels),
701 .iio_info = &ad7793_info,
702 .sample_freq_avail = ad7793_sample_freq_avail,
703 .flags = AD7793_FLAG_HAS_GAIN |
704 AD7793_FLAG_HAS_BUFFER,
708 static int ad7793_probe(struct spi_device *spi)
710 const struct ad7793_platform_data *pdata = spi->dev.platform_data;
711 struct ad7793_state *st;
712 struct iio_dev *indio_dev;
713 int ret, vref_mv = 0;
716 dev_err(&spi->dev, "no platform data?\n");
721 dev_err(&spi->dev, "no IRQ?\n");
725 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
726 if (indio_dev == NULL)
729 st = iio_priv(indio_dev);
731 ad_sd_init(&st->sd, indio_dev, spi, &ad7793_sigma_delta_info);
733 if (pdata->refsel != AD7793_REFSEL_INTERNAL) {
734 st->reg = devm_regulator_get(&spi->dev, "refin");
736 return PTR_ERR(st->reg);
738 ret = regulator_enable(st->reg);
742 vref_mv = regulator_get_voltage(st->reg);
745 goto error_disable_reg;
750 vref_mv = 1170; /* Build-in ref */
754 &ad7793_chip_info_tbl[spi_get_device_id(spi)->driver_data];
756 spi_set_drvdata(spi, indio_dev);
758 indio_dev->dev.parent = &spi->dev;
759 indio_dev->dev.of_node = spi->dev.of_node;
760 indio_dev->name = spi_get_device_id(spi)->name;
761 indio_dev->modes = INDIO_DIRECT_MODE;
762 indio_dev->channels = st->chip_info->channels;
763 indio_dev->num_channels = st->chip_info->num_channels;
764 indio_dev->info = st->chip_info->iio_info;
766 ret = ad_sd_setup_buffer_and_trigger(indio_dev);
768 goto error_disable_reg;
770 ret = ad7793_setup(indio_dev, pdata, vref_mv);
772 goto error_remove_trigger;
774 ret = iio_device_register(indio_dev);
776 goto error_remove_trigger;
780 error_remove_trigger:
781 ad_sd_cleanup_buffer_and_trigger(indio_dev);
783 if (pdata->refsel != AD7793_REFSEL_INTERNAL)
784 regulator_disable(st->reg);
789 static int ad7793_remove(struct spi_device *spi)
791 const struct ad7793_platform_data *pdata = spi->dev.platform_data;
792 struct iio_dev *indio_dev = spi_get_drvdata(spi);
793 struct ad7793_state *st = iio_priv(indio_dev);
795 iio_device_unregister(indio_dev);
796 ad_sd_cleanup_buffer_and_trigger(indio_dev);
798 if (pdata->refsel != AD7793_REFSEL_INTERNAL)
799 regulator_disable(st->reg);
804 static const struct spi_device_id ad7793_id[] = {
805 {"ad7785", ID_AD7785},
806 {"ad7792", ID_AD7792},
807 {"ad7793", ID_AD7793},
808 {"ad7794", ID_AD7794},
809 {"ad7795", ID_AD7795},
810 {"ad7796", ID_AD7796},
811 {"ad7797", ID_AD7797},
812 {"ad7798", ID_AD7798},
813 {"ad7799", ID_AD7799},
816 MODULE_DEVICE_TABLE(spi, ad7793_id);
818 static struct spi_driver ad7793_driver = {
822 .probe = ad7793_probe,
823 .remove = ad7793_remove,
824 .id_table = ad7793_id,
826 module_spi_driver(ad7793_driver);
828 MODULE_AUTHOR("Michael Hennerich <hennerich@blackfin.uclinux.org>");
829 MODULE_DESCRIPTION("Analog Devices AD7793 and similar ADCs");
830 MODULE_LICENSE("GPL v2");