drivers/iio/adc/ad7124.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * AD7124 SPI ADC driver
   4  *
   5  * Copyright 2018 Analog Devices Inc.
   6  */
   7 #include <linux/bitfield.h>
   8 #include <linux/clk.h>
   9 #include <linux/delay.h>
  10 #include <linux/device.h>
  11 #include <linux/err.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/of_device.h>
  16 #include <linux/regulator/consumer.h>
  17 #include <linux/spi/spi.h>
  18
  19 #include <linux/iio/iio.h>
  20 #include <linux/iio/adc/ad_sigma_delta.h>
  21 #include <linux/iio/sysfs.h>
  22
  23 /* AD7124 registers */
  24 #define AD7124_COMMS                    0x00
  25 #define AD7124_STATUS                   0x00
  26 #define AD7124_ADC_CONTROL              0x01
  27 #define AD7124_DATA                     0x02
  28 #define AD7124_IO_CONTROL_1             0x03
  29 #define AD7124_IO_CONTROL_2             0x04
  30 #define AD7124_ID                       0x05
  31 #define AD7124_ERROR                    0x06
  32 #define AD7124_ERROR_EN         0x07
  33 #define AD7124_MCLK_COUNT               0x08
  34 #define AD7124_CHANNEL(x)               (0x09 + (x))
  35 #define AD7124_CONFIG(x)                (0x19 + (x))
  36 #define AD7124_FILTER(x)                (0x21 + (x))
  37 #define AD7124_OFFSET(x)                (0x29 + (x))
  38 #define AD7124_GAIN(x)                  (0x31 + (x))
  39
  40 /* AD7124_STATUS */
  41 #define AD7124_STATUS_POR_FLAG_MSK      BIT(4)
  42
  43 /* AD7124_ADC_CONTROL */
  44 #define AD7124_ADC_CTRL_REF_EN_MSK      BIT(8)
  45 #define AD7124_ADC_CTRL_REF_EN(x)       FIELD_PREP(AD7124_ADC_CTRL_REF_EN_MSK, x)
  46 #define AD7124_ADC_CTRL_PWR_MSK GENMASK(7, 6)
  47 #define AD7124_ADC_CTRL_PWR(x)          FIELD_PREP(AD7124_ADC_CTRL_PWR_MSK, x)
  48 #define AD7124_ADC_CTRL_MODE_MSK        GENMASK(5, 2)
  49 #define AD7124_ADC_CTRL_MODE(x) FIELD_PREP(AD7124_ADC_CTRL_MODE_MSK, x)
  50
  51 /* AD7124 ID */
  52 #define AD7124_DEVICE_ID_MSK            GENMASK(7, 4)
  53 #define AD7124_DEVICE_ID_GET(x)         FIELD_GET(AD7124_DEVICE_ID_MSK, x)
  54 #define AD7124_SILICON_REV_MSK          GENMASK(3, 0)
  55 #define AD7124_SILICON_REV_GET(x)       FIELD_GET(AD7124_SILICON_REV_MSK, x)
  56
  57 #define CHIPID_AD7124_4                 0x0
  58 #define CHIPID_AD7124_8                 0x1
  59
  60 /* AD7124_CHANNEL_X */
  61 #define AD7124_CHANNEL_EN_MSK           BIT(15)
  62 #define AD7124_CHANNEL_EN(x)            FIELD_PREP(AD7124_CHANNEL_EN_MSK, x)
  63 #define AD7124_CHANNEL_SETUP_MSK        GENMASK(14, 12)
  64 #define AD7124_CHANNEL_SETUP(x) FIELD_PREP(AD7124_CHANNEL_SETUP_MSK, x)
  65 #define AD7124_CHANNEL_AINP_MSK GENMASK(9, 5)
  66 #define AD7124_CHANNEL_AINP(x)          FIELD_PREP(AD7124_CHANNEL_AINP_MSK, x)
  67 #define AD7124_CHANNEL_AINM_MSK GENMASK(4, 0)
  68 #define AD7124_CHANNEL_AINM(x)          FIELD_PREP(AD7124_CHANNEL_AINM_MSK, x)
  69
  70 /* AD7124_CONFIG_X */
  71 #define AD7124_CONFIG_BIPOLAR_MSK       BIT(11)
  72 #define AD7124_CONFIG_BIPOLAR(x)        FIELD_PREP(AD7124_CONFIG_BIPOLAR_MSK, x)
  73 #define AD7124_CONFIG_REF_SEL_MSK       GENMASK(4, 3)
  74 #define AD7124_CONFIG_REF_SEL(x)        FIELD_PREP(AD7124_CONFIG_REF_SEL_MSK, x)
  75 #define AD7124_CONFIG_PGA_MSK           GENMASK(2, 0)
  76 #define AD7124_CONFIG_PGA(x)            FIELD_PREP(AD7124_CONFIG_PGA_MSK, x)
  77 #define AD7124_CONFIG_IN_BUFF_MSK       GENMASK(6, 5)
  78 #define AD7124_CONFIG_IN_BUFF(x)        FIELD_PREP(AD7124_CONFIG_IN_BUFF_MSK, x)
  79
  80 /* AD7124_FILTER_X */
  81 #define AD7124_FILTER_FS_MSK            GENMASK(10, 0)
  82 #define AD7124_FILTER_FS(x)             FIELD_PREP(AD7124_FILTER_FS_MSK, x)
  83 #define AD7124_FILTER_TYPE_MSK          GENMASK(23, 21)
  84 #define AD7124_FILTER_TYPE_SEL(x)       FIELD_PREP(AD7124_FILTER_TYPE_MSK, x)
  85
  86 #define AD7124_SINC3_FILTER 2
  87 #define AD7124_SINC4_FILTER 0
  88
  89 enum ad7124_ids {
  90         ID_AD7124_4,
  91         ID_AD7124_8,
  92 };
  93
  94 enum ad7124_ref_sel {
  95         AD7124_REFIN1,
  96         AD7124_REFIN2,
  97         AD7124_INT_REF,
  98         AD7124_AVDD_REF,
  99 };
 100
 101 enum ad7124_power_mode {
 102         AD7124_LOW_POWER,
 103         AD7124_MID_POWER,
 104         AD7124_FULL_POWER,
 105 };
 106
 107 static const unsigned int ad7124_gain[8] = {
 108         1, 2, 4, 8, 16, 32, 64, 128
 109 };
 110
 111 static const unsigned int ad7124_reg_size[] = {
 112         1, 2, 3, 3, 2, 1, 3, 3, 1, 2, 2, 2, 2,
 113         2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
 114         2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3,
 115         3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3,
 116         3, 3, 3, 3, 3
 117 };
 118
 119 static const int ad7124_master_clk_freq_hz[3] = {
 120         [AD7124_LOW_POWER] = 76800,
 121         [AD7124_MID_POWER] = 153600,
 122         [AD7124_FULL_POWER] = 614400,
 123 };
 124
 125 static const char * const ad7124_ref_names[] = {
 126         [AD7124_REFIN1] = "refin1",
 127         [AD7124_REFIN2] = "refin2",
 128         [AD7124_INT_REF] = "int",
 129         [AD7124_AVDD_REF] = "avdd",
 130 };
 131
 132 struct ad7124_chip_info {
 133         const char *name;
 134         unsigned int chip_id;
 135         unsigned int num_inputs;
 136 };
 137
 138 struct ad7124_channel_config {
 139         enum ad7124_ref_sel refsel;
 140         bool bipolar;
 141         bool buf_positive;
 142         bool buf_negative;
 143         unsigned int ain;
 144         unsigned int vref_mv;
 145         unsigned int pga_bits;
 146         unsigned int odr;
 147         unsigned int filter_type;
 148 };
 149
 150 struct ad7124_state {
 151         const struct ad7124_chip_info *chip_info;
 152         struct ad_sigma_delta sd;
 153         struct ad7124_channel_config *channel_config;
 154         struct regulator *vref[4];
 155         struct clk *mclk;
 156         unsigned int adc_control;
 157         unsigned int num_channels;
 158 };
 159
 160 static const struct iio_chan_spec ad7124_channel_template = {
 161         .type = IIO_VOLTAGE,
 162         .indexed = 1,
 163         .differential = 1,
 164         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 165                 BIT(IIO_CHAN_INFO_SCALE) |
 166                 BIT(IIO_CHAN_INFO_OFFSET) |
 167                 BIT(IIO_CHAN_INFO_SAMP_FREQ) |
 168                 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY),
 169         .scan_type = {
 170                 .sign = 'u',
 171                 .realbits = 24,
 172                 .storagebits = 32,
 173                 .endianness = IIO_BE,
 174         },
 175 };
 176
 177 static struct ad7124_chip_info ad7124_chip_info_tbl[] = {
 178         [ID_AD7124_4] = {
 179                 .name = "ad7124-4",
 180                 .chip_id = CHIPID_AD7124_4,
 181                 .num_inputs = 8,
 182         },
 183         [ID_AD7124_8] = {
 184                 .name = "ad7124-8",
 185                 .chip_id = CHIPID_AD7124_8,
 186                 .num_inputs = 16,
 187         },
 188 };
 189
 190 static int ad7124_find_closest_match(const int *array,
 191                                      unsigned int size, int val)
 192 {
 193         int i, idx;
 194         unsigned int diff_new, diff_old;
 195
 196         diff_old = U32_MAX;
 197         idx = 0;
 198
 199         for (i = 0; i < size; i++) {
 200                 diff_new = abs(val - array[i]);
 201                 if (diff_new < diff_old) {
 202                         diff_old = diff_new;
 203                         idx = i;
 204                 }
 205         }
 206
 207         return idx;
 208 }
 209
 210 static int ad7124_spi_write_mask(struct ad7124_state *st,
 211                                  unsigned int addr,
 212                                  unsigned long mask,
 213                                  unsigned int val,
 214                                  unsigned int bytes)
 215 {
 216         unsigned int readval;
 217         int ret;
 218
 219         ret = ad_sd_read_reg(&st->sd, addr, bytes, &readval);
 220         if (ret < 0)
 221                 return ret;
 222
 223         readval &= ~mask;
 224         readval |= val;
 225
 226         return ad_sd_write_reg(&st->sd, addr, bytes, readval);
 227 }
 228
 229 static int ad7124_set_mode(struct ad_sigma_delta *sd,
 230                            enum ad_sigma_delta_mode mode)
 231 {
 232         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 233
 234         st->adc_control &= ~AD7124_ADC_CTRL_MODE_MSK;
 235         st->adc_control |= AD7124_ADC_CTRL_MODE(mode);
 236
 237         return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 238 }
 239
 240 static int ad7124_set_channel(struct ad_sigma_delta *sd, unsigned int channel)
 241 {
 242         struct ad7124_state *st = container_of(sd, struct ad7124_state, sd);
 243         unsigned int val;
 244
 245         val = st->channel_config[channel].ain | AD7124_CHANNEL_EN(1) |
 246               AD7124_CHANNEL_SETUP(channel);
 247
 248         return ad_sd_write_reg(&st->sd, AD7124_CHANNEL(channel), 2, val);
 249 }
 250
 251 static const struct ad_sigma_delta_info ad7124_sigma_delta_info = {
 252         .set_channel = ad7124_set_channel,
 253         .set_mode = ad7124_set_mode,
 254         .has_registers = true,
 255         .addr_shift = 0,
 256         .read_mask = BIT(6),
 257         .data_reg = AD7124_DATA,
 258         .irq_flags = IRQF_TRIGGER_FALLING,
 259 };
 260
 261 static int ad7124_set_channel_odr(struct ad7124_state *st,
 262                                   unsigned int channel,
 263                                   unsigned int odr)
 264 {
 265         unsigned int fclk, odr_sel_bits;
 266         int ret;
 267
 268         fclk = clk_get_rate(st->mclk);
 269         /*
 270          * FS[10:0] = fCLK / (fADC x 32) where:
 271          * fADC is the output data rate
 272          * fCLK is the master clock frequency
 273          * FS[10:0] are the bits in the filter register
 274          * FS[10:0] can have a value from 1 to 2047
 275          */
 276         odr_sel_bits = DIV_ROUND_CLOSEST(fclk, odr * 32);
 277         if (odr_sel_bits < 1)
 278                 odr_sel_bits = 1;
 279         else if (odr_sel_bits > 2047)
 280                 odr_sel_bits = 2047;
 281
 282         ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
 283                                     AD7124_FILTER_FS_MSK,
 284                                     AD7124_FILTER_FS(odr_sel_bits), 3);
 285         if (ret < 0)
 286                 return ret;
 287         /* fADC = fCLK / (FS[10:0] x 32) */
 288         st->channel_config[channel].odr =
 289                 DIV_ROUND_CLOSEST(fclk, odr_sel_bits * 32);
 290
 291         return 0;
 292 }
 293
 294 static int ad7124_set_channel_gain(struct ad7124_state *st,
 295                                    unsigned int channel,
 296                                    unsigned int gain)
 297 {
 298         unsigned int res;
 299         int ret;
 300
 301         res = ad7124_find_closest_match(ad7124_gain,
 302                                         ARRAY_SIZE(ad7124_gain), gain);
 303         ret = ad7124_spi_write_mask(st, AD7124_CONFIG(channel),
 304                                     AD7124_CONFIG_PGA_MSK,
 305                                     AD7124_CONFIG_PGA(res), 2);
 306         if (ret < 0)
 307                 return ret;
 308
 309         st->channel_config[channel].pga_bits = res;
 310
 311         return 0;
 312 }
 313
 314 static int ad7124_get_3db_filter_freq(struct ad7124_state *st,
 315                                       unsigned int channel)
 316 {
 317         unsigned int fadc;
 318
 319         fadc = st->channel_config[channel].odr;
 320
 321         switch (st->channel_config[channel].filter_type) {
 322         case AD7124_SINC3_FILTER:
 323                 return DIV_ROUND_CLOSEST(fadc * 230, 1000);
 324         case AD7124_SINC4_FILTER:
 325                 return DIV_ROUND_CLOSEST(fadc * 262, 1000);
 326         default:
 327                 return -EINVAL;
 328         }
 329 }
 330
 331 static int ad7124_set_3db_filter_freq(struct ad7124_state *st,
 332                                       unsigned int channel,
 333                                       unsigned int freq)
 334 {
 335         unsigned int sinc4_3db_odr;
 336         unsigned int sinc3_3db_odr;
 337         unsigned int new_filter;
 338         unsigned int new_odr;
 339
 340         sinc4_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 230);
 341         sinc3_3db_odr = DIV_ROUND_CLOSEST(freq * 1000, 262);
 342
 343         if (sinc4_3db_odr > sinc3_3db_odr) {
 344                 new_filter = AD7124_SINC3_FILTER;
 345                 new_odr = sinc4_3db_odr;
 346         } else {
 347                 new_filter = AD7124_SINC4_FILTER;
 348                 new_odr = sinc3_3db_odr;
 349         }
 350
 351         if (st->channel_config[channel].filter_type != new_filter) {
 352                 int ret;
 353
 354                 st->channel_config[channel].filter_type = new_filter;
 355                 ret = ad7124_spi_write_mask(st, AD7124_FILTER(channel),
 356                                             AD7124_FILTER_TYPE_MSK,
 357                                             AD7124_FILTER_TYPE_SEL(new_filter),
 358                                             3);
 359                 if (ret < 0)
 360                         return ret;
 361         }
 362
 363         return ad7124_set_channel_odr(st, channel, new_odr);
 364 }
 365
 366 static int ad7124_read_raw(struct iio_dev *indio_dev,
 367                            struct iio_chan_spec const *chan,
 368                            int *val, int *val2, long info)
 369 {
 370         struct ad7124_state *st = iio_priv(indio_dev);
 371         int idx, ret;
 372
 373         switch (info) {
 374         case IIO_CHAN_INFO_RAW:
 375                 ret = ad_sigma_delta_single_conversion(indio_dev, chan, val);
 376                 if (ret < 0)
 377                         return ret;
 378
 379                 /* After the conversion is performed, disable the channel */
 380                 ret = ad_sd_write_reg(&st->sd,
 381                                       AD7124_CHANNEL(chan->address), 2,
 382                                       st->channel_config[chan->address].ain |
 383                                       AD7124_CHANNEL_EN(0));
 384                 if (ret < 0)
 385                         return ret;
 386
 387                 return IIO_VAL_INT;
 388         case IIO_CHAN_INFO_SCALE:
 389                 idx = st->channel_config[chan->address].pga_bits;
 390                 *val = st->channel_config[chan->address].vref_mv;
 391                 if (st->channel_config[chan->address].bipolar)
 392                         *val2 = chan->scan_type.realbits - 1 + idx;
 393                 else
 394                         *val2 = chan->scan_type.realbits + idx;
 395
 396                 return IIO_VAL_FRACTIONAL_LOG2;
 397         case IIO_CHAN_INFO_OFFSET:
 398                 if (st->channel_config[chan->address].bipolar)
 399                         *val = -(1 << (chan->scan_type.realbits - 1));
 400                 else
 401                         *val = 0;
 402
 403                 return IIO_VAL_INT;
 404         case IIO_CHAN_INFO_SAMP_FREQ:
 405                 *val = st->channel_config[chan->address].odr;
 406
 407                 return IIO_VAL_INT;
 408         case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
 409                 *val = ad7124_get_3db_filter_freq(st, chan->scan_index);
 410                 return IIO_VAL_INT;
 411         default:
 412                 return -EINVAL;
 413         }
 414 }
 415
 416 static int ad7124_write_raw(struct iio_dev *indio_dev,
 417                             struct iio_chan_spec const *chan,
 418                             int val, int val2, long info)
 419 {
 420         struct ad7124_state *st = iio_priv(indio_dev);
 421         unsigned int res, gain, full_scale, vref;
 422
 423         switch (info) {
 424         case IIO_CHAN_INFO_SAMP_FREQ:
 425                 if (val2 != 0)
 426                         return -EINVAL;
 427
 428                 return ad7124_set_channel_odr(st, chan->address, val);
 429         case IIO_CHAN_INFO_SCALE:
 430                 if (val != 0)
 431                         return -EINVAL;
 432
 433                 if (st->channel_config[chan->address].bipolar)
 434                         full_scale = 1 << (chan->scan_type.realbits - 1);
 435                 else
 436                         full_scale = 1 << chan->scan_type.realbits;
 437
 438                 vref = st->channel_config[chan->address].vref_mv * 1000000LL;
 439                 res = DIV_ROUND_CLOSEST(vref, full_scale);
 440                 gain = DIV_ROUND_CLOSEST(res, val2);
 441
 442                 return ad7124_set_channel_gain(st, chan->address, gain);
 443         case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
 444                 if (val2 != 0)
 445                         return -EINVAL;
 446
 447                 return ad7124_set_3db_filter_freq(st, chan->address, val);
 448         default:
 449                 return -EINVAL;
 450         }
 451 }
 452
 453 static int ad7124_reg_access(struct iio_dev *indio_dev,
 454                              unsigned int reg,
 455                              unsigned int writeval,
 456                              unsigned int *readval)
 457 {
 458         struct ad7124_state *st = iio_priv(indio_dev);
 459         int ret;
 460
 461         if (reg >= ARRAY_SIZE(ad7124_reg_size))
 462                 return -EINVAL;
 463
 464         if (readval)
 465                 ret = ad_sd_read_reg(&st->sd, reg, ad7124_reg_size[reg],
 466                                      readval);
 467         else
 468                 ret = ad_sd_write_reg(&st->sd, reg, ad7124_reg_size[reg],
 469                                       writeval);
 470
 471         return ret;
 472 }
 473
 474 static IIO_CONST_ATTR(in_voltage_scale_available,
 475         "0.000001164 0.000002328 0.000004656 0.000009313 0.000018626 0.000037252 0.000074505 0.000149011 0.000298023");
 476
 477 static struct attribute *ad7124_attributes[] = {
 478         &iio_const_attr_in_voltage_scale_available.dev_attr.attr,
 479         NULL,
 480 };
 481
 482 static const struct attribute_group ad7124_attrs_group = {
 483         .attrs = ad7124_attributes,
 484 };
 485
 486 static const struct iio_info ad7124_info = {
 487         .read_raw = ad7124_read_raw,
 488         .write_raw = ad7124_write_raw,
 489         .debugfs_reg_access = &ad7124_reg_access,
 490         .validate_trigger = ad_sd_validate_trigger,
 491         .attrs = &ad7124_attrs_group,
 492 };
 493
 494 static int ad7124_soft_reset(struct ad7124_state *st)
 495 {
 496         unsigned int readval, timeout;
 497         int ret;
 498
 499         ret = ad_sd_reset(&st->sd, 64);
 500         if (ret < 0)
 501                 return ret;
 502
 503         timeout = 100;
 504         do {
 505                 ret = ad_sd_read_reg(&st->sd, AD7124_STATUS, 1, &readval);
 506                 if (ret < 0)
 507                         return ret;
 508
 509                 if (!(readval & AD7124_STATUS_POR_FLAG_MSK))
 510                         return 0;
 511
 512                 /* The AD7124 requires typically 2ms to power up and settle */
 513                 usleep_range(100, 2000);
 514         } while (--timeout);
 515
 516         dev_err(&st->sd.spi->dev, "Soft reset failed\n");
 517
 518         return -EIO;
 519 }
 520
 521 static int ad7124_check_chip_id(struct ad7124_state *st)
 522 {
 523         unsigned int readval, chip_id, silicon_rev;
 524         int ret;
 525
 526         ret = ad_sd_read_reg(&st->sd, AD7124_ID, 1, &readval);
 527         if (ret < 0)
 528                 return ret;
 529
 530         chip_id = AD7124_DEVICE_ID_GET(readval);
 531         silicon_rev = AD7124_SILICON_REV_GET(readval);
 532
 533         if (chip_id != st->chip_info->chip_id) {
 534                 dev_err(&st->sd.spi->dev,
 535                         "Chip ID mismatch: expected %u, got %u\n",
 536                         st->chip_info->chip_id, chip_id);
 537                 return -ENODEV;
 538         }
 539
 540         if (silicon_rev == 0) {
 541                 dev_err(&st->sd.spi->dev,
 542                         "Silicon revision empty. Chip may not be present\n");
 543                 return -ENODEV;
 544         }
 545
 546         return 0;
 547 }
 548
 549 static int ad7124_init_channel_vref(struct ad7124_state *st,
 550                                     unsigned int channel_number)
 551 {
 552         unsigned int refsel = st->channel_config[channel_number].refsel;
 553
 554         switch (refsel) {
 555         case AD7124_REFIN1:
 556         case AD7124_REFIN2:
 557         case AD7124_AVDD_REF:
 558                 if (IS_ERR(st->vref[refsel])) {
 559                         dev_err(&st->sd.spi->dev,
 560                                 "Error, trying to use external voltage reference without a %s regulator.\n",
 561                                 ad7124_ref_names[refsel]);
 562                         return PTR_ERR(st->vref[refsel]);
 563                 }
 564                 st->channel_config[channel_number].vref_mv =
 565                         regulator_get_voltage(st->vref[refsel]);
 566                 /* Conversion from uV to mV */
 567                 st->channel_config[channel_number].vref_mv /= 1000;
 568                 break;
 569         case AD7124_INT_REF:
 570                 st->channel_config[channel_number].vref_mv = 2500;
 571                 st->adc_control &= ~AD7124_ADC_CTRL_REF_EN_MSK;
 572                 st->adc_control |= AD7124_ADC_CTRL_REF_EN(1);
 573                 return ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL,
 574                                       2, st->adc_control);
 575         default:
 576                 dev_err(&st->sd.spi->dev, "Invalid reference %d\n", refsel);
 577                 return -EINVAL;
 578         }
 579
 580         return 0;
 581 }
 582
 583 static int ad7124_of_parse_channel_config(struct iio_dev *indio_dev,
 584                                           struct device_node *np)
 585 {
 586         struct ad7124_state *st = iio_priv(indio_dev);
 587         struct device_node *child;
 588         struct iio_chan_spec *chan;
 589         struct ad7124_channel_config *chan_config;
 590         unsigned int ain[2], channel = 0, tmp;
 591         int ret;
 592
 593         st->num_channels = of_get_available_child_count(np);
 594         if (!st->num_channels) {
 595                 dev_err(indio_dev->dev.parent, "no channel children\n");
 596                 return -ENODEV;
 597         }
 598
 599         chan = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 600                             sizeof(*chan), GFP_KERNEL);
 601         if (!chan)
 602                 return -ENOMEM;
 603
 604         chan_config = devm_kcalloc(indio_dev->dev.parent, st->num_channels,
 605                                    sizeof(*chan_config), GFP_KERNEL);
 606         if (!chan_config)
 607                 return -ENOMEM;
 608
 609         indio_dev->channels = chan;
 610         indio_dev->num_channels = st->num_channels;
 611         st->channel_config = chan_config;
 612
 613         for_each_available_child_of_node(np, child) {
 614                 ret = of_property_read_u32(child, "reg", &channel);
 615                 if (ret)
 616                         goto err;
 617
 618                 if (channel >= indio_dev->num_channels) {
 619                         dev_err(indio_dev->dev.parent,
 620                                 "Channel index >= number of channels\n");
 621                         ret = -EINVAL;
 622                         goto err;
 623                 }
 624
 625                 ret = of_property_read_u32_array(child, "diff-channels",
 626                                                  ain, 2);
 627                 if (ret)
 628                         goto err;
 629
 630                 st->channel_config[channel].ain = AD7124_CHANNEL_AINP(ain[0]) |
 631                                                   AD7124_CHANNEL_AINM(ain[1]);
 632                 st->channel_config[channel].bipolar =
 633                         of_property_read_bool(child, "bipolar");
 634
 635                 ret = of_property_read_u32(child, "adi,reference-select", &tmp);
 636                 if (ret)
 637                         st->channel_config[channel].refsel = AD7124_INT_REF;
 638                 else
 639                         st->channel_config[channel].refsel = tmp;
 640
 641                 st->channel_config[channel].buf_positive =
 642                         of_property_read_bool(child, "adi,buffered-positive");
 643                 st->channel_config[channel].buf_negative =
 644                         of_property_read_bool(child, "adi,buffered-negative");
 645
 646                 chan[channel] = ad7124_channel_template;
 647                 chan[channel].address = channel;
 648                 chan[channel].scan_index = channel;
 649                 chan[channel].channel = ain[0];
 650                 chan[channel].channel2 = ain[1];
 651         }
 652
 653         return 0;
 654 err:
 655         of_node_put(child);
 656
 657         return ret;
 658 }
 659
 660 static int ad7124_setup(struct ad7124_state *st)
 661 {
 662         unsigned int val, fclk, power_mode;
 663         int i, ret, tmp;
 664
 665         fclk = clk_get_rate(st->mclk);
 666         if (!fclk)
 667                 return -EINVAL;
 668
 669         /* The power mode changes the master clock frequency */
 670         power_mode = ad7124_find_closest_match(ad7124_master_clk_freq_hz,
 671                                         ARRAY_SIZE(ad7124_master_clk_freq_hz),
 672                                         fclk);
 673         if (fclk != ad7124_master_clk_freq_hz[power_mode]) {
 674                 ret = clk_set_rate(st->mclk, fclk);
 675                 if (ret)
 676                         return ret;
 677         }
 678
 679         /* Set the power mode */
 680         st->adc_control &= ~AD7124_ADC_CTRL_PWR_MSK;
 681         st->adc_control |= AD7124_ADC_CTRL_PWR(power_mode);
 682         ret = ad_sd_write_reg(&st->sd, AD7124_ADC_CONTROL, 2, st->adc_control);
 683         if (ret < 0)
 684                 return ret;
 685
 686         for (i = 0; i < st->num_channels; i++) {
 687                 val = st->channel_config[i].ain | AD7124_CHANNEL_SETUP(i);
 688                 ret = ad_sd_write_reg(&st->sd, AD7124_CHANNEL(i), 2, val);
 689                 if (ret < 0)
 690                         return ret;
 691
 692                 ret = ad7124_init_channel_vref(st, i);
 693                 if (ret < 0)
 694                         return ret;
 695
 696                 tmp = (st->channel_config[i].buf_positive << 1)  +
 697                         st->channel_config[i].buf_negative;
 698
 699                 val = AD7124_CONFIG_BIPOLAR(st->channel_config[i].bipolar) |
 700                       AD7124_CONFIG_REF_SEL(st->channel_config[i].refsel) |
 701                       AD7124_CONFIG_IN_BUFF(tmp);
 702                 ret = ad_sd_write_reg(&st->sd, AD7124_CONFIG(i), 2, val);
 703                 if (ret < 0)
 704                         return ret;
 705                 /*
 706                  * 9.38 SPS is the minimum output data rate supported
 707                  * regardless of the selected power mode. Round it up to 10 and
 708                  * set all the enabled channels to this default value.
 709                  */
 710                 ret = ad7124_set_channel_odr(st, i, 10);
 711         }
 712
 713         return ret;
 714 }
 715
 716 static void ad7124_reg_disable(void *r)
 717 {
 718         regulator_disable(r);
 719 }
 720
 721 static int ad7124_probe(struct spi_device *spi)
 722 {
 723         const struct ad7124_chip_info *info;
 724         struct ad7124_state *st;
 725         struct iio_dev *indio_dev;
 726         int i, ret;
 727
 728         info = of_device_get_match_data(&spi->dev);
 729         if (!info)
 730                 return -ENODEV;
 731
 732         indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st));
 733         if (!indio_dev)
 734                 return -ENOMEM;
 735
 736         st = iio_priv(indio_dev);
 737
 738         st->chip_info = info;
 739
 740         ad_sd_init(&st->sd, indio_dev, spi, &ad7124_sigma_delta_info);
 741
 742         spi_set_drvdata(spi, indio_dev);
 743
 744         indio_dev->name = st->chip_info->name;
 745         indio_dev->modes = INDIO_DIRECT_MODE;
 746         indio_dev->info = &ad7124_info;
 747
 748         ret = ad7124_of_parse_channel_config(indio_dev, spi->dev.of_node);
 749         if (ret < 0)
 750                 return ret;
 751
 752         for (i = 0; i < ARRAY_SIZE(st->vref); i++) {
 753                 if (i == AD7124_INT_REF)
 754                         continue;
 755
 756                 st->vref[i] = devm_regulator_get_optional(&spi->dev,
 757                                                 ad7124_ref_names[i]);
 758                 if (PTR_ERR(st->vref[i]) == -ENODEV)
 759                         continue;
 760                 else if (IS_ERR(st->vref[i]))
 761                         return PTR_ERR(st->vref[i]);
 762
 763                 ret = regulator_enable(st->vref[i]);
 764                 if (ret)
 765                         return ret;
 766
 767                 ret = devm_add_action_or_reset(&spi->dev, ad7124_reg_disable,
 768                                                st->vref[i]);
 769                 if (ret)
 770                         return ret;
 771         }
 772
 773         st->mclk = devm_clk_get(&spi->dev, "mclk");
 774         if (IS_ERR(st->mclk))
 775                 return PTR_ERR(st->mclk);
 776
 777         ret = clk_prepare_enable(st->mclk);
 778         if (ret < 0)
 779                 return ret;
 780
 781         ret = ad7124_soft_reset(st);
 782         if (ret < 0)
 783                 goto error_clk_disable_unprepare;
 784
 785         ret = ad7124_check_chip_id(st);
 786         if (ret)
 787                 goto error_clk_disable_unprepare;
 788
 789         ret = ad7124_setup(st);
 790         if (ret < 0)
 791                 goto error_clk_disable_unprepare;
 792
 793         ret = ad_sd_setup_buffer_and_trigger(indio_dev);
 794         if (ret < 0)
 795                 goto error_clk_disable_unprepare;
 796
 797         ret = iio_device_register(indio_dev);
 798         if (ret < 0) {
 799                 dev_err(&spi->dev, "Failed to register iio device\n");
 800                 goto error_remove_trigger;
 801         }
 802
 803         return 0;
 804
 805 error_remove_trigger:
 806         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 807 error_clk_disable_unprepare:
 808         clk_disable_unprepare(st->mclk);
 809
 810         return ret;
 811 }
 812
 813 static int ad7124_remove(struct spi_device *spi)
 814 {
 815         struct iio_dev *indio_dev = spi_get_drvdata(spi);
 816         struct ad7124_state *st = iio_priv(indio_dev);
 817
 818         iio_device_unregister(indio_dev);
 819         ad_sd_cleanup_buffer_and_trigger(indio_dev);
 820         clk_disable_unprepare(st->mclk);
 821
 822         return 0;
 823 }
 824
 825 static const struct of_device_id ad7124_of_match[] = {
 826         { .compatible = "adi,ad7124-4",
 827                 .data = &ad7124_chip_info_tbl[ID_AD7124_4], },
 828         { .compatible = "adi,ad7124-8",
 829                 .data = &ad7124_chip_info_tbl[ID_AD7124_8], },
 830         { },
 831 };
 832 MODULE_DEVICE_TABLE(of, ad7124_of_match);
 833
 834 static struct spi_driver ad71124_driver = {
 835         .driver = {
 836                 .name = "ad7124",
 837                 .of_match_table = ad7124_of_match,
 838         },
 839         .probe = ad7124_probe,
 840         .remove = ad7124_remove,
 841 };
 842 module_spi_driver(ad71124_driver);
 843
 844 MODULE_AUTHOR("Stefan Popa <stefan.popa@analog.com>");
 845 MODULE_DESCRIPTION("Analog Devices AD7124 SPI driver");
 846 MODULE_LICENSE("GPL");