1 // SPDX-License-Identifier: GPL-2.0-only
3 * Murata SCA3300 3-axis industrial accelerometer
5 * Copyright (c) 2021 Vaisala Oyj. All rights reserved.
8 #include <linux/bitops.h>
9 #include <linux/crc8.h>
10 #include <linux/delay.h>
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/spi/spi.h>
15 #include <asm/unaligned.h>
17 #include <linux/iio/buffer.h>
18 #include <linux/iio/iio.h>
19 #include <linux/iio/sysfs.h>
20 #include <linux/iio/trigger_consumer.h>
21 #include <linux/iio/triggered_buffer.h>
23 #define SCA3300_ALIAS "sca3300"
25 #define SCA3300_CRC8_POLYNOMIAL 0x1d
27 /* Device mode register */
28 #define SCA3300_REG_MODE 0xd
29 #define SCA3300_MODE_SW_RESET 0x20
31 /* Last register in map */
32 #define SCA3300_REG_SELBANK 0x1f
34 /* Device status and mask */
35 #define SCA3300_REG_STATUS 0x6
36 #define SCA3300_STATUS_MASK GENMASK(8, 0)
39 #define SCA3300_REG_WHOAMI 0x10
40 #define SCA3300_WHOAMI_ID 0x51
42 /* Device return status and mask */
43 #define SCA3300_VALUE_RS_ERROR 0x3
44 #define SCA3300_MASK_RS_STATUS GENMASK(1, 0)
46 enum sca3300_scan_indexes {
54 #define SCA3300_ACCEL_CHANNEL(index, reg, axis) { \
58 .channel2 = IIO_MOD_##axis, \
59 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
60 .info_mask_shared_by_type = \
61 BIT(IIO_CHAN_INFO_SCALE) | \
62 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
63 .info_mask_shared_by_type_available = \
64 BIT(IIO_CHAN_INFO_SCALE) | \
65 BIT(IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY), \
66 .scan_index = index, \
71 .endianness = IIO_CPU, \
75 static const struct iio_chan_spec sca3300_channels[] = {
76 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_X, 0x1, X),
77 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Y, 0x2, Y),
78 SCA3300_ACCEL_CHANNEL(SCA3300_ACC_Z, 0x3, Z),
82 .scan_index = SCA3300_TEMP,
83 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),
88 .endianness = IIO_CPU,
91 IIO_CHAN_SOFT_TIMESTAMP(4),
94 static const int sca3300_lp_freq[] = {70, 70, 70, 10};
95 static const int sca3300_accel_scale[][2] = {{0, 370}, {0, 741}, {0, 185}, {0, 185}};
97 static const unsigned long sca3300_scan_masks[] = {
98 BIT(SCA3300_ACC_X) | BIT(SCA3300_ACC_Y) | BIT(SCA3300_ACC_Z) |
104 * struct sca3300_data - device data
105 * @spi: SPI device structure
106 * @lock: Data buffer lock
107 * @scan: Triggered buffer. Four channel 16-bit data + 64-bit timestamp
108 * @txbuf: Transmit buffer
109 * @rxbuf: Receive buffer
111 struct sca3300_data {
112 struct spi_device *spi;
116 s64 ts __aligned(sizeof(s64));
118 u8 txbuf[4] ____cacheline_aligned;
122 DECLARE_CRC8_TABLE(sca3300_crc_table);
124 static int sca3300_transfer(struct sca3300_data *sca_data, int *val)
126 /* Consecutive requests min. 10 us delay (Datasheet section 5.1.2) */
127 struct spi_delay delay = { .value = 10, .unit = SPI_DELAY_UNIT_USECS };
131 struct spi_transfer xfers[2] = {
133 .tx_buf = sca_data->txbuf,
134 .len = ARRAY_SIZE(sca_data->txbuf),
139 .rx_buf = sca_data->rxbuf,
140 .len = ARRAY_SIZE(sca_data->rxbuf),
145 /* inverted crc value as described in device data sheet */
146 crc = ~crc8(sca3300_crc_table, &sca_data->txbuf[0], 3, CRC8_INIT_VALUE);
147 sca_data->txbuf[3] = crc;
149 ret = spi_sync_transfer(sca_data->spi, xfers, ARRAY_SIZE(xfers));
151 dev_err(&sca_data->spi->dev,
152 "transfer error, error: %d\n", ret);
156 crc = ~crc8(sca3300_crc_table, &sca_data->rxbuf[0], 3, CRC8_INIT_VALUE);
157 if (sca_data->rxbuf[3] != crc) {
158 dev_err(&sca_data->spi->dev, "CRC checksum mismatch");
162 /* get return status */
163 rs = sca_data->rxbuf[0] & SCA3300_MASK_RS_STATUS;
164 if (rs == SCA3300_VALUE_RS_ERROR)
167 *val = sign_extend32(get_unaligned_be16(&sca_data->rxbuf[1]), 15);
172 static int sca3300_error_handler(struct sca3300_data *sca_data)
177 mutex_lock(&sca_data->lock);
178 sca_data->txbuf[0] = SCA3300_REG_STATUS << 2;
179 ret = sca3300_transfer(sca_data, &val);
180 mutex_unlock(&sca_data->lock);
182 * Return status error is cleared after reading status register once,
183 * expect EINVAL here.
185 if (ret != -EINVAL) {
186 dev_err(&sca_data->spi->dev,
187 "error reading device status: %d\n", ret);
191 dev_err(&sca_data->spi->dev, "device status: 0x%lx\n",
192 val & SCA3300_STATUS_MASK);
197 static int sca3300_read_reg(struct sca3300_data *sca_data, u8 reg, int *val)
201 mutex_lock(&sca_data->lock);
202 sca_data->txbuf[0] = reg << 2;
203 ret = sca3300_transfer(sca_data, val);
204 mutex_unlock(&sca_data->lock);
208 return sca3300_error_handler(sca_data);
211 static int sca3300_write_reg(struct sca3300_data *sca_data, u8 reg, int val)
216 mutex_lock(&sca_data->lock);
217 /* BIT(7) for write operation */
218 sca_data->txbuf[0] = BIT(7) | (reg << 2);
219 put_unaligned_be16(val, &sca_data->txbuf[1]);
220 ret = sca3300_transfer(sca_data, ®_val);
221 mutex_unlock(&sca_data->lock);
225 return sca3300_error_handler(sca_data);
228 static int sca3300_write_raw(struct iio_dev *indio_dev,
229 struct iio_chan_spec const *chan,
230 int val, int val2, long mask)
232 struct sca3300_data *data = iio_priv(indio_dev);
238 case IIO_CHAN_INFO_SCALE:
242 for (i = 0; i < ARRAY_SIZE(sca3300_accel_scale); i++) {
243 if (val2 == sca3300_accel_scale[i][1])
244 return sca3300_write_reg(data, SCA3300_REG_MODE, i);
248 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
249 ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val);
252 /* freq. change is possible only for mode 3 and 4 */
253 if (reg_val == 2 && val == sca3300_lp_freq[3])
254 return sca3300_write_reg(data, SCA3300_REG_MODE, 3);
255 if (reg_val == 3 && val == sca3300_lp_freq[2])
256 return sca3300_write_reg(data, SCA3300_REG_MODE, 2);
263 static int sca3300_read_raw(struct iio_dev *indio_dev,
264 struct iio_chan_spec const *chan,
265 int *val, int *val2, long mask)
267 struct sca3300_data *data = iio_priv(indio_dev);
272 case IIO_CHAN_INFO_RAW:
273 ret = sca3300_read_reg(data, chan->address, val);
277 case IIO_CHAN_INFO_SCALE:
278 ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val);
282 *val2 = sca3300_accel_scale[reg_val][1];
283 return IIO_VAL_INT_PLUS_MICRO;
284 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
285 ret = sca3300_read_reg(data, SCA3300_REG_MODE, ®_val);
288 *val = sca3300_lp_freq[reg_val];
295 static irqreturn_t sca3300_trigger_handler(int irq, void *p)
297 struct iio_poll_func *pf = p;
298 struct iio_dev *indio_dev = pf->indio_dev;
299 struct sca3300_data *data = iio_priv(indio_dev);
300 int bit, ret, val, i = 0;
302 for_each_set_bit(bit, indio_dev->active_scan_mask,
303 indio_dev->masklength) {
304 ret = sca3300_read_reg(data, sca3300_channels[bit].address,
307 dev_err_ratelimited(&data->spi->dev,
308 "failed to read register, error: %d\n", ret);
309 /* handled, but bailing out due to errors */
312 data->scan.channels[i++] = val;
315 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
316 iio_get_time_ns(indio_dev));
318 iio_trigger_notify_done(indio_dev->trig);
324 * sca3300_init - Device init sequence. See datasheet rev 2 section
325 * 4.2 Start-Up Sequence for details.
327 static int sca3300_init(struct sca3300_data *sca_data,
328 struct iio_dev *indio_dev)
333 ret = sca3300_write_reg(sca_data, SCA3300_REG_MODE,
334 SCA3300_MODE_SW_RESET);
339 * Wait 1ms after SW-reset command.
340 * Wait 15ms for settling of signal paths.
342 usleep_range(16e3, 50e3);
344 ret = sca3300_read_reg(sca_data, SCA3300_REG_WHOAMI, &value);
348 if (value != SCA3300_WHOAMI_ID) {
349 dev_err(&sca_data->spi->dev,
350 "device id not expected value, %d != %u\n",
351 value, SCA3300_WHOAMI_ID);
357 static int sca3300_debugfs_reg_access(struct iio_dev *indio_dev,
358 unsigned int reg, unsigned int writeval,
359 unsigned int *readval)
361 struct sca3300_data *data = iio_priv(indio_dev);
365 if (reg > SCA3300_REG_SELBANK)
369 return sca3300_write_reg(data, reg, writeval);
371 ret = sca3300_read_reg(data, reg, &value);
380 static int sca3300_read_avail(struct iio_dev *indio_dev,
381 struct iio_chan_spec const *chan,
382 const int **vals, int *type, int *length,
386 case IIO_CHAN_INFO_SCALE:
387 *vals = (const int *)sca3300_accel_scale;
388 *length = ARRAY_SIZE(sca3300_accel_scale) * 2 - 2;
389 *type = IIO_VAL_INT_PLUS_MICRO;
390 return IIO_AVAIL_LIST;
391 case IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY:
392 *vals = &sca3300_lp_freq[2];
395 return IIO_AVAIL_LIST;
401 static const struct iio_info sca3300_info = {
402 .read_raw = sca3300_read_raw,
403 .write_raw = sca3300_write_raw,
404 .debugfs_reg_access = &sca3300_debugfs_reg_access,
405 .read_avail = sca3300_read_avail,
408 static int sca3300_probe(struct spi_device *spi)
410 struct sca3300_data *sca_data;
411 struct iio_dev *indio_dev;
414 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*sca_data));
418 sca_data = iio_priv(indio_dev);
419 mutex_init(&sca_data->lock);
422 crc8_populate_msb(sca3300_crc_table, SCA3300_CRC8_POLYNOMIAL);
424 indio_dev->info = &sca3300_info;
425 indio_dev->name = SCA3300_ALIAS;
426 indio_dev->modes = INDIO_DIRECT_MODE;
427 indio_dev->channels = sca3300_channels;
428 indio_dev->num_channels = ARRAY_SIZE(sca3300_channels);
429 indio_dev->available_scan_masks = sca3300_scan_masks;
431 ret = sca3300_init(sca_data, indio_dev);
433 dev_err(&spi->dev, "failed to init device, error: %d\n", ret);
437 ret = devm_iio_triggered_buffer_setup(&spi->dev, indio_dev,
438 iio_pollfunc_store_time,
439 sca3300_trigger_handler, NULL);
442 "iio triggered buffer setup failed, error: %d\n", ret);
446 ret = devm_iio_device_register(&spi->dev, indio_dev);
448 dev_err(&spi->dev, "iio device register failed, error: %d\n",
455 static const struct of_device_id sca3300_dt_ids[] = {
456 { .compatible = "murata,sca3300"},
459 MODULE_DEVICE_TABLE(of, sca3300_dt_ids);
461 static struct spi_driver sca3300_driver = {
463 .name = SCA3300_ALIAS,
464 .of_match_table = sca3300_dt_ids,
466 .probe = sca3300_probe,
468 module_spi_driver(sca3300_driver);
470 MODULE_AUTHOR("Tomas Melin <tomas.melin@vaisala.com>");
471 MODULE_DESCRIPTION("Murata SCA3300 SPI Accelerometer");
472 MODULE_LICENSE("GPL v2");