2 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
4 * device name digital output 7-bit I2C slave address (pin selectable)
5 * ---------------------------------------------------------------------
6 * MMA8451Q 14 bit 0x1c / 0x1d
7 * MMA8452Q 12 bit 0x1c / 0x1d
8 * MMA8453Q 10 bit 0x1c / 0x1d
9 * MMA8652FC 12 bit 0x1d
10 * MMA8653FC 10 bit 0x1d
11 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
13 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
14 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
16 * This file is subject to the terms and conditions of version 2 of
17 * the GNU General Public License. See the file COPYING in the main
18 * directory of this archive for more details.
20 * TODO: orientation events
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/events.h>
32 #include <linux/delay.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/pm_runtime.h>
37 #define MMA8452_STATUS 0x00
38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
39 #define MMA8452_OUT_X 0x01 /* MSB first */
40 #define MMA8452_OUT_Y 0x03
41 #define MMA8452_OUT_Z 0x05
42 #define MMA8452_INT_SRC 0x0c
43 #define MMA8452_WHO_AM_I 0x0d
44 #define MMA8452_DATA_CFG 0x0e
45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
46 #define MMA8452_DATA_CFG_FS_2G 0
47 #define MMA8452_DATA_CFG_FS_4G 1
48 #define MMA8452_DATA_CFG_FS_8G 2
49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
50 #define MMA8452_HP_FILTER_CUTOFF 0x0f
51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
52 #define MMA8452_FF_MT_CFG 0x15
53 #define MMA8452_FF_MT_CFG_OAE BIT(6)
54 #define MMA8452_FF_MT_CFG_ELE BIT(7)
55 #define MMA8452_FF_MT_SRC 0x16
56 #define MMA8452_FF_MT_SRC_XHE BIT(1)
57 #define MMA8452_FF_MT_SRC_YHE BIT(3)
58 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
59 #define MMA8452_FF_MT_THS 0x17
60 #define MMA8452_FF_MT_THS_MASK 0x7f
61 #define MMA8452_FF_MT_COUNT 0x18
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
65 #define MMA8452_TRANSIENT_SRC 0x1e
66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
69 #define MMA8452_TRANSIENT_THS 0x1f
70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
71 #define MMA8452_TRANSIENT_COUNT 0x20
72 #define MMA8452_CTRL_REG1 0x2a
73 #define MMA8452_CTRL_ACTIVE BIT(0)
74 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
75 #define MMA8452_CTRL_DR_SHIFT 3
76 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
77 #define MMA8452_CTRL_REG2 0x2b
78 #define MMA8452_CTRL_REG2_RST BIT(6)
79 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
80 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
81 #define MMA8452_CTRL_REG4 0x2d
82 #define MMA8452_CTRL_REG5 0x2e
83 #define MMA8452_OFF_X 0x2f
84 #define MMA8452_OFF_Y 0x30
85 #define MMA8452_OFF_Z 0x31
87 #define MMA8452_MAX_REG 0x31
89 #define MMA8452_INT_DRDY BIT(0)
90 #define MMA8452_INT_FF_MT BIT(2)
91 #define MMA8452_INT_TRANS BIT(5)
93 #define MMA8451_DEVICE_ID 0x1a
94 #define MMA8452_DEVICE_ID 0x2a
95 #define MMA8453_DEVICE_ID 0x3a
96 #define MMA8652_DEVICE_ID 0x4a
97 #define MMA8653_DEVICE_ID 0x5a
98 #define FXLS8471_DEVICE_ID 0x6a
100 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
102 struct mma8452_data {
103 struct i2c_client *client;
107 const struct mma_chip_info *chip_info;
109 /* Ensure correct alignment of time stamp when present */
117 * struct mma_chip_info - chip specific data
118 * @chip_id: WHO_AM_I register's value
119 * @channels: struct iio_chan_spec matching the device's
121 * @num_channels: number of channels
122 * @mma_scales: scale factors for converting register values
123 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
124 * per mode: m/s^2 and micro m/s^2
125 * @ev_cfg: event config register address
126 * @ev_cfg_ele: latch bit in event config register
127 * @ev_cfg_chan_shift: number of the bit to enable events in X
128 * direction; in event config register
129 * @ev_src: event source register address
130 * @ev_src_xe: bit in event source register that indicates
131 * an event in X direction
132 * @ev_src_ye: bit in event source register that indicates
133 * an event in Y direction
134 * @ev_src_ze: bit in event source register that indicates
135 * an event in Z direction
136 * @ev_ths: event threshold register address
137 * @ev_ths_mask: mask for the threshold value
138 * @ev_count: event count (period) register address
140 * Since not all chips supported by the driver support comparing high pass
141 * filtered data for events (interrupts), different interrupt sources are
142 * used for different chips and the relevant registers are included here.
144 struct mma_chip_info {
146 const struct iio_chan_spec *channels;
148 const int mma_scales[3][2];
151 u8 ev_cfg_chan_shift;
168 static int mma8452_drdy(struct mma8452_data *data)
172 while (tries-- > 0) {
173 int ret = i2c_smbus_read_byte_data(data->client,
177 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
183 dev_err(&data->client->dev, "data not ready\n");
188 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
194 ret = pm_runtime_get_sync(&client->dev);
196 pm_runtime_mark_last_busy(&client->dev);
197 ret = pm_runtime_put_autosuspend(&client->dev);
201 dev_err(&client->dev,
202 "failed to change power state to %d\n", on);
204 pm_runtime_put_noidle(&client->dev);
213 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
215 int ret = mma8452_drdy(data);
220 ret = mma8452_set_runtime_pm_state(data->client, true);
224 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
225 3 * sizeof(__be16), (u8 *)buf);
227 ret = mma8452_set_runtime_pm_state(data->client, false);
232 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
238 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
239 vals[n][0], vals[n][1]);
241 /* replace trailing space by newline */
247 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
251 if (val == vals[n][0] && val2 == vals[n][1])
257 static int mma8452_get_odr_index(struct mma8452_data *data)
259 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
260 MMA8452_CTRL_DR_SHIFT;
263 static const int mma8452_samp_freq[8][2] = {
264 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
265 {6, 250000}, {1, 560000}
268 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
269 static const int mma8452_transient_time_step_us[4][8] = {
270 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
271 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
272 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
273 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
276 /* Datasheet table "High-Pass Filter Cutoff Options" */
277 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
279 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
280 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
281 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
282 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
283 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
284 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
285 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
286 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
288 { /* low noise low power */
289 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
290 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
291 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
292 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
293 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
294 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
295 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
296 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
298 { /* high resolution */
299 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
300 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
301 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
302 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
303 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
304 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
305 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
306 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
309 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
310 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
311 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
312 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
313 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
314 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
315 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
316 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
320 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
321 static const u16 mma8452_os_ratio[4][8] = {
322 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
323 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
324 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
325 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
326 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
329 static int mma8452_get_power_mode(struct mma8452_data *data)
333 reg = i2c_smbus_read_byte_data(data->client,
338 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
339 MMA8452_CTRL_REG2_MODS_SHIFT);
342 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
343 struct device_attribute *attr,
346 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
347 ARRAY_SIZE(mma8452_samp_freq));
350 static ssize_t mma8452_show_scale_avail(struct device *dev,
351 struct device_attribute *attr,
354 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
355 to_i2c_client(dev)));
357 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
358 ARRAY_SIZE(data->chip_info->mma_scales));
361 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
362 struct device_attribute *attr,
365 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
366 struct mma8452_data *data = iio_priv(indio_dev);
369 i = mma8452_get_odr_index(data);
370 j = mma8452_get_power_mode(data);
374 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
375 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
378 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
379 struct device_attribute *attr,
382 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
383 struct mma8452_data *data = iio_priv(indio_dev);
384 int i = mma8452_get_odr_index(data);
389 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
390 if (val == mma8452_os_ratio[j][i])
393 val = mma8452_os_ratio[j][i];
395 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
402 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
403 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
404 mma8452_show_scale_avail, NULL, 0);
405 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
406 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
407 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO,
408 mma8452_show_os_ratio_avail, NULL, 0);
410 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
413 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
414 ARRAY_SIZE(mma8452_samp_freq),
418 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
420 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
421 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
424 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
429 i = mma8452_get_odr_index(data);
430 j = mma8452_get_power_mode(data);
434 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
435 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
438 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
442 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
446 i = mma8452_get_odr_index(data);
447 j = mma8452_get_power_mode(data);
451 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
452 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
453 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
458 static int mma8452_read_raw(struct iio_dev *indio_dev,
459 struct iio_chan_spec const *chan,
460 int *val, int *val2, long mask)
462 struct mma8452_data *data = iio_priv(indio_dev);
467 case IIO_CHAN_INFO_RAW:
468 if (iio_buffer_enabled(indio_dev))
471 mutex_lock(&data->lock);
472 ret = mma8452_read(data, buffer);
473 mutex_unlock(&data->lock);
477 *val = sign_extend32(be16_to_cpu(
478 buffer[chan->scan_index]) >> chan->scan_type.shift,
479 chan->scan_type.realbits - 1);
482 case IIO_CHAN_INFO_SCALE:
483 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
484 *val = data->chip_info->mma_scales[i][0];
485 *val2 = data->chip_info->mma_scales[i][1];
487 return IIO_VAL_INT_PLUS_MICRO;
488 case IIO_CHAN_INFO_SAMP_FREQ:
489 i = mma8452_get_odr_index(data);
490 *val = mma8452_samp_freq[i][0];
491 *val2 = mma8452_samp_freq[i][1];
493 return IIO_VAL_INT_PLUS_MICRO;
494 case IIO_CHAN_INFO_CALIBBIAS:
495 ret = i2c_smbus_read_byte_data(data->client,
501 *val = sign_extend32(ret, 7);
504 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
505 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
506 ret = mma8452_read_hp_filter(data, val, val2);
514 return IIO_VAL_INT_PLUS_MICRO;
515 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
516 ret = mma8452_get_power_mode(data);
520 i = mma8452_get_odr_index(data);
522 *val = mma8452_os_ratio[ret][i];
529 static int mma8452_standby(struct mma8452_data *data)
531 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
532 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
535 static int mma8452_active(struct mma8452_data *data)
537 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
541 /* returns >0 if active, 0 if in standby and <0 on error */
542 static int mma8452_is_active(struct mma8452_data *data)
546 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
550 return reg & MMA8452_CTRL_ACTIVE;
553 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
558 mutex_lock(&data->lock);
560 is_active = mma8452_is_active(data);
566 /* config can only be changed when in standby */
568 ret = mma8452_standby(data);
573 ret = i2c_smbus_write_byte_data(data->client, reg, val);
578 ret = mma8452_active(data);
585 mutex_unlock(&data->lock);
590 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
594 reg = i2c_smbus_read_byte_data(data->client,
599 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
600 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
602 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
605 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
606 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
609 const struct mma_chip_info *chip = data->chip_info;
611 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
615 return !(val & MMA8452_FF_MT_CFG_OAE);
618 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
621 const struct mma_chip_info *chip = data->chip_info;
623 if ((state && mma8452_freefall_mode_enabled(data)) ||
624 (!state && !(mma8452_freefall_mode_enabled(data))))
627 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
632 val |= BIT(idx_x + chip->ev_cfg_chan_shift);
633 val |= BIT(idx_y + chip->ev_cfg_chan_shift);
634 val |= BIT(idx_z + chip->ev_cfg_chan_shift);
635 val &= ~MMA8452_FF_MT_CFG_OAE;
637 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
638 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
639 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
640 val |= MMA8452_FF_MT_CFG_OAE;
643 return mma8452_change_config(data, chip->ev_cfg, val);
646 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
651 i = mma8452_get_hp_filter_index(data, val, val2);
655 reg = i2c_smbus_read_byte_data(data->client,
656 MMA8452_HP_FILTER_CUTOFF);
660 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
663 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
666 static int mma8452_write_raw(struct iio_dev *indio_dev,
667 struct iio_chan_spec const *chan,
668 int val, int val2, long mask)
670 struct mma8452_data *data = iio_priv(indio_dev);
673 if (iio_buffer_enabled(indio_dev))
677 case IIO_CHAN_INFO_SAMP_FREQ:
678 i = mma8452_get_samp_freq_index(data, val, val2);
682 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
683 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
685 return mma8452_change_config(data, MMA8452_CTRL_REG1,
687 case IIO_CHAN_INFO_SCALE:
688 i = mma8452_get_scale_index(data, val, val2);
692 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
695 return mma8452_change_config(data, MMA8452_DATA_CFG,
697 case IIO_CHAN_INFO_CALIBBIAS:
698 if (val < -128 || val > 127)
701 return mma8452_change_config(data,
702 MMA8452_OFF_X + chan->scan_index,
705 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
706 if (val == 0 && val2 == 0) {
707 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
709 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
710 ret = mma8452_set_hp_filter_frequency(data, val, val2);
715 return mma8452_change_config(data, MMA8452_DATA_CFG,
718 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
719 ret = mma8452_get_odr_index(data);
721 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
722 if (mma8452_os_ratio[i][ret] == val)
723 return mma8452_set_power_mode(data, i);
731 static int mma8452_read_thresh(struct iio_dev *indio_dev,
732 const struct iio_chan_spec *chan,
733 enum iio_event_type type,
734 enum iio_event_direction dir,
735 enum iio_event_info info,
738 struct mma8452_data *data = iio_priv(indio_dev);
739 int ret, us, power_mode;
742 case IIO_EV_INFO_VALUE:
743 ret = i2c_smbus_read_byte_data(data->client,
744 data->chip_info->ev_ths);
748 *val = ret & data->chip_info->ev_ths_mask;
752 case IIO_EV_INFO_PERIOD:
753 ret = i2c_smbus_read_byte_data(data->client,
754 data->chip_info->ev_count);
758 power_mode = mma8452_get_power_mode(data);
762 us = ret * mma8452_transient_time_step_us[power_mode][
763 mma8452_get_odr_index(data)];
764 *val = us / USEC_PER_SEC;
765 *val2 = us % USEC_PER_SEC;
767 return IIO_VAL_INT_PLUS_MICRO;
769 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
770 ret = i2c_smbus_read_byte_data(data->client,
771 MMA8452_TRANSIENT_CFG);
775 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
779 ret = mma8452_read_hp_filter(data, val, val2);
784 return IIO_VAL_INT_PLUS_MICRO;
791 static int mma8452_write_thresh(struct iio_dev *indio_dev,
792 const struct iio_chan_spec *chan,
793 enum iio_event_type type,
794 enum iio_event_direction dir,
795 enum iio_event_info info,
798 struct mma8452_data *data = iio_priv(indio_dev);
802 case IIO_EV_INFO_VALUE:
803 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
806 return mma8452_change_config(data, data->chip_info->ev_ths,
809 case IIO_EV_INFO_PERIOD:
810 ret = mma8452_get_power_mode(data);
814 steps = (val * USEC_PER_SEC + val2) /
815 mma8452_transient_time_step_us[ret][
816 mma8452_get_odr_index(data)];
818 if (steps < 0 || steps > 0xff)
821 return mma8452_change_config(data, data->chip_info->ev_count,
824 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
825 reg = i2c_smbus_read_byte_data(data->client,
826 MMA8452_TRANSIENT_CFG);
830 if (val == 0 && val2 == 0) {
831 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
833 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
834 ret = mma8452_set_hp_filter_frequency(data, val, val2);
839 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
846 static int mma8452_read_event_config(struct iio_dev *indio_dev,
847 const struct iio_chan_spec *chan,
848 enum iio_event_type type,
849 enum iio_event_direction dir)
851 struct mma8452_data *data = iio_priv(indio_dev);
852 const struct mma_chip_info *chip = data->chip_info;
856 case IIO_EV_DIR_FALLING:
857 return mma8452_freefall_mode_enabled(data);
858 case IIO_EV_DIR_RISING:
859 if (mma8452_freefall_mode_enabled(data))
862 ret = i2c_smbus_read_byte_data(data->client,
863 data->chip_info->ev_cfg);
867 return !!(ret & BIT(chan->scan_index +
868 chip->ev_cfg_chan_shift));
874 static int mma8452_write_event_config(struct iio_dev *indio_dev,
875 const struct iio_chan_spec *chan,
876 enum iio_event_type type,
877 enum iio_event_direction dir,
880 struct mma8452_data *data = iio_priv(indio_dev);
881 const struct mma_chip_info *chip = data->chip_info;
884 ret = mma8452_set_runtime_pm_state(data->client, state);
889 case IIO_EV_DIR_FALLING:
890 return mma8452_set_freefall_mode(data, state);
891 case IIO_EV_DIR_RISING:
892 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
897 if (mma8452_freefall_mode_enabled(data)) {
898 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
899 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
900 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
901 val |= MMA8452_FF_MT_CFG_OAE;
903 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
905 if (mma8452_freefall_mode_enabled(data))
908 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
911 val |= chip->ev_cfg_ele;
913 return mma8452_change_config(data, chip->ev_cfg, val);
919 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
921 struct mma8452_data *data = iio_priv(indio_dev);
922 s64 ts = iio_get_time_ns(indio_dev);
925 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
929 if (mma8452_freefall_mode_enabled(data)) {
930 iio_push_event(indio_dev,
931 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
932 IIO_MOD_X_AND_Y_AND_Z,
939 if (src & data->chip_info->ev_src_xe)
940 iio_push_event(indio_dev,
941 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
946 if (src & data->chip_info->ev_src_ye)
947 iio_push_event(indio_dev,
948 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
953 if (src & data->chip_info->ev_src_ze)
954 iio_push_event(indio_dev,
955 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
961 static irqreturn_t mma8452_interrupt(int irq, void *p)
963 struct iio_dev *indio_dev = p;
964 struct mma8452_data *data = iio_priv(indio_dev);
965 const struct mma_chip_info *chip = data->chip_info;
969 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
973 if (src & MMA8452_INT_DRDY) {
974 iio_trigger_poll_chained(indio_dev->trig);
978 if ((src & MMA8452_INT_TRANS &&
979 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
980 (src & MMA8452_INT_FF_MT &&
981 chip->ev_src == MMA8452_FF_MT_SRC)) {
982 mma8452_transient_interrupt(indio_dev);
989 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
991 struct iio_poll_func *pf = p;
992 struct iio_dev *indio_dev = pf->indio_dev;
993 struct mma8452_data *data = iio_priv(indio_dev);
996 ret = mma8452_read(data, data->buffer.channels);
1000 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1001 iio_get_time_ns(indio_dev));
1004 iio_trigger_notify_done(indio_dev->trig);
1009 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1010 unsigned reg, unsigned writeval,
1014 struct mma8452_data *data = iio_priv(indio_dev);
1016 if (reg > MMA8452_MAX_REG)
1020 return mma8452_change_config(data, reg, writeval);
1022 ret = i2c_smbus_read_byte_data(data->client, reg);
1031 static const struct iio_event_spec mma8452_freefall_event[] = {
1033 .type = IIO_EV_TYPE_MAG,
1034 .dir = IIO_EV_DIR_FALLING,
1035 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1036 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1037 BIT(IIO_EV_INFO_PERIOD) |
1038 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1042 static const struct iio_event_spec mma8652_freefall_event[] = {
1044 .type = IIO_EV_TYPE_MAG,
1045 .dir = IIO_EV_DIR_FALLING,
1046 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1047 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1048 BIT(IIO_EV_INFO_PERIOD)
1052 static const struct iio_event_spec mma8452_transient_event[] = {
1054 .type = IIO_EV_TYPE_MAG,
1055 .dir = IIO_EV_DIR_RISING,
1056 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1057 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1058 BIT(IIO_EV_INFO_PERIOD) |
1059 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1063 static const struct iio_event_spec mma8452_motion_event[] = {
1065 .type = IIO_EV_TYPE_MAG,
1066 .dir = IIO_EV_DIR_RISING,
1067 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1068 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1069 BIT(IIO_EV_INFO_PERIOD)
1074 * Threshold is configured in fixed 8G/127 steps regardless of
1075 * currently selected scale for measurement.
1077 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1079 static struct attribute *mma8452_event_attributes[] = {
1080 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1084 static struct attribute_group mma8452_event_attribute_group = {
1085 .attrs = mma8452_event_attributes,
1088 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1089 .type = IIO_ACCEL, \
1091 .channel2 = modifier, \
1093 .event_spec = mma8452_freefall_event, \
1094 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1097 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1098 .type = IIO_ACCEL, \
1100 .channel2 = modifier, \
1102 .event_spec = mma8652_freefall_event, \
1103 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1106 #define MMA8452_CHANNEL(axis, idx, bits) { \
1107 .type = IIO_ACCEL, \
1109 .channel2 = IIO_MOD_##axis, \
1110 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1111 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1112 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1113 BIT(IIO_CHAN_INFO_SCALE) | \
1114 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1115 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1116 .scan_index = idx, \
1119 .realbits = (bits), \
1120 .storagebits = 16, \
1121 .shift = 16 - (bits), \
1122 .endianness = IIO_BE, \
1124 .event_spec = mma8452_transient_event, \
1125 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1128 #define MMA8652_CHANNEL(axis, idx, bits) { \
1129 .type = IIO_ACCEL, \
1131 .channel2 = IIO_MOD_##axis, \
1132 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1133 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1134 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1135 BIT(IIO_CHAN_INFO_SCALE) | \
1136 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1137 .scan_index = idx, \
1140 .realbits = (bits), \
1141 .storagebits = 16, \
1142 .shift = 16 - (bits), \
1143 .endianness = IIO_BE, \
1145 .event_spec = mma8452_motion_event, \
1146 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1149 static const struct iio_chan_spec mma8451_channels[] = {
1150 MMA8452_CHANNEL(X, idx_x, 14),
1151 MMA8452_CHANNEL(Y, idx_y, 14),
1152 MMA8452_CHANNEL(Z, idx_z, 14),
1153 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1154 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1157 static const struct iio_chan_spec mma8452_channels[] = {
1158 MMA8452_CHANNEL(X, idx_x, 12),
1159 MMA8452_CHANNEL(Y, idx_y, 12),
1160 MMA8452_CHANNEL(Z, idx_z, 12),
1161 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1162 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1165 static const struct iio_chan_spec mma8453_channels[] = {
1166 MMA8452_CHANNEL(X, idx_x, 10),
1167 MMA8452_CHANNEL(Y, idx_y, 10),
1168 MMA8452_CHANNEL(Z, idx_z, 10),
1169 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1170 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1173 static const struct iio_chan_spec mma8652_channels[] = {
1174 MMA8652_CHANNEL(X, idx_x, 12),
1175 MMA8652_CHANNEL(Y, idx_y, 12),
1176 MMA8652_CHANNEL(Z, idx_z, 12),
1177 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1178 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1181 static const struct iio_chan_spec mma8653_channels[] = {
1182 MMA8652_CHANNEL(X, idx_x, 10),
1183 MMA8652_CHANNEL(Y, idx_y, 10),
1184 MMA8652_CHANNEL(Z, idx_z, 10),
1185 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1186 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1198 static const struct mma_chip_info mma_chip_info_table[] = {
1200 .chip_id = MMA8451_DEVICE_ID,
1201 .channels = mma8451_channels,
1202 .num_channels = ARRAY_SIZE(mma8451_channels),
1204 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1205 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1207 * The userspace interface uses m/s^2 and we declare micro units
1208 * So scale factor for 12 bit here is given by:
1209 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1211 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1212 .ev_cfg = MMA8452_TRANSIENT_CFG,
1213 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1214 .ev_cfg_chan_shift = 1,
1215 .ev_src = MMA8452_TRANSIENT_SRC,
1216 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1217 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1218 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1219 .ev_ths = MMA8452_TRANSIENT_THS,
1220 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1221 .ev_count = MMA8452_TRANSIENT_COUNT,
1224 .chip_id = MMA8452_DEVICE_ID,
1225 .channels = mma8452_channels,
1226 .num_channels = ARRAY_SIZE(mma8452_channels),
1227 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1228 .ev_cfg = MMA8452_TRANSIENT_CFG,
1229 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1230 .ev_cfg_chan_shift = 1,
1231 .ev_src = MMA8452_TRANSIENT_SRC,
1232 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1233 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1234 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1235 .ev_ths = MMA8452_TRANSIENT_THS,
1236 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1237 .ev_count = MMA8452_TRANSIENT_COUNT,
1240 .chip_id = MMA8453_DEVICE_ID,
1241 .channels = mma8453_channels,
1242 .num_channels = ARRAY_SIZE(mma8453_channels),
1243 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1244 .ev_cfg = MMA8452_TRANSIENT_CFG,
1245 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1246 .ev_cfg_chan_shift = 1,
1247 .ev_src = MMA8452_TRANSIENT_SRC,
1248 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1249 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1250 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1251 .ev_ths = MMA8452_TRANSIENT_THS,
1252 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1253 .ev_count = MMA8452_TRANSIENT_COUNT,
1256 .chip_id = MMA8652_DEVICE_ID,
1257 .channels = mma8652_channels,
1258 .num_channels = ARRAY_SIZE(mma8652_channels),
1259 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1260 .ev_cfg = MMA8452_FF_MT_CFG,
1261 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1262 .ev_cfg_chan_shift = 3,
1263 .ev_src = MMA8452_FF_MT_SRC,
1264 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1265 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1266 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1267 .ev_ths = MMA8452_FF_MT_THS,
1268 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1269 .ev_count = MMA8452_FF_MT_COUNT,
1272 .chip_id = MMA8653_DEVICE_ID,
1273 .channels = mma8653_channels,
1274 .num_channels = ARRAY_SIZE(mma8653_channels),
1275 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1276 .ev_cfg = MMA8452_FF_MT_CFG,
1277 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1278 .ev_cfg_chan_shift = 3,
1279 .ev_src = MMA8452_FF_MT_SRC,
1280 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1281 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1282 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1283 .ev_ths = MMA8452_FF_MT_THS,
1284 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1285 .ev_count = MMA8452_FF_MT_COUNT,
1288 .chip_id = FXLS8471_DEVICE_ID,
1289 .channels = mma8451_channels,
1290 .num_channels = ARRAY_SIZE(mma8451_channels),
1291 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1292 .ev_cfg = MMA8452_TRANSIENT_CFG,
1293 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1294 .ev_cfg_chan_shift = 1,
1295 .ev_src = MMA8452_TRANSIENT_SRC,
1296 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1297 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1298 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1299 .ev_ths = MMA8452_TRANSIENT_THS,
1300 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1301 .ev_count = MMA8452_TRANSIENT_COUNT,
1305 static struct attribute *mma8452_attributes[] = {
1306 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1307 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1308 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1309 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1313 static const struct attribute_group mma8452_group = {
1314 .attrs = mma8452_attributes,
1317 static const struct iio_info mma8452_info = {
1318 .attrs = &mma8452_group,
1319 .read_raw = &mma8452_read_raw,
1320 .write_raw = &mma8452_write_raw,
1321 .event_attrs = &mma8452_event_attribute_group,
1322 .read_event_value = &mma8452_read_thresh,
1323 .write_event_value = &mma8452_write_thresh,
1324 .read_event_config = &mma8452_read_event_config,
1325 .write_event_config = &mma8452_write_event_config,
1326 .debugfs_reg_access = &mma8452_reg_access_dbg,
1327 .driver_module = THIS_MODULE,
1330 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1332 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1335 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1336 struct mma8452_data *data = iio_priv(indio_dev);
1339 ret = mma8452_set_runtime_pm_state(data->client, state);
1343 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1348 reg |= MMA8452_INT_DRDY;
1350 reg &= ~MMA8452_INT_DRDY;
1352 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1355 static int mma8452_validate_device(struct iio_trigger *trig,
1356 struct iio_dev *indio_dev)
1358 struct iio_dev *indio = iio_trigger_get_drvdata(trig);
1360 if (indio != indio_dev)
1366 static const struct iio_trigger_ops mma8452_trigger_ops = {
1367 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1368 .validate_device = mma8452_validate_device,
1369 .owner = THIS_MODULE,
1372 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1374 struct mma8452_data *data = iio_priv(indio_dev);
1375 struct iio_trigger *trig;
1378 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1384 trig->dev.parent = &data->client->dev;
1385 trig->ops = &mma8452_trigger_ops;
1386 iio_trigger_set_drvdata(trig, indio_dev);
1388 ret = iio_trigger_register(trig);
1392 indio_dev->trig = iio_trigger_get(trig);
1397 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1399 if (indio_dev->trig)
1400 iio_trigger_unregister(indio_dev->trig);
1403 static int mma8452_reset(struct i2c_client *client)
1409 * Find on fxls8471, after config reset bit, it reset immediately,
1410 * and will not give ACK, so here do not check the return value.
1411 * The following code will read the reset register, and check whether
1414 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1415 MMA8452_CTRL_REG2_RST);
1417 for (i = 0; i < 10; i++) {
1418 usleep_range(100, 200);
1419 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1421 continue; /* I2C comm reset */
1424 if (!(ret & MMA8452_CTRL_REG2_RST))
1431 static const struct of_device_id mma8452_dt_ids[] = {
1432 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1433 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1434 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1435 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1436 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1437 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1440 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1442 static int mma8452_probe(struct i2c_client *client,
1443 const struct i2c_device_id *id)
1445 struct mma8452_data *data;
1446 struct iio_dev *indio_dev;
1448 const struct of_device_id *match;
1450 match = of_match_device(mma8452_dt_ids, &client->dev);
1452 dev_err(&client->dev, "unknown device model\n");
1456 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1460 data = iio_priv(indio_dev);
1461 data->client = client;
1462 mutex_init(&data->lock);
1463 data->chip_info = match->data;
1465 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1470 case MMA8451_DEVICE_ID:
1471 case MMA8452_DEVICE_ID:
1472 case MMA8453_DEVICE_ID:
1473 case MMA8652_DEVICE_ID:
1474 case MMA8653_DEVICE_ID:
1475 case FXLS8471_DEVICE_ID:
1476 if (ret == data->chip_info->chip_id)
1482 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1483 match->compatible, data->chip_info->chip_id);
1485 i2c_set_clientdata(client, indio_dev);
1486 indio_dev->info = &mma8452_info;
1487 indio_dev->name = id->name;
1488 indio_dev->dev.parent = &client->dev;
1489 indio_dev->modes = INDIO_DIRECT_MODE;
1490 indio_dev->channels = data->chip_info->channels;
1491 indio_dev->num_channels = data->chip_info->num_channels;
1492 indio_dev->available_scan_masks = mma8452_scan_masks;
1494 ret = mma8452_reset(client);
1498 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1499 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1505 * By default set transient threshold to max to avoid events if
1506 * enabling without configuring threshold.
1508 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1509 MMA8452_TRANSIENT_THS_MASK);
1515 * Although we enable the interrupt sources once and for
1516 * all here the event detection itself is not enabled until
1517 * userspace asks for it by mma8452_write_event_config()
1519 int supported_interrupts = MMA8452_INT_DRDY |
1522 int enabled_interrupts = MMA8452_INT_TRANS |
1526 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1528 if (irq2 == client->irq) {
1529 dev_dbg(&client->dev, "using interrupt line INT2\n");
1531 ret = i2c_smbus_write_byte_data(client,
1533 supported_interrupts);
1537 dev_dbg(&client->dev, "using interrupt line INT1\n");
1540 ret = i2c_smbus_write_byte_data(client,
1542 enabled_interrupts);
1546 ret = mma8452_trigger_setup(indio_dev);
1551 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1552 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1553 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1556 goto trigger_cleanup;
1558 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1559 mma8452_trigger_handler, NULL);
1561 goto trigger_cleanup;
1564 ret = devm_request_threaded_irq(&client->dev,
1566 NULL, mma8452_interrupt,
1567 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1568 client->name, indio_dev);
1570 goto buffer_cleanup;
1573 ret = pm_runtime_set_active(&client->dev);
1575 goto buffer_cleanup;
1577 pm_runtime_enable(&client->dev);
1578 pm_runtime_set_autosuspend_delay(&client->dev,
1579 MMA8452_AUTO_SUSPEND_DELAY_MS);
1580 pm_runtime_use_autosuspend(&client->dev);
1582 ret = iio_device_register(indio_dev);
1584 goto buffer_cleanup;
1586 ret = mma8452_set_freefall_mode(data, false);
1588 goto unregister_device;
1593 iio_device_unregister(indio_dev);
1596 iio_triggered_buffer_cleanup(indio_dev);
1599 mma8452_trigger_cleanup(indio_dev);
1604 static int mma8452_remove(struct i2c_client *client)
1606 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1608 iio_device_unregister(indio_dev);
1610 pm_runtime_disable(&client->dev);
1611 pm_runtime_set_suspended(&client->dev);
1612 pm_runtime_put_noidle(&client->dev);
1614 iio_triggered_buffer_cleanup(indio_dev);
1615 mma8452_trigger_cleanup(indio_dev);
1616 mma8452_standby(iio_priv(indio_dev));
1622 static int mma8452_runtime_suspend(struct device *dev)
1624 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1625 struct mma8452_data *data = iio_priv(indio_dev);
1628 mutex_lock(&data->lock);
1629 ret = mma8452_standby(data);
1630 mutex_unlock(&data->lock);
1632 dev_err(&data->client->dev, "powering off device failed\n");
1639 static int mma8452_runtime_resume(struct device *dev)
1641 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1642 struct mma8452_data *data = iio_priv(indio_dev);
1645 ret = mma8452_active(data);
1649 ret = mma8452_get_odr_index(data);
1650 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1652 usleep_range(sleep_val * 1000, 20000);
1654 msleep_interruptible(sleep_val);
1660 #ifdef CONFIG_PM_SLEEP
1661 static int mma8452_suspend(struct device *dev)
1663 return mma8452_standby(iio_priv(i2c_get_clientdata(
1664 to_i2c_client(dev))));
1667 static int mma8452_resume(struct device *dev)
1669 return mma8452_active(iio_priv(i2c_get_clientdata(
1670 to_i2c_client(dev))));
1674 static const struct dev_pm_ops mma8452_pm_ops = {
1675 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume)
1676 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1677 mma8452_runtime_resume, NULL)
1680 static const struct i2c_device_id mma8452_id[] = {
1681 { "mma8451", mma8451 },
1682 { "mma8452", mma8452 },
1683 { "mma8453", mma8453 },
1684 { "mma8652", mma8652 },
1685 { "mma8653", mma8653 },
1686 { "fxls8471", fxls8471 },
1689 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1691 static struct i2c_driver mma8452_driver = {
1694 .of_match_table = of_match_ptr(mma8452_dt_ids),
1695 .pm = &mma8452_pm_ops,
1697 .probe = mma8452_probe,
1698 .remove = mma8452_remove,
1699 .id_table = mma8452_id,
1701 module_i2c_driver(mma8452_driver);
1703 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1704 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1705 MODULE_LICENSE("GPL");