1 // SPDX-License-Identifier: GPL-2.0
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
14 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
18 * TODO: orientation events
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
36 #define MMA8452_STATUS 0x00
37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38 #define MMA8452_OUT_X 0x01 /* MSB first */
39 #define MMA8452_OUT_Y 0x03
40 #define MMA8452_OUT_Z 0x05
41 #define MMA8452_INT_SRC 0x0c
42 #define MMA8452_WHO_AM_I 0x0d
43 #define MMA8452_DATA_CFG 0x0e
44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45 #define MMA8452_DATA_CFG_FS_2G 0
46 #define MMA8452_DATA_CFG_FS_4G 1
47 #define MMA8452_DATA_CFG_FS_8G 2
48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49 #define MMA8452_HP_FILTER_CUTOFF 0x0f
50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51 #define MMA8452_FF_MT_CFG 0x15
52 #define MMA8452_FF_MT_CFG_OAE BIT(6)
53 #define MMA8452_FF_MT_CFG_ELE BIT(7)
54 #define MMA8452_FF_MT_SRC 0x16
55 #define MMA8452_FF_MT_SRC_XHE BIT(1)
56 #define MMA8452_FF_MT_SRC_YHE BIT(3)
57 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
58 #define MMA8452_FF_MT_THS 0x17
59 #define MMA8452_FF_MT_THS_MASK 0x7f
60 #define MMA8452_FF_MT_COUNT 0x18
61 #define MMA8452_FF_MT_CHAN_SHIFT 3
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
66 #define MMA8452_TRANSIENT_SRC 0x1e
67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
70 #define MMA8452_TRANSIENT_THS 0x1f
71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
72 #define MMA8452_TRANSIENT_COUNT 0x20
73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
74 #define MMA8452_CTRL_REG1 0x2a
75 #define MMA8452_CTRL_ACTIVE BIT(0)
76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
77 #define MMA8452_CTRL_DR_SHIFT 3
78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
79 #define MMA8452_CTRL_REG2 0x2b
80 #define MMA8452_CTRL_REG2_RST BIT(6)
81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
83 #define MMA8452_CTRL_REG4 0x2d
84 #define MMA8452_CTRL_REG5 0x2e
85 #define MMA8452_OFF_X 0x2f
86 #define MMA8452_OFF_Y 0x30
87 #define MMA8452_OFF_Z 0x31
89 #define MMA8452_MAX_REG 0x31
91 #define MMA8452_INT_DRDY BIT(0)
92 #define MMA8452_INT_FF_MT BIT(2)
93 #define MMA8452_INT_TRANS BIT(5)
95 #define MMA8451_DEVICE_ID 0x1a
96 #define MMA8452_DEVICE_ID 0x2a
97 #define MMA8453_DEVICE_ID 0x3a
98 #define MMA8652_DEVICE_ID 0x4a
99 #define MMA8653_DEVICE_ID 0x5a
100 #define FXLS8471_DEVICE_ID 0x6a
102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
104 struct mma8452_data {
105 struct i2c_client *client;
109 const struct mma_chip_info *chip_info;
111 struct regulator *vdd_reg;
112 struct regulator *vddio_reg;
114 /* Ensure correct alignment of time stamp when present */
122 * struct mma8452_event_regs - chip specific data related to events
123 * @ev_cfg: event config register address
124 * @ev_cfg_ele: latch bit in event config register
125 * @ev_cfg_chan_shift: number of the bit to enable events in X
126 * direction; in event config register
127 * @ev_src: event source register address
128 * @ev_ths: event threshold register address
129 * @ev_ths_mask: mask for the threshold value
130 * @ev_count: event count (period) register address
132 * Since not all chips supported by the driver support comparing high pass
133 * filtered data for events (interrupts), different interrupt sources are
134 * used for different chips and the relevant registers are included here.
136 struct mma8452_event_regs {
139 u8 ev_cfg_chan_shift;
146 static const struct mma8452_event_regs ff_mt_ev_regs = {
147 .ev_cfg = MMA8452_FF_MT_CFG,
148 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
149 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
150 .ev_src = MMA8452_FF_MT_SRC,
151 .ev_ths = MMA8452_FF_MT_THS,
152 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
153 .ev_count = MMA8452_FF_MT_COUNT
156 static const struct mma8452_event_regs trans_ev_regs = {
157 .ev_cfg = MMA8452_TRANSIENT_CFG,
158 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
159 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
160 .ev_src = MMA8452_TRANSIENT_SRC,
161 .ev_ths = MMA8452_TRANSIENT_THS,
162 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
163 .ev_count = MMA8452_TRANSIENT_COUNT,
167 * struct mma_chip_info - chip specific data
168 * @chip_id: WHO_AM_I register's value
169 * @channels: struct iio_chan_spec matching the device's
171 * @num_channels: number of channels
172 * @mma_scales: scale factors for converting register values
173 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
174 * per mode: m/s^2 and micro m/s^2
175 * @all_events: all events supported by this chip
176 * @enabled_events: event flags enabled and handled by this driver
178 struct mma_chip_info {
181 const struct iio_chan_spec *channels;
183 const int mma_scales[3][2];
195 static int mma8452_drdy(struct mma8452_data *data)
199 while (tries-- > 0) {
200 int ret = i2c_smbus_read_byte_data(data->client,
204 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
207 if (data->sleep_val <= 20)
208 usleep_range(data->sleep_val * 250,
209 data->sleep_val * 500);
214 dev_err(&data->client->dev, "data not ready\n");
219 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
225 ret = pm_runtime_get_sync(&client->dev);
227 pm_runtime_mark_last_busy(&client->dev);
228 ret = pm_runtime_put_autosuspend(&client->dev);
232 dev_err(&client->dev,
233 "failed to change power state to %d\n", on);
235 pm_runtime_put_noidle(&client->dev);
244 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
246 int ret = mma8452_drdy(data);
251 ret = mma8452_set_runtime_pm_state(data->client, true);
255 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
256 3 * sizeof(__be16), (u8 *)buf);
258 ret = mma8452_set_runtime_pm_state(data->client, false);
263 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
269 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
270 vals[n][0], vals[n][1]);
272 /* replace trailing space by newline */
278 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
282 if (val == vals[n][0] && val2 == vals[n][1])
288 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
290 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
291 MMA8452_CTRL_DR_SHIFT;
294 static const int mma8452_samp_freq[8][2] = {
295 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
296 {6, 250000}, {1, 560000}
299 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
300 static const unsigned int mma8452_time_step_us[4][8] = {
301 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
302 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
303 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
304 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
307 /* Datasheet table "High-Pass Filter Cutoff Options" */
308 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
310 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
311 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
312 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
313 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
316 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
317 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
319 { /* low noise low power */
320 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
321 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
322 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
323 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
324 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
325 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
326 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
327 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
329 { /* high resolution */
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
336 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
337 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
340 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
341 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
342 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
343 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
344 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
345 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
346 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
347 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
351 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
352 static const u16 mma8452_os_ratio[4][8] = {
353 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
354 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
355 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
356 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
357 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
360 static int mma8452_get_power_mode(struct mma8452_data *data)
364 reg = i2c_smbus_read_byte_data(data->client,
369 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
370 MMA8452_CTRL_REG2_MODS_SHIFT);
373 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
374 struct device_attribute *attr,
377 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
378 ARRAY_SIZE(mma8452_samp_freq));
381 static ssize_t mma8452_show_scale_avail(struct device *dev,
382 struct device_attribute *attr,
385 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
386 to_i2c_client(dev)));
388 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
389 ARRAY_SIZE(data->chip_info->mma_scales));
392 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
393 struct device_attribute *attr,
396 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
397 struct mma8452_data *data = iio_priv(indio_dev);
400 i = mma8452_get_odr_index(data);
401 j = mma8452_get_power_mode(data);
405 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
406 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
409 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
410 struct device_attribute *attr,
413 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
414 struct mma8452_data *data = iio_priv(indio_dev);
415 int i = mma8452_get_odr_index(data);
420 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
421 if (val == mma8452_os_ratio[j][i])
424 val = mma8452_os_ratio[j][i];
426 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
433 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
434 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
435 mma8452_show_scale_avail, NULL, 0);
436 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
437 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
438 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
439 mma8452_show_os_ratio_avail, NULL, 0);
441 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
444 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
445 ARRAY_SIZE(mma8452_samp_freq),
449 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
451 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
452 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
455 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
460 i = mma8452_get_odr_index(data);
461 j = mma8452_get_power_mode(data);
465 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
466 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
469 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
473 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
477 i = mma8452_get_odr_index(data);
478 j = mma8452_get_power_mode(data);
482 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
483 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
484 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
489 static int mma8452_read_raw(struct iio_dev *indio_dev,
490 struct iio_chan_spec const *chan,
491 int *val, int *val2, long mask)
493 struct mma8452_data *data = iio_priv(indio_dev);
498 case IIO_CHAN_INFO_RAW:
499 ret = iio_device_claim_direct_mode(indio_dev);
503 mutex_lock(&data->lock);
504 ret = mma8452_read(data, buffer);
505 mutex_unlock(&data->lock);
506 iio_device_release_direct_mode(indio_dev);
510 *val = sign_extend32(be16_to_cpu(
511 buffer[chan->scan_index]) >> chan->scan_type.shift,
512 chan->scan_type.realbits - 1);
515 case IIO_CHAN_INFO_SCALE:
516 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
517 *val = data->chip_info->mma_scales[i][0];
518 *val2 = data->chip_info->mma_scales[i][1];
520 return IIO_VAL_INT_PLUS_MICRO;
521 case IIO_CHAN_INFO_SAMP_FREQ:
522 i = mma8452_get_odr_index(data);
523 *val = mma8452_samp_freq[i][0];
524 *val2 = mma8452_samp_freq[i][1];
526 return IIO_VAL_INT_PLUS_MICRO;
527 case IIO_CHAN_INFO_CALIBBIAS:
528 ret = i2c_smbus_read_byte_data(data->client,
534 *val = sign_extend32(ret, 7);
537 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
538 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
539 ret = mma8452_read_hp_filter(data, val, val2);
547 return IIO_VAL_INT_PLUS_MICRO;
548 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
549 ret = mma8452_get_power_mode(data);
553 i = mma8452_get_odr_index(data);
555 *val = mma8452_os_ratio[ret][i];
562 static int mma8452_calculate_sleep(struct mma8452_data *data)
564 int ret, i = mma8452_get_odr_index(data);
566 if (mma8452_samp_freq[i][0] > 0)
567 ret = 1000 / mma8452_samp_freq[i][0];
571 return ret == 0 ? 1 : ret;
574 static int mma8452_standby(struct mma8452_data *data)
576 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
577 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
580 static int mma8452_active(struct mma8452_data *data)
582 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
586 /* returns >0 if active, 0 if in standby and <0 on error */
587 static int mma8452_is_active(struct mma8452_data *data)
591 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
595 return reg & MMA8452_CTRL_ACTIVE;
598 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
603 mutex_lock(&data->lock);
605 is_active = mma8452_is_active(data);
611 /* config can only be changed when in standby */
613 ret = mma8452_standby(data);
618 ret = i2c_smbus_write_byte_data(data->client, reg, val);
623 ret = mma8452_active(data);
630 mutex_unlock(&data->lock);
635 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
639 reg = i2c_smbus_read_byte_data(data->client,
644 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
645 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
647 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
650 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
651 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
655 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
659 return !(val & MMA8452_FF_MT_CFG_OAE);
662 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
666 if ((state && mma8452_freefall_mode_enabled(data)) ||
667 (!state && !(mma8452_freefall_mode_enabled(data))))
670 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
675 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
676 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
677 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
678 val &= ~MMA8452_FF_MT_CFG_OAE;
680 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
681 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
682 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
683 val |= MMA8452_FF_MT_CFG_OAE;
686 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
689 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
694 i = mma8452_get_hp_filter_index(data, val, val2);
698 reg = i2c_smbus_read_byte_data(data->client,
699 MMA8452_HP_FILTER_CUTOFF);
703 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
706 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
709 static int mma8452_write_raw(struct iio_dev *indio_dev,
710 struct iio_chan_spec const *chan,
711 int val, int val2, long mask)
713 struct mma8452_data *data = iio_priv(indio_dev);
716 ret = iio_device_claim_direct_mode(indio_dev);
721 case IIO_CHAN_INFO_SAMP_FREQ:
722 i = mma8452_get_samp_freq_index(data, val, val2);
727 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
728 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
730 data->sleep_val = mma8452_calculate_sleep(data);
732 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
735 case IIO_CHAN_INFO_SCALE:
736 i = mma8452_get_scale_index(data, val, val2);
742 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
745 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
748 case IIO_CHAN_INFO_CALIBBIAS:
749 if (val < -128 || val > 127) {
754 ret = mma8452_change_config(data,
755 MMA8452_OFF_X + chan->scan_index,
759 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
760 if (val == 0 && val2 == 0) {
761 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
763 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
764 ret = mma8452_set_hp_filter_frequency(data, val, val2);
769 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
773 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
774 ret = mma8452_get_odr_index(data);
776 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
777 if (mma8452_os_ratio[i][ret] == val) {
778 ret = mma8452_set_power_mode(data, i);
788 iio_device_release_direct_mode(indio_dev);
792 static int mma8452_get_event_regs(struct mma8452_data *data,
793 const struct iio_chan_spec *chan, enum iio_event_direction dir,
794 const struct mma8452_event_regs **ev_reg)
799 switch (chan->type) {
802 case IIO_EV_DIR_RISING:
803 if ((data->chip_info->all_events
804 & MMA8452_INT_TRANS) &&
805 (data->chip_info->enabled_events
806 & MMA8452_INT_TRANS))
807 *ev_reg = &trans_ev_regs;
809 *ev_reg = &ff_mt_ev_regs;
811 case IIO_EV_DIR_FALLING:
812 *ev_reg = &ff_mt_ev_regs;
822 static int mma8452_read_event_value(struct iio_dev *indio_dev,
823 const struct iio_chan_spec *chan,
824 enum iio_event_type type,
825 enum iio_event_direction dir,
826 enum iio_event_info info,
829 struct mma8452_data *data = iio_priv(indio_dev);
830 int ret, us, power_mode;
831 const struct mma8452_event_regs *ev_regs;
833 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
838 case IIO_EV_INFO_VALUE:
839 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
843 *val = ret & ev_regs->ev_ths_mask;
847 case IIO_EV_INFO_PERIOD:
848 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
852 power_mode = mma8452_get_power_mode(data);
856 us = ret * mma8452_time_step_us[power_mode][
857 mma8452_get_odr_index(data)];
858 *val = us / USEC_PER_SEC;
859 *val2 = us % USEC_PER_SEC;
861 return IIO_VAL_INT_PLUS_MICRO;
863 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
864 ret = i2c_smbus_read_byte_data(data->client,
865 MMA8452_TRANSIENT_CFG);
869 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
873 ret = mma8452_read_hp_filter(data, val, val2);
878 return IIO_VAL_INT_PLUS_MICRO;
885 static int mma8452_write_event_value(struct iio_dev *indio_dev,
886 const struct iio_chan_spec *chan,
887 enum iio_event_type type,
888 enum iio_event_direction dir,
889 enum iio_event_info info,
892 struct mma8452_data *data = iio_priv(indio_dev);
894 const struct mma8452_event_regs *ev_regs;
896 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
901 case IIO_EV_INFO_VALUE:
902 if (val < 0 || val > ev_regs->ev_ths_mask)
905 return mma8452_change_config(data, ev_regs->ev_ths, val);
907 case IIO_EV_INFO_PERIOD:
908 ret = mma8452_get_power_mode(data);
912 steps = (val * USEC_PER_SEC + val2) /
913 mma8452_time_step_us[ret][
914 mma8452_get_odr_index(data)];
916 if (steps < 0 || steps > 0xff)
919 return mma8452_change_config(data, ev_regs->ev_count, steps);
921 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
922 reg = i2c_smbus_read_byte_data(data->client,
923 MMA8452_TRANSIENT_CFG);
927 if (val == 0 && val2 == 0) {
928 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
930 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
931 ret = mma8452_set_hp_filter_frequency(data, val, val2);
936 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
943 static int mma8452_read_event_config(struct iio_dev *indio_dev,
944 const struct iio_chan_spec *chan,
945 enum iio_event_type type,
946 enum iio_event_direction dir)
948 struct mma8452_data *data = iio_priv(indio_dev);
950 const struct mma8452_event_regs *ev_regs;
952 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
957 case IIO_EV_DIR_FALLING:
958 return mma8452_freefall_mode_enabled(data);
959 case IIO_EV_DIR_RISING:
960 ret = i2c_smbus_read_byte_data(data->client,
965 return !!(ret & BIT(chan->scan_index +
966 ev_regs->ev_cfg_chan_shift));
972 static int mma8452_write_event_config(struct iio_dev *indio_dev,
973 const struct iio_chan_spec *chan,
974 enum iio_event_type type,
975 enum iio_event_direction dir,
978 struct mma8452_data *data = iio_priv(indio_dev);
980 const struct mma8452_event_regs *ev_regs;
982 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
986 ret = mma8452_set_runtime_pm_state(data->client, state);
991 case IIO_EV_DIR_FALLING:
992 return mma8452_set_freefall_mode(data, state);
993 case IIO_EV_DIR_RISING:
994 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
999 if (mma8452_freefall_mode_enabled(data)) {
1000 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
1001 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
1002 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1003 val |= MMA8452_FF_MT_CFG_OAE;
1005 val |= BIT(chan->scan_index +
1006 ev_regs->ev_cfg_chan_shift);
1008 if (mma8452_freefall_mode_enabled(data))
1011 val &= ~BIT(chan->scan_index +
1012 ev_regs->ev_cfg_chan_shift);
1015 val |= ev_regs->ev_cfg_ele;
1017 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1023 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1025 struct mma8452_data *data = iio_priv(indio_dev);
1026 s64 ts = iio_get_time_ns(indio_dev);
1029 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1033 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1034 iio_push_event(indio_dev,
1035 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1040 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1041 iio_push_event(indio_dev,
1042 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1047 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1048 iio_push_event(indio_dev,
1049 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1055 static irqreturn_t mma8452_interrupt(int irq, void *p)
1057 struct iio_dev *indio_dev = p;
1058 struct mma8452_data *data = iio_priv(indio_dev);
1062 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1066 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1069 if (src & MMA8452_INT_DRDY) {
1070 iio_trigger_poll_chained(indio_dev->trig);
1074 if (src & MMA8452_INT_FF_MT) {
1075 if (mma8452_freefall_mode_enabled(data)) {
1076 s64 ts = iio_get_time_ns(indio_dev);
1078 iio_push_event(indio_dev,
1079 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1080 IIO_MOD_X_AND_Y_AND_Z,
1082 IIO_EV_DIR_FALLING),
1088 if (src & MMA8452_INT_TRANS) {
1089 mma8452_transient_interrupt(indio_dev);
1096 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1098 struct iio_poll_func *pf = p;
1099 struct iio_dev *indio_dev = pf->indio_dev;
1100 struct mma8452_data *data = iio_priv(indio_dev);
1103 ret = mma8452_read(data, data->buffer.channels);
1107 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1108 iio_get_time_ns(indio_dev));
1111 iio_trigger_notify_done(indio_dev->trig);
1116 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1117 unsigned int reg, unsigned int writeval,
1118 unsigned int *readval)
1121 struct mma8452_data *data = iio_priv(indio_dev);
1123 if (reg > MMA8452_MAX_REG)
1127 return mma8452_change_config(data, reg, writeval);
1129 ret = i2c_smbus_read_byte_data(data->client, reg);
1138 static const struct iio_event_spec mma8452_freefall_event[] = {
1140 .type = IIO_EV_TYPE_MAG,
1141 .dir = IIO_EV_DIR_FALLING,
1142 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1143 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1144 BIT(IIO_EV_INFO_PERIOD) |
1145 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1149 static const struct iio_event_spec mma8652_freefall_event[] = {
1151 .type = IIO_EV_TYPE_MAG,
1152 .dir = IIO_EV_DIR_FALLING,
1153 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1154 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1155 BIT(IIO_EV_INFO_PERIOD)
1159 static const struct iio_event_spec mma8452_transient_event[] = {
1161 .type = IIO_EV_TYPE_MAG,
1162 .dir = IIO_EV_DIR_RISING,
1163 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1164 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1165 BIT(IIO_EV_INFO_PERIOD) |
1166 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1170 static const struct iio_event_spec mma8452_motion_event[] = {
1172 .type = IIO_EV_TYPE_MAG,
1173 .dir = IIO_EV_DIR_RISING,
1174 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1175 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1176 BIT(IIO_EV_INFO_PERIOD)
1181 * Threshold is configured in fixed 8G/127 steps regardless of
1182 * currently selected scale for measurement.
1184 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1186 static struct attribute *mma8452_event_attributes[] = {
1187 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1191 static struct attribute_group mma8452_event_attribute_group = {
1192 .attrs = mma8452_event_attributes,
1195 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1196 .type = IIO_ACCEL, \
1198 .channel2 = modifier, \
1200 .event_spec = mma8452_freefall_event, \
1201 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1204 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1205 .type = IIO_ACCEL, \
1207 .channel2 = modifier, \
1209 .event_spec = mma8652_freefall_event, \
1210 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1213 #define MMA8452_CHANNEL(axis, idx, bits) { \
1214 .type = IIO_ACCEL, \
1216 .channel2 = IIO_MOD_##axis, \
1217 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1218 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1219 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1220 BIT(IIO_CHAN_INFO_SCALE) | \
1221 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1222 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1223 .scan_index = idx, \
1226 .realbits = (bits), \
1227 .storagebits = 16, \
1228 .shift = 16 - (bits), \
1229 .endianness = IIO_BE, \
1231 .event_spec = mma8452_transient_event, \
1232 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1235 #define MMA8652_CHANNEL(axis, idx, bits) { \
1236 .type = IIO_ACCEL, \
1238 .channel2 = IIO_MOD_##axis, \
1239 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1240 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1241 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1242 BIT(IIO_CHAN_INFO_SCALE) | \
1243 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1244 .scan_index = idx, \
1247 .realbits = (bits), \
1248 .storagebits = 16, \
1249 .shift = 16 - (bits), \
1250 .endianness = IIO_BE, \
1252 .event_spec = mma8452_motion_event, \
1253 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1256 static const struct iio_chan_spec mma8451_channels[] = {
1257 MMA8452_CHANNEL(X, idx_x, 14),
1258 MMA8452_CHANNEL(Y, idx_y, 14),
1259 MMA8452_CHANNEL(Z, idx_z, 14),
1260 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1261 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1264 static const struct iio_chan_spec mma8452_channels[] = {
1265 MMA8452_CHANNEL(X, idx_x, 12),
1266 MMA8452_CHANNEL(Y, idx_y, 12),
1267 MMA8452_CHANNEL(Z, idx_z, 12),
1268 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1269 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1272 static const struct iio_chan_spec mma8453_channels[] = {
1273 MMA8452_CHANNEL(X, idx_x, 10),
1274 MMA8452_CHANNEL(Y, idx_y, 10),
1275 MMA8452_CHANNEL(Z, idx_z, 10),
1276 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1277 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1280 static const struct iio_chan_spec mma8652_channels[] = {
1281 MMA8652_CHANNEL(X, idx_x, 12),
1282 MMA8652_CHANNEL(Y, idx_y, 12),
1283 MMA8652_CHANNEL(Z, idx_z, 12),
1284 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1285 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1288 static const struct iio_chan_spec mma8653_channels[] = {
1289 MMA8652_CHANNEL(X, idx_x, 10),
1290 MMA8652_CHANNEL(Y, idx_y, 10),
1291 MMA8652_CHANNEL(Z, idx_z, 10),
1292 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1293 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1305 static const struct mma_chip_info mma_chip_info_table[] = {
1308 .chip_id = MMA8451_DEVICE_ID,
1309 .channels = mma8451_channels,
1310 .num_channels = ARRAY_SIZE(mma8451_channels),
1312 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1313 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1315 * The userspace interface uses m/s^2 and we declare micro units
1316 * So scale factor for 12 bit here is given by:
1317 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1319 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1321 * Although we enable the interrupt sources once and for
1322 * all here the event detection itself is not enabled until
1323 * userspace asks for it by mma8452_write_event_config()
1325 .all_events = MMA8452_INT_DRDY |
1328 .enabled_events = MMA8452_INT_TRANS |
1333 .chip_id = MMA8452_DEVICE_ID,
1334 .channels = mma8452_channels,
1335 .num_channels = ARRAY_SIZE(mma8452_channels),
1336 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1338 * Although we enable the interrupt sources once and for
1339 * all here the event detection itself is not enabled until
1340 * userspace asks for it by mma8452_write_event_config()
1342 .all_events = MMA8452_INT_DRDY |
1345 .enabled_events = MMA8452_INT_TRANS |
1350 .chip_id = MMA8453_DEVICE_ID,
1351 .channels = mma8453_channels,
1352 .num_channels = ARRAY_SIZE(mma8453_channels),
1353 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1355 * Although we enable the interrupt sources once and for
1356 * all here the event detection itself is not enabled until
1357 * userspace asks for it by mma8452_write_event_config()
1359 .all_events = MMA8452_INT_DRDY |
1362 .enabled_events = MMA8452_INT_TRANS |
1367 .chip_id = MMA8652_DEVICE_ID,
1368 .channels = mma8652_channels,
1369 .num_channels = ARRAY_SIZE(mma8652_channels),
1370 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1371 .all_events = MMA8452_INT_DRDY |
1373 .enabled_events = MMA8452_INT_FF_MT,
1377 .chip_id = MMA8653_DEVICE_ID,
1378 .channels = mma8653_channels,
1379 .num_channels = ARRAY_SIZE(mma8653_channels),
1380 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1382 * Although we enable the interrupt sources once and for
1383 * all here the event detection itself is not enabled until
1384 * userspace asks for it by mma8452_write_event_config()
1386 .all_events = MMA8452_INT_DRDY |
1388 .enabled_events = MMA8452_INT_FF_MT,
1392 .chip_id = FXLS8471_DEVICE_ID,
1393 .channels = mma8451_channels,
1394 .num_channels = ARRAY_SIZE(mma8451_channels),
1395 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1397 * Although we enable the interrupt sources once and for
1398 * all here the event detection itself is not enabled until
1399 * userspace asks for it by mma8452_write_event_config()
1401 .all_events = MMA8452_INT_DRDY |
1404 .enabled_events = MMA8452_INT_TRANS |
1409 static struct attribute *mma8452_attributes[] = {
1410 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1411 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1412 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1413 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1417 static const struct attribute_group mma8452_group = {
1418 .attrs = mma8452_attributes,
1421 static const struct iio_info mma8452_info = {
1422 .attrs = &mma8452_group,
1423 .read_raw = &mma8452_read_raw,
1424 .write_raw = &mma8452_write_raw,
1425 .event_attrs = &mma8452_event_attribute_group,
1426 .read_event_value = &mma8452_read_event_value,
1427 .write_event_value = &mma8452_write_event_value,
1428 .read_event_config = &mma8452_read_event_config,
1429 .write_event_config = &mma8452_write_event_config,
1430 .debugfs_reg_access = &mma8452_reg_access_dbg,
1433 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1435 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1438 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1439 struct mma8452_data *data = iio_priv(indio_dev);
1442 ret = mma8452_set_runtime_pm_state(data->client, state);
1446 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1451 reg |= MMA8452_INT_DRDY;
1453 reg &= ~MMA8452_INT_DRDY;
1455 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1458 static const struct iio_trigger_ops mma8452_trigger_ops = {
1459 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1460 .validate_device = iio_trigger_validate_own_device,
1463 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1465 struct mma8452_data *data = iio_priv(indio_dev);
1466 struct iio_trigger *trig;
1469 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1475 trig->dev.parent = &data->client->dev;
1476 trig->ops = &mma8452_trigger_ops;
1477 iio_trigger_set_drvdata(trig, indio_dev);
1479 ret = iio_trigger_register(trig);
1483 indio_dev->trig = iio_trigger_get(trig);
1488 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1490 if (indio_dev->trig)
1491 iio_trigger_unregister(indio_dev->trig);
1494 static int mma8452_reset(struct i2c_client *client)
1500 * Find on fxls8471, after config reset bit, it reset immediately,
1501 * and will not give ACK, so here do not check the return value.
1502 * The following code will read the reset register, and check whether
1505 i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1506 MMA8452_CTRL_REG2_RST);
1508 for (i = 0; i < 10; i++) {
1509 usleep_range(100, 200);
1510 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1512 continue; /* I2C comm reset */
1515 if (!(ret & MMA8452_CTRL_REG2_RST))
1522 static const struct of_device_id mma8452_dt_ids[] = {
1523 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1524 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1525 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1526 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1527 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1528 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1531 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1533 static int mma8452_probe(struct i2c_client *client,
1534 const struct i2c_device_id *id)
1536 struct mma8452_data *data;
1537 struct iio_dev *indio_dev;
1540 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1544 data = iio_priv(indio_dev);
1545 data->client = client;
1546 mutex_init(&data->lock);
1548 data->chip_info = device_get_match_data(&client->dev);
1549 if (!data->chip_info) {
1551 data->chip_info = &mma_chip_info_table[id->driver_data];
1553 dev_err(&client->dev, "unknown device model\n");
1558 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1559 if (IS_ERR(data->vdd_reg))
1560 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1561 "failed to get VDD regulator!\n");
1563 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1564 if (IS_ERR(data->vddio_reg))
1565 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1566 "failed to get VDDIO regulator!\n");
1568 ret = regulator_enable(data->vdd_reg);
1570 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1574 ret = regulator_enable(data->vddio_reg);
1576 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1577 goto disable_regulator_vdd;
1580 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1582 goto disable_regulators;
1585 case MMA8451_DEVICE_ID:
1586 case MMA8452_DEVICE_ID:
1587 case MMA8453_DEVICE_ID:
1588 case MMA8652_DEVICE_ID:
1589 case MMA8653_DEVICE_ID:
1590 case FXLS8471_DEVICE_ID:
1591 if (ret == data->chip_info->chip_id)
1596 goto disable_regulators;
1599 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1600 data->chip_info->name, data->chip_info->chip_id);
1602 i2c_set_clientdata(client, indio_dev);
1603 indio_dev->info = &mma8452_info;
1604 indio_dev->name = data->chip_info->name;
1605 indio_dev->modes = INDIO_DIRECT_MODE;
1606 indio_dev->channels = data->chip_info->channels;
1607 indio_dev->num_channels = data->chip_info->num_channels;
1608 indio_dev->available_scan_masks = mma8452_scan_masks;
1610 ret = mma8452_reset(client);
1612 goto disable_regulators;
1614 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1615 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1618 goto disable_regulators;
1621 * By default set transient threshold to max to avoid events if
1622 * enabling without configuring threshold.
1624 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1625 MMA8452_TRANSIENT_THS_MASK);
1627 goto disable_regulators;
1632 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1634 if (irq2 == client->irq) {
1635 dev_dbg(&client->dev, "using interrupt line INT2\n");
1637 ret = i2c_smbus_write_byte_data(client,
1639 data->chip_info->all_events);
1641 goto disable_regulators;
1643 dev_dbg(&client->dev, "using interrupt line INT1\n");
1646 ret = i2c_smbus_write_byte_data(client,
1648 data->chip_info->enabled_events);
1650 goto disable_regulators;
1652 ret = mma8452_trigger_setup(indio_dev);
1654 goto disable_regulators;
1657 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1658 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1660 data->sleep_val = mma8452_calculate_sleep(data);
1662 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1665 goto trigger_cleanup;
1667 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1668 mma8452_trigger_handler, NULL);
1670 goto trigger_cleanup;
1673 ret = devm_request_threaded_irq(&client->dev,
1675 NULL, mma8452_interrupt,
1676 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1677 client->name, indio_dev);
1679 goto buffer_cleanup;
1682 ret = pm_runtime_set_active(&client->dev);
1684 goto buffer_cleanup;
1686 pm_runtime_enable(&client->dev);
1687 pm_runtime_set_autosuspend_delay(&client->dev,
1688 MMA8452_AUTO_SUSPEND_DELAY_MS);
1689 pm_runtime_use_autosuspend(&client->dev);
1691 ret = iio_device_register(indio_dev);
1693 goto buffer_cleanup;
1695 ret = mma8452_set_freefall_mode(data, false);
1697 goto unregister_device;
1702 iio_device_unregister(indio_dev);
1705 iio_triggered_buffer_cleanup(indio_dev);
1708 mma8452_trigger_cleanup(indio_dev);
1711 regulator_disable(data->vddio_reg);
1713 disable_regulator_vdd:
1714 regulator_disable(data->vdd_reg);
1719 static int mma8452_remove(struct i2c_client *client)
1721 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1722 struct mma8452_data *data = iio_priv(indio_dev);
1724 iio_device_unregister(indio_dev);
1726 pm_runtime_disable(&client->dev);
1727 pm_runtime_set_suspended(&client->dev);
1728 pm_runtime_put_noidle(&client->dev);
1730 iio_triggered_buffer_cleanup(indio_dev);
1731 mma8452_trigger_cleanup(indio_dev);
1732 mma8452_standby(iio_priv(indio_dev));
1734 regulator_disable(data->vddio_reg);
1735 regulator_disable(data->vdd_reg);
1741 static int mma8452_runtime_suspend(struct device *dev)
1743 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1744 struct mma8452_data *data = iio_priv(indio_dev);
1747 mutex_lock(&data->lock);
1748 ret = mma8452_standby(data);
1749 mutex_unlock(&data->lock);
1751 dev_err(&data->client->dev, "powering off device failed\n");
1755 ret = regulator_disable(data->vddio_reg);
1757 dev_err(dev, "failed to disable VDDIO regulator\n");
1761 ret = regulator_disable(data->vdd_reg);
1763 dev_err(dev, "failed to disable VDD regulator\n");
1770 static int mma8452_runtime_resume(struct device *dev)
1772 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1773 struct mma8452_data *data = iio_priv(indio_dev);
1776 ret = regulator_enable(data->vdd_reg);
1778 dev_err(dev, "failed to enable VDD regulator\n");
1782 ret = regulator_enable(data->vddio_reg);
1784 dev_err(dev, "failed to enable VDDIO regulator\n");
1785 regulator_disable(data->vdd_reg);
1789 ret = mma8452_active(data);
1791 goto runtime_resume_failed;
1793 ret = mma8452_get_odr_index(data);
1794 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1796 usleep_range(sleep_val * 1000, 20000);
1798 msleep_interruptible(sleep_val);
1802 runtime_resume_failed:
1803 regulator_disable(data->vddio_reg);
1804 regulator_disable(data->vdd_reg);
1810 static const struct dev_pm_ops mma8452_pm_ops = {
1811 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1812 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1813 mma8452_runtime_resume, NULL)
1816 static const struct i2c_device_id mma8452_id[] = {
1817 { "mma8451", mma8451 },
1818 { "mma8452", mma8452 },
1819 { "mma8453", mma8453 },
1820 { "mma8652", mma8652 },
1821 { "mma8653", mma8653 },
1822 { "fxls8471", fxls8471 },
1825 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1827 static struct i2c_driver mma8452_driver = {
1830 .of_match_table = mma8452_dt_ids,
1831 .pm = &mma8452_pm_ops,
1833 .probe = mma8452_probe,
1834 .remove = mma8452_remove,
1835 .id_table = mma8452_id,
1837 module_i2c_driver(mma8452_driver);
1839 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1840 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1841 MODULE_LICENSE("GPL");