1 // SPDX-License-Identifier: GPL-2.0
3 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
5 * device name digital output 7-bit I2C slave address (pin selectable)
6 * ---------------------------------------------------------------------
7 * MMA8451Q 14 bit 0x1c / 0x1d
8 * MMA8452Q 12 bit 0x1c / 0x1d
9 * MMA8453Q 10 bit 0x1c / 0x1d
10 * MMA8652FC 12 bit 0x1d
11 * MMA8653FC 10 bit 0x1d
12 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
14 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
15 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
18 * TODO: orientation events
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/iio/iio.h>
24 #include <linux/iio/sysfs.h>
25 #include <linux/iio/buffer.h>
26 #include <linux/iio/trigger.h>
27 #include <linux/iio/trigger_consumer.h>
28 #include <linux/iio/triggered_buffer.h>
29 #include <linux/iio/events.h>
30 #include <linux/delay.h>
31 #include <linux/of_device.h>
32 #include <linux/of_irq.h>
33 #include <linux/pm_runtime.h>
34 #include <linux/regulator/consumer.h>
36 #define MMA8452_STATUS 0x00
37 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
38 #define MMA8452_OUT_X 0x01 /* MSB first */
39 #define MMA8452_OUT_Y 0x03
40 #define MMA8452_OUT_Z 0x05
41 #define MMA8452_INT_SRC 0x0c
42 #define MMA8452_WHO_AM_I 0x0d
43 #define MMA8452_DATA_CFG 0x0e
44 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
45 #define MMA8452_DATA_CFG_FS_2G 0
46 #define MMA8452_DATA_CFG_FS_4G 1
47 #define MMA8452_DATA_CFG_FS_8G 2
48 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
49 #define MMA8452_HP_FILTER_CUTOFF 0x0f
50 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
51 #define MMA8452_FF_MT_CFG 0x15
52 #define MMA8452_FF_MT_CFG_OAE BIT(6)
53 #define MMA8452_FF_MT_CFG_ELE BIT(7)
54 #define MMA8452_FF_MT_SRC 0x16
55 #define MMA8452_FF_MT_SRC_XHE BIT(1)
56 #define MMA8452_FF_MT_SRC_YHE BIT(3)
57 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
58 #define MMA8452_FF_MT_THS 0x17
59 #define MMA8452_FF_MT_THS_MASK 0x7f
60 #define MMA8452_FF_MT_COUNT 0x18
61 #define MMA8452_FF_MT_CHAN_SHIFT 3
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_CHAN(chan) BIT(chan + 1)
64 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
65 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
66 #define MMA8452_TRANSIENT_SRC 0x1e
67 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
68 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
69 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
70 #define MMA8452_TRANSIENT_THS 0x1f
71 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
72 #define MMA8452_TRANSIENT_COUNT 0x20
73 #define MMA8452_TRANSIENT_CHAN_SHIFT 1
74 #define MMA8452_CTRL_REG1 0x2a
75 #define MMA8452_CTRL_ACTIVE BIT(0)
76 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
77 #define MMA8452_CTRL_DR_SHIFT 3
78 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
79 #define MMA8452_CTRL_REG2 0x2b
80 #define MMA8452_CTRL_REG2_RST BIT(6)
81 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
82 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
83 #define MMA8452_CTRL_REG4 0x2d
84 #define MMA8452_CTRL_REG5 0x2e
85 #define MMA8452_OFF_X 0x2f
86 #define MMA8452_OFF_Y 0x30
87 #define MMA8452_OFF_Z 0x31
89 #define MMA8452_MAX_REG 0x31
91 #define MMA8452_INT_DRDY BIT(0)
92 #define MMA8452_INT_FF_MT BIT(2)
93 #define MMA8452_INT_TRANS BIT(5)
95 #define MMA8451_DEVICE_ID 0x1a
96 #define MMA8452_DEVICE_ID 0x2a
97 #define MMA8453_DEVICE_ID 0x3a
98 #define MMA8652_DEVICE_ID 0x4a
99 #define MMA8653_DEVICE_ID 0x5a
100 #define FXLS8471_DEVICE_ID 0x6a
102 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
104 struct mma8452_data {
105 struct i2c_client *client;
109 const struct mma_chip_info *chip_info;
111 struct regulator *vdd_reg;
112 struct regulator *vddio_reg;
114 /* Ensure correct alignment of time stamp when present */
122 * struct mma8452_event_regs - chip specific data related to events
123 * @ev_cfg: event config register address
124 * @ev_cfg_ele: latch bit in event config register
125 * @ev_cfg_chan_shift: number of the bit to enable events in X
126 * direction; in event config register
127 * @ev_src: event source register address
128 * @ev_ths: event threshold register address
129 * @ev_ths_mask: mask for the threshold value
130 * @ev_count: event count (period) register address
132 * Since not all chips supported by the driver support comparing high pass
133 * filtered data for events (interrupts), different interrupt sources are
134 * used for different chips and the relevant registers are included here.
136 struct mma8452_event_regs {
139 u8 ev_cfg_chan_shift;
146 static const struct mma8452_event_regs ff_mt_ev_regs = {
147 .ev_cfg = MMA8452_FF_MT_CFG,
148 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
149 .ev_cfg_chan_shift = MMA8452_FF_MT_CHAN_SHIFT,
150 .ev_src = MMA8452_FF_MT_SRC,
151 .ev_ths = MMA8452_FF_MT_THS,
152 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
153 .ev_count = MMA8452_FF_MT_COUNT
156 static const struct mma8452_event_regs trans_ev_regs = {
157 .ev_cfg = MMA8452_TRANSIENT_CFG,
158 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
159 .ev_cfg_chan_shift = MMA8452_TRANSIENT_CHAN_SHIFT,
160 .ev_src = MMA8452_TRANSIENT_SRC,
161 .ev_ths = MMA8452_TRANSIENT_THS,
162 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
163 .ev_count = MMA8452_TRANSIENT_COUNT,
167 * struct mma_chip_info - chip specific data
168 * @chip_id: WHO_AM_I register's value
169 * @channels: struct iio_chan_spec matching the device's
171 * @num_channels: number of channels
172 * @mma_scales: scale factors for converting register values
173 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
174 * per mode: m/s^2 and micro m/s^2
175 * @all_events: all events supported by this chip
176 * @enabled_events: event flags enabled and handled by this driver
178 struct mma_chip_info {
181 const struct iio_chan_spec *channels;
183 const int mma_scales[3][2];
195 static int mma8452_drdy(struct mma8452_data *data)
199 while (tries-- > 0) {
200 int ret = i2c_smbus_read_byte_data(data->client,
204 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
207 if (data->sleep_val <= 20)
208 usleep_range(data->sleep_val * 250,
209 data->sleep_val * 500);
214 dev_err(&data->client->dev, "data not ready\n");
219 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
225 ret = pm_runtime_resume_and_get(&client->dev);
227 pm_runtime_mark_last_busy(&client->dev);
228 ret = pm_runtime_put_autosuspend(&client->dev);
232 dev_err(&client->dev,
233 "failed to change power state to %d\n", on);
242 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
244 int ret = mma8452_drdy(data);
249 ret = mma8452_set_runtime_pm_state(data->client, true);
253 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
254 3 * sizeof(__be16), (u8 *)buf);
256 ret = mma8452_set_runtime_pm_state(data->client, false);
261 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
267 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
268 vals[n][0], vals[n][1]);
270 /* replace trailing space by newline */
276 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
280 if (val == vals[n][0] && val2 == vals[n][1])
286 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
288 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
289 MMA8452_CTRL_DR_SHIFT;
292 static const int mma8452_samp_freq[8][2] = {
293 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
294 {6, 250000}, {1, 560000}
297 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
298 static const unsigned int mma8452_time_step_us[4][8] = {
299 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
300 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
301 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
302 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
305 /* Datasheet table "High-Pass Filter Cutoff Options" */
306 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
308 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
309 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
310 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
311 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
312 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
313 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
314 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
315 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
317 { /* low noise low power */
318 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
319 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
320 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
321 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
322 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
323 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
324 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
325 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
327 { /* high resolution */
328 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
329 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
330 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
331 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
332 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
333 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
334 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
335 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
338 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
339 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
340 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
341 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
342 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
343 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
344 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
345 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
349 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
350 static const u16 mma8452_os_ratio[4][8] = {
351 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
352 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
353 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
354 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
355 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
358 static int mma8452_get_power_mode(struct mma8452_data *data)
362 reg = i2c_smbus_read_byte_data(data->client,
367 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
368 MMA8452_CTRL_REG2_MODS_SHIFT);
371 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
372 struct device_attribute *attr,
375 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
376 ARRAY_SIZE(mma8452_samp_freq));
379 static ssize_t mma8452_show_scale_avail(struct device *dev,
380 struct device_attribute *attr,
383 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
384 to_i2c_client(dev)));
386 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
387 ARRAY_SIZE(data->chip_info->mma_scales));
390 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
391 struct device_attribute *attr,
394 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
395 struct mma8452_data *data = iio_priv(indio_dev);
398 i = mma8452_get_odr_index(data);
399 j = mma8452_get_power_mode(data);
403 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
404 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
407 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
408 struct device_attribute *attr,
411 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
412 struct mma8452_data *data = iio_priv(indio_dev);
413 int i = mma8452_get_odr_index(data);
418 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
419 if (val == mma8452_os_ratio[j][i])
422 val = mma8452_os_ratio[j][i];
424 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
431 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
432 static IIO_DEVICE_ATTR(in_accel_scale_available, 0444,
433 mma8452_show_scale_avail, NULL, 0);
434 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
435 0444, mma8452_show_hp_cutoff_avail, NULL, 0);
436 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, 0444,
437 mma8452_show_os_ratio_avail, NULL, 0);
439 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
442 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
443 ARRAY_SIZE(mma8452_samp_freq),
447 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
449 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
450 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
453 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
458 i = mma8452_get_odr_index(data);
459 j = mma8452_get_power_mode(data);
463 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
464 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
467 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
471 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
475 i = mma8452_get_odr_index(data);
476 j = mma8452_get_power_mode(data);
480 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
481 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
482 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
487 static int mma8452_read_raw(struct iio_dev *indio_dev,
488 struct iio_chan_spec const *chan,
489 int *val, int *val2, long mask)
491 struct mma8452_data *data = iio_priv(indio_dev);
496 case IIO_CHAN_INFO_RAW:
497 ret = iio_device_claim_direct_mode(indio_dev);
501 mutex_lock(&data->lock);
502 ret = mma8452_read(data, buffer);
503 mutex_unlock(&data->lock);
504 iio_device_release_direct_mode(indio_dev);
508 *val = sign_extend32(be16_to_cpu(
509 buffer[chan->scan_index]) >> chan->scan_type.shift,
510 chan->scan_type.realbits - 1);
513 case IIO_CHAN_INFO_SCALE:
514 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
515 *val = data->chip_info->mma_scales[i][0];
516 *val2 = data->chip_info->mma_scales[i][1];
518 return IIO_VAL_INT_PLUS_MICRO;
519 case IIO_CHAN_INFO_SAMP_FREQ:
520 i = mma8452_get_odr_index(data);
521 *val = mma8452_samp_freq[i][0];
522 *val2 = mma8452_samp_freq[i][1];
524 return IIO_VAL_INT_PLUS_MICRO;
525 case IIO_CHAN_INFO_CALIBBIAS:
526 ret = i2c_smbus_read_byte_data(data->client,
532 *val = sign_extend32(ret, 7);
535 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
536 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
537 ret = mma8452_read_hp_filter(data, val, val2);
545 return IIO_VAL_INT_PLUS_MICRO;
546 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
547 ret = mma8452_get_power_mode(data);
551 i = mma8452_get_odr_index(data);
553 *val = mma8452_os_ratio[ret][i];
560 static int mma8452_calculate_sleep(struct mma8452_data *data)
562 int ret, i = mma8452_get_odr_index(data);
564 if (mma8452_samp_freq[i][0] > 0)
565 ret = 1000 / mma8452_samp_freq[i][0];
569 return ret == 0 ? 1 : ret;
572 static int mma8452_standby(struct mma8452_data *data)
574 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
575 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
578 static int mma8452_active(struct mma8452_data *data)
580 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
584 /* returns >0 if active, 0 if in standby and <0 on error */
585 static int mma8452_is_active(struct mma8452_data *data)
589 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
593 return reg & MMA8452_CTRL_ACTIVE;
596 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
601 mutex_lock(&data->lock);
603 is_active = mma8452_is_active(data);
609 /* config can only be changed when in standby */
611 ret = mma8452_standby(data);
616 ret = i2c_smbus_write_byte_data(data->client, reg, val);
621 ret = mma8452_active(data);
628 mutex_unlock(&data->lock);
633 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
637 reg = i2c_smbus_read_byte_data(data->client,
642 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
643 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
645 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
648 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
649 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
653 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
657 return !(val & MMA8452_FF_MT_CFG_OAE);
660 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
664 if ((state && mma8452_freefall_mode_enabled(data)) ||
665 (!state && !(mma8452_freefall_mode_enabled(data))))
668 val = i2c_smbus_read_byte_data(data->client, MMA8452_FF_MT_CFG);
673 val |= BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
674 val |= BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
675 val |= BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
676 val &= ~MMA8452_FF_MT_CFG_OAE;
678 val &= ~BIT(idx_x + MMA8452_FF_MT_CHAN_SHIFT);
679 val &= ~BIT(idx_y + MMA8452_FF_MT_CHAN_SHIFT);
680 val &= ~BIT(idx_z + MMA8452_FF_MT_CHAN_SHIFT);
681 val |= MMA8452_FF_MT_CFG_OAE;
684 return mma8452_change_config(data, MMA8452_FF_MT_CFG, val);
687 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
692 i = mma8452_get_hp_filter_index(data, val, val2);
696 reg = i2c_smbus_read_byte_data(data->client,
697 MMA8452_HP_FILTER_CUTOFF);
701 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
704 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
707 static int mma8452_write_raw(struct iio_dev *indio_dev,
708 struct iio_chan_spec const *chan,
709 int val, int val2, long mask)
711 struct mma8452_data *data = iio_priv(indio_dev);
714 ret = iio_device_claim_direct_mode(indio_dev);
719 case IIO_CHAN_INFO_SAMP_FREQ:
720 i = mma8452_get_samp_freq_index(data, val, val2);
725 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
726 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
728 data->sleep_val = mma8452_calculate_sleep(data);
730 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
733 case IIO_CHAN_INFO_SCALE:
734 i = mma8452_get_scale_index(data, val, val2);
740 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
743 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
746 case IIO_CHAN_INFO_CALIBBIAS:
747 if (val < -128 || val > 127) {
752 ret = mma8452_change_config(data,
753 MMA8452_OFF_X + chan->scan_index,
757 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
758 if (val == 0 && val2 == 0) {
759 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
761 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
762 ret = mma8452_set_hp_filter_frequency(data, val, val2);
767 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
771 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
772 ret = mma8452_get_odr_index(data);
774 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
775 if (mma8452_os_ratio[i][ret] == val) {
776 ret = mma8452_set_power_mode(data, i);
786 iio_device_release_direct_mode(indio_dev);
790 static int mma8452_get_event_regs(struct mma8452_data *data,
791 const struct iio_chan_spec *chan, enum iio_event_direction dir,
792 const struct mma8452_event_regs **ev_reg)
797 switch (chan->type) {
800 case IIO_EV_DIR_RISING:
801 if ((data->chip_info->all_events
802 & MMA8452_INT_TRANS) &&
803 (data->chip_info->enabled_events
804 & MMA8452_INT_TRANS))
805 *ev_reg = &trans_ev_regs;
807 *ev_reg = &ff_mt_ev_regs;
809 case IIO_EV_DIR_FALLING:
810 *ev_reg = &ff_mt_ev_regs;
820 static int mma8452_read_event_value(struct iio_dev *indio_dev,
821 const struct iio_chan_spec *chan,
822 enum iio_event_type type,
823 enum iio_event_direction dir,
824 enum iio_event_info info,
827 struct mma8452_data *data = iio_priv(indio_dev);
828 int ret, us, power_mode;
829 const struct mma8452_event_regs *ev_regs;
831 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
836 case IIO_EV_INFO_VALUE:
837 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_ths);
841 *val = ret & ev_regs->ev_ths_mask;
845 case IIO_EV_INFO_PERIOD:
846 ret = i2c_smbus_read_byte_data(data->client, ev_regs->ev_count);
850 power_mode = mma8452_get_power_mode(data);
854 us = ret * mma8452_time_step_us[power_mode][
855 mma8452_get_odr_index(data)];
856 *val = us / USEC_PER_SEC;
857 *val2 = us % USEC_PER_SEC;
859 return IIO_VAL_INT_PLUS_MICRO;
861 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
862 ret = i2c_smbus_read_byte_data(data->client,
863 MMA8452_TRANSIENT_CFG);
867 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
871 ret = mma8452_read_hp_filter(data, val, val2);
876 return IIO_VAL_INT_PLUS_MICRO;
883 static int mma8452_write_event_value(struct iio_dev *indio_dev,
884 const struct iio_chan_spec *chan,
885 enum iio_event_type type,
886 enum iio_event_direction dir,
887 enum iio_event_info info,
890 struct mma8452_data *data = iio_priv(indio_dev);
892 const struct mma8452_event_regs *ev_regs;
894 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
899 case IIO_EV_INFO_VALUE:
900 if (val < 0 || val > ev_regs->ev_ths_mask)
903 return mma8452_change_config(data, ev_regs->ev_ths, val);
905 case IIO_EV_INFO_PERIOD:
906 ret = mma8452_get_power_mode(data);
910 steps = (val * USEC_PER_SEC + val2) /
911 mma8452_time_step_us[ret][
912 mma8452_get_odr_index(data)];
914 if (steps < 0 || steps > 0xff)
917 return mma8452_change_config(data, ev_regs->ev_count, steps);
919 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
920 reg = i2c_smbus_read_byte_data(data->client,
921 MMA8452_TRANSIENT_CFG);
925 if (val == 0 && val2 == 0) {
926 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
928 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
929 ret = mma8452_set_hp_filter_frequency(data, val, val2);
934 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
941 static int mma8452_read_event_config(struct iio_dev *indio_dev,
942 const struct iio_chan_spec *chan,
943 enum iio_event_type type,
944 enum iio_event_direction dir)
946 struct mma8452_data *data = iio_priv(indio_dev);
948 const struct mma8452_event_regs *ev_regs;
950 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
955 case IIO_EV_DIR_FALLING:
956 return mma8452_freefall_mode_enabled(data);
957 case IIO_EV_DIR_RISING:
958 ret = i2c_smbus_read_byte_data(data->client,
963 return !!(ret & BIT(chan->scan_index +
964 ev_regs->ev_cfg_chan_shift));
970 static int mma8452_write_event_config(struct iio_dev *indio_dev,
971 const struct iio_chan_spec *chan,
972 enum iio_event_type type,
973 enum iio_event_direction dir,
976 struct mma8452_data *data = iio_priv(indio_dev);
978 const struct mma8452_event_regs *ev_regs;
980 ret = mma8452_get_event_regs(data, chan, dir, &ev_regs);
984 ret = mma8452_set_runtime_pm_state(data->client, state);
989 case IIO_EV_DIR_FALLING:
990 return mma8452_set_freefall_mode(data, state);
991 case IIO_EV_DIR_RISING:
992 val = i2c_smbus_read_byte_data(data->client, ev_regs->ev_cfg);
997 if (mma8452_freefall_mode_enabled(data)) {
998 val &= ~BIT(idx_x + ev_regs->ev_cfg_chan_shift);
999 val &= ~BIT(idx_y + ev_regs->ev_cfg_chan_shift);
1000 val &= ~BIT(idx_z + ev_regs->ev_cfg_chan_shift);
1001 val |= MMA8452_FF_MT_CFG_OAE;
1003 val |= BIT(chan->scan_index +
1004 ev_regs->ev_cfg_chan_shift);
1006 if (mma8452_freefall_mode_enabled(data))
1009 val &= ~BIT(chan->scan_index +
1010 ev_regs->ev_cfg_chan_shift);
1013 val |= ev_regs->ev_cfg_ele;
1015 return mma8452_change_config(data, ev_regs->ev_cfg, val);
1021 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
1023 struct mma8452_data *data = iio_priv(indio_dev);
1024 s64 ts = iio_get_time_ns(indio_dev);
1027 src = i2c_smbus_read_byte_data(data->client, MMA8452_TRANSIENT_SRC);
1031 if (src & MMA8452_TRANSIENT_SRC_XTRANSE)
1032 iio_push_event(indio_dev,
1033 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
1038 if (src & MMA8452_TRANSIENT_SRC_YTRANSE)
1039 iio_push_event(indio_dev,
1040 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
1045 if (src & MMA8452_TRANSIENT_SRC_ZTRANSE)
1046 iio_push_event(indio_dev,
1047 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
1053 static irqreturn_t mma8452_interrupt(int irq, void *p)
1055 struct iio_dev *indio_dev = p;
1056 struct mma8452_data *data = iio_priv(indio_dev);
1060 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
1064 if (!(src & (data->chip_info->enabled_events | MMA8452_INT_DRDY)))
1067 if (src & MMA8452_INT_DRDY) {
1068 iio_trigger_poll_chained(indio_dev->trig);
1072 if (src & MMA8452_INT_FF_MT) {
1073 if (mma8452_freefall_mode_enabled(data)) {
1074 s64 ts = iio_get_time_ns(indio_dev);
1076 iio_push_event(indio_dev,
1077 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
1078 IIO_MOD_X_AND_Y_AND_Z,
1080 IIO_EV_DIR_FALLING),
1086 if (src & MMA8452_INT_TRANS) {
1087 mma8452_transient_interrupt(indio_dev);
1094 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1096 struct iio_poll_func *pf = p;
1097 struct iio_dev *indio_dev = pf->indio_dev;
1098 struct mma8452_data *data = iio_priv(indio_dev);
1101 ret = mma8452_read(data, data->buffer.channels);
1105 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1106 iio_get_time_ns(indio_dev));
1109 iio_trigger_notify_done(indio_dev->trig);
1114 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1115 unsigned int reg, unsigned int writeval,
1116 unsigned int *readval)
1119 struct mma8452_data *data = iio_priv(indio_dev);
1121 if (reg > MMA8452_MAX_REG)
1125 return mma8452_change_config(data, reg, writeval);
1127 ret = i2c_smbus_read_byte_data(data->client, reg);
1136 static const struct iio_event_spec mma8452_freefall_event[] = {
1138 .type = IIO_EV_TYPE_MAG,
1139 .dir = IIO_EV_DIR_FALLING,
1140 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1141 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1142 BIT(IIO_EV_INFO_PERIOD) |
1143 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1147 static const struct iio_event_spec mma8652_freefall_event[] = {
1149 .type = IIO_EV_TYPE_MAG,
1150 .dir = IIO_EV_DIR_FALLING,
1151 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1152 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1153 BIT(IIO_EV_INFO_PERIOD)
1157 static const struct iio_event_spec mma8452_transient_event[] = {
1159 .type = IIO_EV_TYPE_MAG,
1160 .dir = IIO_EV_DIR_RISING,
1161 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1162 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1163 BIT(IIO_EV_INFO_PERIOD) |
1164 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1168 static const struct iio_event_spec mma8452_motion_event[] = {
1170 .type = IIO_EV_TYPE_MAG,
1171 .dir = IIO_EV_DIR_RISING,
1172 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1173 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1174 BIT(IIO_EV_INFO_PERIOD)
1179 * Threshold is configured in fixed 8G/127 steps regardless of
1180 * currently selected scale for measurement.
1182 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1184 static struct attribute *mma8452_event_attributes[] = {
1185 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1189 static const struct attribute_group mma8452_event_attribute_group = {
1190 .attrs = mma8452_event_attributes,
1193 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1194 .type = IIO_ACCEL, \
1196 .channel2 = modifier, \
1198 .event_spec = mma8452_freefall_event, \
1199 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1202 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1203 .type = IIO_ACCEL, \
1205 .channel2 = modifier, \
1207 .event_spec = mma8652_freefall_event, \
1208 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1211 #define MMA8452_CHANNEL(axis, idx, bits) { \
1212 .type = IIO_ACCEL, \
1214 .channel2 = IIO_MOD_##axis, \
1215 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1216 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1217 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1218 BIT(IIO_CHAN_INFO_SCALE) | \
1219 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1220 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1221 .scan_index = idx, \
1224 .realbits = (bits), \
1225 .storagebits = 16, \
1226 .shift = 16 - (bits), \
1227 .endianness = IIO_BE, \
1229 .event_spec = mma8452_transient_event, \
1230 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1233 #define MMA8652_CHANNEL(axis, idx, bits) { \
1234 .type = IIO_ACCEL, \
1236 .channel2 = IIO_MOD_##axis, \
1237 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1238 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1239 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1240 BIT(IIO_CHAN_INFO_SCALE) | \
1241 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1242 .scan_index = idx, \
1245 .realbits = (bits), \
1246 .storagebits = 16, \
1247 .shift = 16 - (bits), \
1248 .endianness = IIO_BE, \
1250 .event_spec = mma8452_motion_event, \
1251 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1254 static const struct iio_chan_spec mma8451_channels[] = {
1255 MMA8452_CHANNEL(X, idx_x, 14),
1256 MMA8452_CHANNEL(Y, idx_y, 14),
1257 MMA8452_CHANNEL(Z, idx_z, 14),
1258 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1259 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1262 static const struct iio_chan_spec mma8452_channels[] = {
1263 MMA8452_CHANNEL(X, idx_x, 12),
1264 MMA8452_CHANNEL(Y, idx_y, 12),
1265 MMA8452_CHANNEL(Z, idx_z, 12),
1266 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1267 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1270 static const struct iio_chan_spec mma8453_channels[] = {
1271 MMA8452_CHANNEL(X, idx_x, 10),
1272 MMA8452_CHANNEL(Y, idx_y, 10),
1273 MMA8452_CHANNEL(Z, idx_z, 10),
1274 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1275 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1278 static const struct iio_chan_spec mma8652_channels[] = {
1279 MMA8652_CHANNEL(X, idx_x, 12),
1280 MMA8652_CHANNEL(Y, idx_y, 12),
1281 MMA8652_CHANNEL(Z, idx_z, 12),
1282 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1283 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1286 static const struct iio_chan_spec mma8653_channels[] = {
1287 MMA8652_CHANNEL(X, idx_x, 10),
1288 MMA8652_CHANNEL(Y, idx_y, 10),
1289 MMA8652_CHANNEL(Z, idx_z, 10),
1290 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1291 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1303 static const struct mma_chip_info mma_chip_info_table[] = {
1306 .chip_id = MMA8451_DEVICE_ID,
1307 .channels = mma8451_channels,
1308 .num_channels = ARRAY_SIZE(mma8451_channels),
1310 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1311 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1313 * The userspace interface uses m/s^2 and we declare micro units
1314 * So scale factor for 12 bit here is given by:
1315 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1317 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1319 * Although we enable the interrupt sources once and for
1320 * all here the event detection itself is not enabled until
1321 * userspace asks for it by mma8452_write_event_config()
1323 .all_events = MMA8452_INT_DRDY |
1326 .enabled_events = MMA8452_INT_TRANS |
1331 .chip_id = MMA8452_DEVICE_ID,
1332 .channels = mma8452_channels,
1333 .num_channels = ARRAY_SIZE(mma8452_channels),
1334 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1336 * Although we enable the interrupt sources once and for
1337 * all here the event detection itself is not enabled until
1338 * userspace asks for it by mma8452_write_event_config()
1340 .all_events = MMA8452_INT_DRDY |
1343 .enabled_events = MMA8452_INT_TRANS |
1348 .chip_id = MMA8453_DEVICE_ID,
1349 .channels = mma8453_channels,
1350 .num_channels = ARRAY_SIZE(mma8453_channels),
1351 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1353 * Although we enable the interrupt sources once and for
1354 * all here the event detection itself is not enabled until
1355 * userspace asks for it by mma8452_write_event_config()
1357 .all_events = MMA8452_INT_DRDY |
1360 .enabled_events = MMA8452_INT_TRANS |
1365 .chip_id = MMA8652_DEVICE_ID,
1366 .channels = mma8652_channels,
1367 .num_channels = ARRAY_SIZE(mma8652_channels),
1368 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1369 .all_events = MMA8452_INT_DRDY |
1371 .enabled_events = MMA8452_INT_FF_MT,
1375 .chip_id = MMA8653_DEVICE_ID,
1376 .channels = mma8653_channels,
1377 .num_channels = ARRAY_SIZE(mma8653_channels),
1378 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1380 * Although we enable the interrupt sources once and for
1381 * all here the event detection itself is not enabled until
1382 * userspace asks for it by mma8452_write_event_config()
1384 .all_events = MMA8452_INT_DRDY |
1386 .enabled_events = MMA8452_INT_FF_MT,
1390 .chip_id = FXLS8471_DEVICE_ID,
1391 .channels = mma8451_channels,
1392 .num_channels = ARRAY_SIZE(mma8451_channels),
1393 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1395 * Although we enable the interrupt sources once and for
1396 * all here the event detection itself is not enabled until
1397 * userspace asks for it by mma8452_write_event_config()
1399 .all_events = MMA8452_INT_DRDY |
1402 .enabled_events = MMA8452_INT_TRANS |
1407 static struct attribute *mma8452_attributes[] = {
1408 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1409 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1410 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1411 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1415 static const struct attribute_group mma8452_group = {
1416 .attrs = mma8452_attributes,
1419 static const struct iio_info mma8452_info = {
1420 .attrs = &mma8452_group,
1421 .read_raw = &mma8452_read_raw,
1422 .write_raw = &mma8452_write_raw,
1423 .event_attrs = &mma8452_event_attribute_group,
1424 .read_event_value = &mma8452_read_event_value,
1425 .write_event_value = &mma8452_write_event_value,
1426 .read_event_config = &mma8452_read_event_config,
1427 .write_event_config = &mma8452_write_event_config,
1428 .debugfs_reg_access = &mma8452_reg_access_dbg,
1431 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1433 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1436 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1437 struct mma8452_data *data = iio_priv(indio_dev);
1440 ret = mma8452_set_runtime_pm_state(data->client, state);
1444 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1449 reg |= MMA8452_INT_DRDY;
1451 reg &= ~MMA8452_INT_DRDY;
1453 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1456 static const struct iio_trigger_ops mma8452_trigger_ops = {
1457 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1458 .validate_device = iio_trigger_validate_own_device,
1461 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1463 struct mma8452_data *data = iio_priv(indio_dev);
1464 struct iio_trigger *trig;
1467 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1469 iio_device_id(indio_dev));
1473 trig->ops = &mma8452_trigger_ops;
1474 iio_trigger_set_drvdata(trig, indio_dev);
1476 ret = iio_trigger_register(trig);
1480 indio_dev->trig = iio_trigger_get(trig);
1485 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1487 if (indio_dev->trig)
1488 iio_trigger_unregister(indio_dev->trig);
1491 static int mma8452_reset(struct i2c_client *client)
1496 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1497 MMA8452_CTRL_REG2_RST);
1501 for (i = 0; i < 10; i++) {
1502 usleep_range(100, 200);
1503 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1505 continue; /* I2C comm reset */
1508 if (!(ret & MMA8452_CTRL_REG2_RST))
1515 static const struct of_device_id mma8452_dt_ids[] = {
1516 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1517 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1518 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1519 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1520 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1521 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1524 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1526 static int mma8452_probe(struct i2c_client *client,
1527 const struct i2c_device_id *id)
1529 struct mma8452_data *data;
1530 struct iio_dev *indio_dev;
1533 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1537 data = iio_priv(indio_dev);
1538 data->client = client;
1539 mutex_init(&data->lock);
1541 data->chip_info = device_get_match_data(&client->dev);
1542 if (!data->chip_info && id) {
1543 data->chip_info = &mma_chip_info_table[id->driver_data];
1545 dev_err(&client->dev, "unknown device model\n");
1549 data->vdd_reg = devm_regulator_get(&client->dev, "vdd");
1550 if (IS_ERR(data->vdd_reg))
1551 return dev_err_probe(&client->dev, PTR_ERR(data->vdd_reg),
1552 "failed to get VDD regulator!\n");
1554 data->vddio_reg = devm_regulator_get(&client->dev, "vddio");
1555 if (IS_ERR(data->vddio_reg))
1556 return dev_err_probe(&client->dev, PTR_ERR(data->vddio_reg),
1557 "failed to get VDDIO regulator!\n");
1559 ret = regulator_enable(data->vdd_reg);
1561 dev_err(&client->dev, "failed to enable VDD regulator!\n");
1565 ret = regulator_enable(data->vddio_reg);
1567 dev_err(&client->dev, "failed to enable VDDIO regulator!\n");
1568 goto disable_regulator_vdd;
1571 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1573 goto disable_regulators;
1576 case MMA8451_DEVICE_ID:
1577 case MMA8452_DEVICE_ID:
1578 case MMA8453_DEVICE_ID:
1579 case MMA8652_DEVICE_ID:
1580 case MMA8653_DEVICE_ID:
1581 case FXLS8471_DEVICE_ID:
1582 if (ret == data->chip_info->chip_id)
1587 goto disable_regulators;
1590 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1591 data->chip_info->name, data->chip_info->chip_id);
1593 i2c_set_clientdata(client, indio_dev);
1594 indio_dev->info = &mma8452_info;
1595 indio_dev->name = data->chip_info->name;
1596 indio_dev->modes = INDIO_DIRECT_MODE;
1597 indio_dev->channels = data->chip_info->channels;
1598 indio_dev->num_channels = data->chip_info->num_channels;
1599 indio_dev->available_scan_masks = mma8452_scan_masks;
1601 ret = mma8452_reset(client);
1603 goto disable_regulators;
1605 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1606 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1609 goto disable_regulators;
1612 * By default set transient threshold to max to avoid events if
1613 * enabling without configuring threshold.
1615 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1616 MMA8452_TRANSIENT_THS_MASK);
1618 goto disable_regulators;
1623 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1625 if (irq2 == client->irq) {
1626 dev_dbg(&client->dev, "using interrupt line INT2\n");
1628 ret = i2c_smbus_write_byte_data(client,
1630 data->chip_info->all_events);
1632 goto disable_regulators;
1634 dev_dbg(&client->dev, "using interrupt line INT1\n");
1637 ret = i2c_smbus_write_byte_data(client,
1639 data->chip_info->enabled_events);
1641 goto disable_regulators;
1643 ret = mma8452_trigger_setup(indio_dev);
1645 goto disable_regulators;
1648 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1649 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1651 data->sleep_val = mma8452_calculate_sleep(data);
1653 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1656 goto trigger_cleanup;
1658 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1659 mma8452_trigger_handler, NULL);
1661 goto trigger_cleanup;
1664 ret = devm_request_threaded_irq(&client->dev,
1666 NULL, mma8452_interrupt,
1667 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1668 client->name, indio_dev);
1670 goto buffer_cleanup;
1673 ret = pm_runtime_set_active(&client->dev);
1675 goto buffer_cleanup;
1677 pm_runtime_enable(&client->dev);
1678 pm_runtime_set_autosuspend_delay(&client->dev,
1679 MMA8452_AUTO_SUSPEND_DELAY_MS);
1680 pm_runtime_use_autosuspend(&client->dev);
1682 ret = iio_device_register(indio_dev);
1684 goto buffer_cleanup;
1686 ret = mma8452_set_freefall_mode(data, false);
1688 goto unregister_device;
1693 iio_device_unregister(indio_dev);
1696 iio_triggered_buffer_cleanup(indio_dev);
1699 mma8452_trigger_cleanup(indio_dev);
1702 regulator_disable(data->vddio_reg);
1704 disable_regulator_vdd:
1705 regulator_disable(data->vdd_reg);
1710 static int mma8452_remove(struct i2c_client *client)
1712 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1713 struct mma8452_data *data = iio_priv(indio_dev);
1715 iio_device_unregister(indio_dev);
1717 pm_runtime_disable(&client->dev);
1718 pm_runtime_set_suspended(&client->dev);
1720 iio_triggered_buffer_cleanup(indio_dev);
1721 mma8452_trigger_cleanup(indio_dev);
1722 mma8452_standby(iio_priv(indio_dev));
1724 regulator_disable(data->vddio_reg);
1725 regulator_disable(data->vdd_reg);
1731 static int mma8452_runtime_suspend(struct device *dev)
1733 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1734 struct mma8452_data *data = iio_priv(indio_dev);
1737 mutex_lock(&data->lock);
1738 ret = mma8452_standby(data);
1739 mutex_unlock(&data->lock);
1741 dev_err(&data->client->dev, "powering off device failed\n");
1745 ret = regulator_disable(data->vddio_reg);
1747 dev_err(dev, "failed to disable VDDIO regulator\n");
1751 ret = regulator_disable(data->vdd_reg);
1753 dev_err(dev, "failed to disable VDD regulator\n");
1760 static int mma8452_runtime_resume(struct device *dev)
1762 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1763 struct mma8452_data *data = iio_priv(indio_dev);
1766 ret = regulator_enable(data->vdd_reg);
1768 dev_err(dev, "failed to enable VDD regulator\n");
1772 ret = regulator_enable(data->vddio_reg);
1774 dev_err(dev, "failed to enable VDDIO regulator\n");
1775 regulator_disable(data->vdd_reg);
1779 ret = mma8452_active(data);
1781 goto runtime_resume_failed;
1783 ret = mma8452_get_odr_index(data);
1784 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1786 usleep_range(sleep_val * 1000, 20000);
1788 msleep_interruptible(sleep_val);
1792 runtime_resume_failed:
1793 regulator_disable(data->vddio_reg);
1794 regulator_disable(data->vdd_reg);
1800 static const struct dev_pm_ops mma8452_pm_ops = {
1801 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1802 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1803 mma8452_runtime_resume, NULL)
1806 static const struct i2c_device_id mma8452_id[] = {
1807 { "mma8451", mma8451 },
1808 { "mma8452", mma8452 },
1809 { "mma8453", mma8453 },
1810 { "mma8652", mma8652 },
1811 { "mma8653", mma8653 },
1812 { "fxls8471", fxls8471 },
1815 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1817 static struct i2c_driver mma8452_driver = {
1820 .of_match_table = mma8452_dt_ids,
1821 .pm = &mma8452_pm_ops,
1823 .probe = mma8452_probe,
1824 .remove = mma8452_remove,
1825 .id_table = mma8452_id,
1827 module_i2c_driver(mma8452_driver);
1829 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1830 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1831 MODULE_LICENSE("GPL");