2 * mma8452.c - Support for following Freescale / NXP 3-axis accelerometers:
4 * device name digital output 7-bit I2C slave address (pin selectable)
5 * ---------------------------------------------------------------------
6 * MMA8451Q 14 bit 0x1c / 0x1d
7 * MMA8452Q 12 bit 0x1c / 0x1d
8 * MMA8453Q 10 bit 0x1c / 0x1d
9 * MMA8652FC 12 bit 0x1d
10 * MMA8653FC 10 bit 0x1d
11 * FXLS8471Q 14 bit 0x1e / 0x1d / 0x1c / 0x1f
13 * Copyright 2015 Martin Kepplinger <martink@posteo.de>
14 * Copyright 2014 Peter Meerwald <pmeerw@pmeerw.net>
16 * This file is subject to the terms and conditions of version 2 of
17 * the GNU General Public License. See the file COPYING in the main
18 * directory of this archive for more details.
20 * TODO: orientation events
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/iio/iio.h>
26 #include <linux/iio/sysfs.h>
27 #include <linux/iio/buffer.h>
28 #include <linux/iio/trigger.h>
29 #include <linux/iio/trigger_consumer.h>
30 #include <linux/iio/triggered_buffer.h>
31 #include <linux/iio/events.h>
32 #include <linux/delay.h>
33 #include <linux/of_device.h>
34 #include <linux/of_irq.h>
35 #include <linux/pm_runtime.h>
37 #define MMA8452_STATUS 0x00
38 #define MMA8452_STATUS_DRDY (BIT(2) | BIT(1) | BIT(0))
39 #define MMA8452_OUT_X 0x01 /* MSB first */
40 #define MMA8452_OUT_Y 0x03
41 #define MMA8452_OUT_Z 0x05
42 #define MMA8452_INT_SRC 0x0c
43 #define MMA8452_WHO_AM_I 0x0d
44 #define MMA8452_DATA_CFG 0x0e
45 #define MMA8452_DATA_CFG_FS_MASK GENMASK(1, 0)
46 #define MMA8452_DATA_CFG_FS_2G 0
47 #define MMA8452_DATA_CFG_FS_4G 1
48 #define MMA8452_DATA_CFG_FS_8G 2
49 #define MMA8452_DATA_CFG_HPF_MASK BIT(4)
50 #define MMA8452_HP_FILTER_CUTOFF 0x0f
51 #define MMA8452_HP_FILTER_CUTOFF_SEL_MASK GENMASK(1, 0)
52 #define MMA8452_FF_MT_CFG 0x15
53 #define MMA8452_FF_MT_CFG_OAE BIT(6)
54 #define MMA8452_FF_MT_CFG_ELE BIT(7)
55 #define MMA8452_FF_MT_SRC 0x16
56 #define MMA8452_FF_MT_SRC_XHE BIT(1)
57 #define MMA8452_FF_MT_SRC_YHE BIT(3)
58 #define MMA8452_FF_MT_SRC_ZHE BIT(5)
59 #define MMA8452_FF_MT_THS 0x17
60 #define MMA8452_FF_MT_THS_MASK 0x7f
61 #define MMA8452_FF_MT_COUNT 0x18
62 #define MMA8452_TRANSIENT_CFG 0x1d
63 #define MMA8452_TRANSIENT_CFG_HPF_BYP BIT(0)
64 #define MMA8452_TRANSIENT_CFG_ELE BIT(4)
65 #define MMA8452_TRANSIENT_SRC 0x1e
66 #define MMA8452_TRANSIENT_SRC_XTRANSE BIT(1)
67 #define MMA8452_TRANSIENT_SRC_YTRANSE BIT(3)
68 #define MMA8452_TRANSIENT_SRC_ZTRANSE BIT(5)
69 #define MMA8452_TRANSIENT_THS 0x1f
70 #define MMA8452_TRANSIENT_THS_MASK GENMASK(6, 0)
71 #define MMA8452_TRANSIENT_COUNT 0x20
72 #define MMA8452_CTRL_REG1 0x2a
73 #define MMA8452_CTRL_ACTIVE BIT(0)
74 #define MMA8452_CTRL_DR_MASK GENMASK(5, 3)
75 #define MMA8452_CTRL_DR_SHIFT 3
76 #define MMA8452_CTRL_DR_DEFAULT 0x4 /* 50 Hz sample frequency */
77 #define MMA8452_CTRL_REG2 0x2b
78 #define MMA8452_CTRL_REG2_RST BIT(6)
79 #define MMA8452_CTRL_REG2_MODS_SHIFT 3
80 #define MMA8452_CTRL_REG2_MODS_MASK 0x1b
81 #define MMA8452_CTRL_REG4 0x2d
82 #define MMA8452_CTRL_REG5 0x2e
83 #define MMA8452_OFF_X 0x2f
84 #define MMA8452_OFF_Y 0x30
85 #define MMA8452_OFF_Z 0x31
87 #define MMA8452_MAX_REG 0x31
89 #define MMA8452_INT_DRDY BIT(0)
90 #define MMA8452_INT_FF_MT BIT(2)
91 #define MMA8452_INT_TRANS BIT(5)
93 #define MMA8451_DEVICE_ID 0x1a
94 #define MMA8452_DEVICE_ID 0x2a
95 #define MMA8453_DEVICE_ID 0x3a
96 #define MMA8652_DEVICE_ID 0x4a
97 #define MMA8653_DEVICE_ID 0x5a
98 #define FXLS8471_DEVICE_ID 0x6a
100 #define MMA8452_AUTO_SUSPEND_DELAY_MS 2000
102 struct mma8452_data {
103 struct i2c_client *client;
107 const struct mma_chip_info *chip_info;
109 /* Ensure correct alignment of time stamp when present */
117 * struct mma_chip_info - chip specific data
118 * @chip_id: WHO_AM_I register's value
119 * @channels: struct iio_chan_spec matching the device's
121 * @num_channels: number of channels
122 * @mma_scales: scale factors for converting register values
123 * to m/s^2; 3 modes: 2g, 4g, 8g; 2 integers
124 * per mode: m/s^2 and micro m/s^2
125 * @ev_cfg: event config register address
126 * @ev_cfg_ele: latch bit in event config register
127 * @ev_cfg_chan_shift: number of the bit to enable events in X
128 * direction; in event config register
129 * @ev_src: event source register address
130 * @ev_src_xe: bit in event source register that indicates
131 * an event in X direction
132 * @ev_src_ye: bit in event source register that indicates
133 * an event in Y direction
134 * @ev_src_ze: bit in event source register that indicates
135 * an event in Z direction
136 * @ev_ths: event threshold register address
137 * @ev_ths_mask: mask for the threshold value
138 * @ev_count: event count (period) register address
140 * Since not all chips supported by the driver support comparing high pass
141 * filtered data for events (interrupts), different interrupt sources are
142 * used for different chips and the relevant registers are included here.
144 struct mma_chip_info {
146 const struct iio_chan_spec *channels;
148 const int mma_scales[3][2];
151 u8 ev_cfg_chan_shift;
168 static int mma8452_drdy(struct mma8452_data *data)
172 while (tries-- > 0) {
173 int ret = i2c_smbus_read_byte_data(data->client,
177 if ((ret & MMA8452_STATUS_DRDY) == MMA8452_STATUS_DRDY)
183 dev_err(&data->client->dev, "data not ready\n");
188 static int mma8452_set_runtime_pm_state(struct i2c_client *client, bool on)
194 ret = pm_runtime_get_sync(&client->dev);
196 pm_runtime_mark_last_busy(&client->dev);
197 ret = pm_runtime_put_autosuspend(&client->dev);
201 dev_err(&client->dev,
202 "failed to change power state to %d\n", on);
204 pm_runtime_put_noidle(&client->dev);
213 static int mma8452_read(struct mma8452_data *data, __be16 buf[3])
215 int ret = mma8452_drdy(data);
220 ret = mma8452_set_runtime_pm_state(data->client, true);
224 ret = i2c_smbus_read_i2c_block_data(data->client, MMA8452_OUT_X,
225 3 * sizeof(__be16), (u8 *)buf);
227 ret = mma8452_set_runtime_pm_state(data->client, false);
232 static ssize_t mma8452_show_int_plus_micros(char *buf, const int (*vals)[2],
238 len += scnprintf(buf + len, PAGE_SIZE - len, "%d.%06d ",
239 vals[n][0], vals[n][1]);
241 /* replace trailing space by newline */
247 static int mma8452_get_int_plus_micros_index(const int (*vals)[2], int n,
251 if (val == vals[n][0] && val2 == vals[n][1])
257 static unsigned int mma8452_get_odr_index(struct mma8452_data *data)
259 return (data->ctrl_reg1 & MMA8452_CTRL_DR_MASK) >>
260 MMA8452_CTRL_DR_SHIFT;
263 static const int mma8452_samp_freq[8][2] = {
264 {800, 0}, {400, 0}, {200, 0}, {100, 0}, {50, 0}, {12, 500000},
265 {6, 250000}, {1, 560000}
268 /* Datasheet table: step time "Relationship with the ODR" (sample frequency) */
269 static const unsigned int mma8452_transient_time_step_us[4][8] = {
270 { 1250, 2500, 5000, 10000, 20000, 20000, 20000, 20000 }, /* normal */
271 { 1250, 2500, 5000, 10000, 20000, 80000, 80000, 80000 }, /* l p l n */
272 { 1250, 2500, 2500, 2500, 2500, 2500, 2500, 2500 }, /* high res*/
273 { 1250, 2500, 5000, 10000, 20000, 80000, 160000, 160000 } /* l p */
276 /* Datasheet table "High-Pass Filter Cutoff Options" */
277 static const int mma8452_hp_filter_cutoff[4][8][4][2] = {
279 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 800 Hz sample */
280 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }, /* 400 Hz sample */
281 { {8, 0}, {4, 0}, {2, 0}, {1, 0} }, /* 200 Hz sample */
282 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} }, /* 100 Hz sample */
283 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 50 Hz sample */
284 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 12.5 Hz sample */
285 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} }, /* 6.25 Hz sample */
286 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} } /* 1.56 Hz sample */
288 { /* low noise low power */
289 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
290 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
291 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
292 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
293 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
294 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
295 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} },
296 { {0, 500000}, {0, 250000}, {0, 125000}, {0, 063000} }
298 { /* high resolution */
299 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
300 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
301 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
302 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
303 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
304 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
305 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
306 { {16, 0}, {8, 0}, {4, 0}, {2, 0} }
309 { {16, 0}, {8, 0}, {4, 0}, {2, 0} },
310 { {8, 0}, {4, 0}, {2, 0}, {1, 0} },
311 { {4, 0}, {2, 0}, {1, 0}, {0, 500000} },
312 { {2, 0}, {1, 0}, {0, 500000}, {0, 250000} },
313 { {1, 0}, {0, 500000}, {0, 250000}, {0, 125000} },
314 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
315 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} },
316 { {0, 250000}, {0, 125000}, {0, 063000}, {0, 031000} }
320 /* Datasheet table "MODS Oversampling modes averaging values at each ODR" */
321 static const u16 mma8452_os_ratio[4][8] = {
322 /* 800 Hz, 400 Hz, ... , 1.56 Hz */
323 { 2, 4, 4, 4, 4, 16, 32, 128 }, /* normal */
324 { 2, 4, 4, 4, 4, 4, 8, 32 }, /* low power low noise */
325 { 2, 4, 8, 16, 32, 128, 256, 1024 }, /* high resolution */
326 { 2, 2, 2, 2, 2, 2, 4, 16 } /* low power */
329 static int mma8452_get_power_mode(struct mma8452_data *data)
333 reg = i2c_smbus_read_byte_data(data->client,
338 return ((reg & MMA8452_CTRL_REG2_MODS_MASK) >>
339 MMA8452_CTRL_REG2_MODS_SHIFT);
342 static ssize_t mma8452_show_samp_freq_avail(struct device *dev,
343 struct device_attribute *attr,
346 return mma8452_show_int_plus_micros(buf, mma8452_samp_freq,
347 ARRAY_SIZE(mma8452_samp_freq));
350 static ssize_t mma8452_show_scale_avail(struct device *dev,
351 struct device_attribute *attr,
354 struct mma8452_data *data = iio_priv(i2c_get_clientdata(
355 to_i2c_client(dev)));
357 return mma8452_show_int_plus_micros(buf, data->chip_info->mma_scales,
358 ARRAY_SIZE(data->chip_info->mma_scales));
361 static ssize_t mma8452_show_hp_cutoff_avail(struct device *dev,
362 struct device_attribute *attr,
365 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
366 struct mma8452_data *data = iio_priv(indio_dev);
369 i = mma8452_get_odr_index(data);
370 j = mma8452_get_power_mode(data);
374 return mma8452_show_int_plus_micros(buf, mma8452_hp_filter_cutoff[j][i],
375 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]));
378 static ssize_t mma8452_show_os_ratio_avail(struct device *dev,
379 struct device_attribute *attr,
382 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
383 struct mma8452_data *data = iio_priv(indio_dev);
384 int i = mma8452_get_odr_index(data);
389 for (j = 0; j < ARRAY_SIZE(mma8452_os_ratio); j++) {
390 if (val == mma8452_os_ratio[j][i])
393 val = mma8452_os_ratio[j][i];
395 len += scnprintf(buf + len, PAGE_SIZE - len, "%d ", val);
402 static IIO_DEV_ATTR_SAMP_FREQ_AVAIL(mma8452_show_samp_freq_avail);
403 static IIO_DEVICE_ATTR(in_accel_scale_available, S_IRUGO,
404 mma8452_show_scale_avail, NULL, 0);
405 static IIO_DEVICE_ATTR(in_accel_filter_high_pass_3db_frequency_available,
406 S_IRUGO, mma8452_show_hp_cutoff_avail, NULL, 0);
407 static IIO_DEVICE_ATTR(in_accel_oversampling_ratio_available, S_IRUGO,
408 mma8452_show_os_ratio_avail, NULL, 0);
410 static int mma8452_get_samp_freq_index(struct mma8452_data *data,
413 return mma8452_get_int_plus_micros_index(mma8452_samp_freq,
414 ARRAY_SIZE(mma8452_samp_freq),
418 static int mma8452_get_scale_index(struct mma8452_data *data, int val, int val2)
420 return mma8452_get_int_plus_micros_index(data->chip_info->mma_scales,
421 ARRAY_SIZE(data->chip_info->mma_scales), val, val2);
424 static int mma8452_get_hp_filter_index(struct mma8452_data *data,
429 i = mma8452_get_odr_index(data);
430 j = mma8452_get_power_mode(data);
434 return mma8452_get_int_plus_micros_index(mma8452_hp_filter_cutoff[j][i],
435 ARRAY_SIZE(mma8452_hp_filter_cutoff[0][0]), val, val2);
438 static int mma8452_read_hp_filter(struct mma8452_data *data, int *hz, int *uHz)
442 ret = i2c_smbus_read_byte_data(data->client, MMA8452_HP_FILTER_CUTOFF);
446 i = mma8452_get_odr_index(data);
447 j = mma8452_get_power_mode(data);
451 ret &= MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
452 *hz = mma8452_hp_filter_cutoff[j][i][ret][0];
453 *uHz = mma8452_hp_filter_cutoff[j][i][ret][1];
458 static int mma8452_read_raw(struct iio_dev *indio_dev,
459 struct iio_chan_spec const *chan,
460 int *val, int *val2, long mask)
462 struct mma8452_data *data = iio_priv(indio_dev);
467 case IIO_CHAN_INFO_RAW:
468 ret = iio_device_claim_direct_mode(indio_dev);
472 mutex_lock(&data->lock);
473 ret = mma8452_read(data, buffer);
474 mutex_unlock(&data->lock);
475 iio_device_release_direct_mode(indio_dev);
479 *val = sign_extend32(be16_to_cpu(
480 buffer[chan->scan_index]) >> chan->scan_type.shift,
481 chan->scan_type.realbits - 1);
484 case IIO_CHAN_INFO_SCALE:
485 i = data->data_cfg & MMA8452_DATA_CFG_FS_MASK;
486 *val = data->chip_info->mma_scales[i][0];
487 *val2 = data->chip_info->mma_scales[i][1];
489 return IIO_VAL_INT_PLUS_MICRO;
490 case IIO_CHAN_INFO_SAMP_FREQ:
491 i = mma8452_get_odr_index(data);
492 *val = mma8452_samp_freq[i][0];
493 *val2 = mma8452_samp_freq[i][1];
495 return IIO_VAL_INT_PLUS_MICRO;
496 case IIO_CHAN_INFO_CALIBBIAS:
497 ret = i2c_smbus_read_byte_data(data->client,
503 *val = sign_extend32(ret, 7);
506 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
507 if (data->data_cfg & MMA8452_DATA_CFG_HPF_MASK) {
508 ret = mma8452_read_hp_filter(data, val, val2);
516 return IIO_VAL_INT_PLUS_MICRO;
517 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
518 ret = mma8452_get_power_mode(data);
522 i = mma8452_get_odr_index(data);
524 *val = mma8452_os_ratio[ret][i];
531 static int mma8452_standby(struct mma8452_data *data)
533 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
534 data->ctrl_reg1 & ~MMA8452_CTRL_ACTIVE);
537 static int mma8452_active(struct mma8452_data *data)
539 return i2c_smbus_write_byte_data(data->client, MMA8452_CTRL_REG1,
543 /* returns >0 if active, 0 if in standby and <0 on error */
544 static int mma8452_is_active(struct mma8452_data *data)
548 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG1);
552 return reg & MMA8452_CTRL_ACTIVE;
555 static int mma8452_change_config(struct mma8452_data *data, u8 reg, u8 val)
560 mutex_lock(&data->lock);
562 is_active = mma8452_is_active(data);
568 /* config can only be changed when in standby */
570 ret = mma8452_standby(data);
575 ret = i2c_smbus_write_byte_data(data->client, reg, val);
580 ret = mma8452_active(data);
587 mutex_unlock(&data->lock);
592 static int mma8452_set_power_mode(struct mma8452_data *data, u8 mode)
596 reg = i2c_smbus_read_byte_data(data->client,
601 reg &= ~MMA8452_CTRL_REG2_MODS_MASK;
602 reg |= mode << MMA8452_CTRL_REG2_MODS_SHIFT;
604 return mma8452_change_config(data, MMA8452_CTRL_REG2, reg);
607 /* returns >0 if in freefall mode, 0 if not or <0 if an error occurred */
608 static int mma8452_freefall_mode_enabled(struct mma8452_data *data)
611 const struct mma_chip_info *chip = data->chip_info;
613 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
617 return !(val & MMA8452_FF_MT_CFG_OAE);
620 static int mma8452_set_freefall_mode(struct mma8452_data *data, bool state)
623 const struct mma_chip_info *chip = data->chip_info;
625 if ((state && mma8452_freefall_mode_enabled(data)) ||
626 (!state && !(mma8452_freefall_mode_enabled(data))))
629 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
634 val |= BIT(idx_x + chip->ev_cfg_chan_shift);
635 val |= BIT(idx_y + chip->ev_cfg_chan_shift);
636 val |= BIT(idx_z + chip->ev_cfg_chan_shift);
637 val &= ~MMA8452_FF_MT_CFG_OAE;
639 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
640 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
641 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
642 val |= MMA8452_FF_MT_CFG_OAE;
645 return mma8452_change_config(data, chip->ev_cfg, val);
648 static int mma8452_set_hp_filter_frequency(struct mma8452_data *data,
653 i = mma8452_get_hp_filter_index(data, val, val2);
657 reg = i2c_smbus_read_byte_data(data->client,
658 MMA8452_HP_FILTER_CUTOFF);
662 reg &= ~MMA8452_HP_FILTER_CUTOFF_SEL_MASK;
665 return mma8452_change_config(data, MMA8452_HP_FILTER_CUTOFF, reg);
668 static int mma8452_write_raw(struct iio_dev *indio_dev,
669 struct iio_chan_spec const *chan,
670 int val, int val2, long mask)
672 struct mma8452_data *data = iio_priv(indio_dev);
675 ret = iio_device_claim_direct_mode(indio_dev);
680 case IIO_CHAN_INFO_SAMP_FREQ:
681 i = mma8452_get_samp_freq_index(data, val, val2);
686 data->ctrl_reg1 &= ~MMA8452_CTRL_DR_MASK;
687 data->ctrl_reg1 |= i << MMA8452_CTRL_DR_SHIFT;
689 ret = mma8452_change_config(data, MMA8452_CTRL_REG1,
692 case IIO_CHAN_INFO_SCALE:
693 i = mma8452_get_scale_index(data, val, val2);
699 data->data_cfg &= ~MMA8452_DATA_CFG_FS_MASK;
702 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
705 case IIO_CHAN_INFO_CALIBBIAS:
706 if (val < -128 || val > 127) {
711 ret = mma8452_change_config(data,
712 MMA8452_OFF_X + chan->scan_index,
716 case IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY:
717 if (val == 0 && val2 == 0) {
718 data->data_cfg &= ~MMA8452_DATA_CFG_HPF_MASK;
720 data->data_cfg |= MMA8452_DATA_CFG_HPF_MASK;
721 ret = mma8452_set_hp_filter_frequency(data, val, val2);
726 ret = mma8452_change_config(data, MMA8452_DATA_CFG,
730 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
731 ret = mma8452_get_odr_index(data);
733 for (i = 0; i < ARRAY_SIZE(mma8452_os_ratio); i++) {
734 if (mma8452_os_ratio[i][ret] == val) {
735 ret = mma8452_set_power_mode(data, i);
745 iio_device_release_direct_mode(indio_dev);
749 static int mma8452_read_thresh(struct iio_dev *indio_dev,
750 const struct iio_chan_spec *chan,
751 enum iio_event_type type,
752 enum iio_event_direction dir,
753 enum iio_event_info info,
756 struct mma8452_data *data = iio_priv(indio_dev);
757 int ret, us, power_mode;
760 case IIO_EV_INFO_VALUE:
761 ret = i2c_smbus_read_byte_data(data->client,
762 data->chip_info->ev_ths);
766 *val = ret & data->chip_info->ev_ths_mask;
770 case IIO_EV_INFO_PERIOD:
771 ret = i2c_smbus_read_byte_data(data->client,
772 data->chip_info->ev_count);
776 power_mode = mma8452_get_power_mode(data);
780 us = ret * mma8452_transient_time_step_us[power_mode][
781 mma8452_get_odr_index(data)];
782 *val = us / USEC_PER_SEC;
783 *val2 = us % USEC_PER_SEC;
785 return IIO_VAL_INT_PLUS_MICRO;
787 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
788 ret = i2c_smbus_read_byte_data(data->client,
789 MMA8452_TRANSIENT_CFG);
793 if (ret & MMA8452_TRANSIENT_CFG_HPF_BYP) {
797 ret = mma8452_read_hp_filter(data, val, val2);
802 return IIO_VAL_INT_PLUS_MICRO;
809 static int mma8452_write_thresh(struct iio_dev *indio_dev,
810 const struct iio_chan_spec *chan,
811 enum iio_event_type type,
812 enum iio_event_direction dir,
813 enum iio_event_info info,
816 struct mma8452_data *data = iio_priv(indio_dev);
820 case IIO_EV_INFO_VALUE:
821 if (val < 0 || val > MMA8452_TRANSIENT_THS_MASK)
824 return mma8452_change_config(data, data->chip_info->ev_ths,
827 case IIO_EV_INFO_PERIOD:
828 ret = mma8452_get_power_mode(data);
832 steps = (val * USEC_PER_SEC + val2) /
833 mma8452_transient_time_step_us[ret][
834 mma8452_get_odr_index(data)];
836 if (steps < 0 || steps > 0xff)
839 return mma8452_change_config(data, data->chip_info->ev_count,
842 case IIO_EV_INFO_HIGH_PASS_FILTER_3DB:
843 reg = i2c_smbus_read_byte_data(data->client,
844 MMA8452_TRANSIENT_CFG);
848 if (val == 0 && val2 == 0) {
849 reg |= MMA8452_TRANSIENT_CFG_HPF_BYP;
851 reg &= ~MMA8452_TRANSIENT_CFG_HPF_BYP;
852 ret = mma8452_set_hp_filter_frequency(data, val, val2);
857 return mma8452_change_config(data, MMA8452_TRANSIENT_CFG, reg);
864 static int mma8452_read_event_config(struct iio_dev *indio_dev,
865 const struct iio_chan_spec *chan,
866 enum iio_event_type type,
867 enum iio_event_direction dir)
869 struct mma8452_data *data = iio_priv(indio_dev);
870 const struct mma_chip_info *chip = data->chip_info;
874 case IIO_EV_DIR_FALLING:
875 return mma8452_freefall_mode_enabled(data);
876 case IIO_EV_DIR_RISING:
877 if (mma8452_freefall_mode_enabled(data))
880 ret = i2c_smbus_read_byte_data(data->client,
881 data->chip_info->ev_cfg);
885 return !!(ret & BIT(chan->scan_index +
886 chip->ev_cfg_chan_shift));
892 static int mma8452_write_event_config(struct iio_dev *indio_dev,
893 const struct iio_chan_spec *chan,
894 enum iio_event_type type,
895 enum iio_event_direction dir,
898 struct mma8452_data *data = iio_priv(indio_dev);
899 const struct mma_chip_info *chip = data->chip_info;
902 ret = mma8452_set_runtime_pm_state(data->client, state);
907 case IIO_EV_DIR_FALLING:
908 return mma8452_set_freefall_mode(data, state);
909 case IIO_EV_DIR_RISING:
910 val = i2c_smbus_read_byte_data(data->client, chip->ev_cfg);
915 if (mma8452_freefall_mode_enabled(data)) {
916 val &= ~BIT(idx_x + chip->ev_cfg_chan_shift);
917 val &= ~BIT(idx_y + chip->ev_cfg_chan_shift);
918 val &= ~BIT(idx_z + chip->ev_cfg_chan_shift);
919 val |= MMA8452_FF_MT_CFG_OAE;
921 val |= BIT(chan->scan_index + chip->ev_cfg_chan_shift);
923 if (mma8452_freefall_mode_enabled(data))
926 val &= ~BIT(chan->scan_index + chip->ev_cfg_chan_shift);
929 val |= chip->ev_cfg_ele;
931 return mma8452_change_config(data, chip->ev_cfg, val);
937 static void mma8452_transient_interrupt(struct iio_dev *indio_dev)
939 struct mma8452_data *data = iio_priv(indio_dev);
940 s64 ts = iio_get_time_ns(indio_dev);
943 src = i2c_smbus_read_byte_data(data->client, data->chip_info->ev_src);
947 if (mma8452_freefall_mode_enabled(data)) {
948 iio_push_event(indio_dev,
949 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0,
950 IIO_MOD_X_AND_Y_AND_Z,
957 if (src & data->chip_info->ev_src_xe)
958 iio_push_event(indio_dev,
959 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_X,
964 if (src & data->chip_info->ev_src_ye)
965 iio_push_event(indio_dev,
966 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Y,
971 if (src & data->chip_info->ev_src_ze)
972 iio_push_event(indio_dev,
973 IIO_MOD_EVENT_CODE(IIO_ACCEL, 0, IIO_MOD_Z,
979 static irqreturn_t mma8452_interrupt(int irq, void *p)
981 struct iio_dev *indio_dev = p;
982 struct mma8452_data *data = iio_priv(indio_dev);
983 const struct mma_chip_info *chip = data->chip_info;
987 src = i2c_smbus_read_byte_data(data->client, MMA8452_INT_SRC);
991 if (src & MMA8452_INT_DRDY) {
992 iio_trigger_poll_chained(indio_dev->trig);
996 if ((src & MMA8452_INT_TRANS &&
997 chip->ev_src == MMA8452_TRANSIENT_SRC) ||
998 (src & MMA8452_INT_FF_MT &&
999 chip->ev_src == MMA8452_FF_MT_SRC)) {
1000 mma8452_transient_interrupt(indio_dev);
1007 static irqreturn_t mma8452_trigger_handler(int irq, void *p)
1009 struct iio_poll_func *pf = p;
1010 struct iio_dev *indio_dev = pf->indio_dev;
1011 struct mma8452_data *data = iio_priv(indio_dev);
1014 ret = mma8452_read(data, data->buffer.channels);
1018 iio_push_to_buffers_with_timestamp(indio_dev, &data->buffer,
1019 iio_get_time_ns(indio_dev));
1022 iio_trigger_notify_done(indio_dev->trig);
1027 static int mma8452_reg_access_dbg(struct iio_dev *indio_dev,
1028 unsigned reg, unsigned writeval,
1032 struct mma8452_data *data = iio_priv(indio_dev);
1034 if (reg > MMA8452_MAX_REG)
1038 return mma8452_change_config(data, reg, writeval);
1040 ret = i2c_smbus_read_byte_data(data->client, reg);
1049 static const struct iio_event_spec mma8452_freefall_event[] = {
1051 .type = IIO_EV_TYPE_MAG,
1052 .dir = IIO_EV_DIR_FALLING,
1053 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1054 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1055 BIT(IIO_EV_INFO_PERIOD) |
1056 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1060 static const struct iio_event_spec mma8652_freefall_event[] = {
1062 .type = IIO_EV_TYPE_MAG,
1063 .dir = IIO_EV_DIR_FALLING,
1064 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1065 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1066 BIT(IIO_EV_INFO_PERIOD)
1070 static const struct iio_event_spec mma8452_transient_event[] = {
1072 .type = IIO_EV_TYPE_MAG,
1073 .dir = IIO_EV_DIR_RISING,
1074 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1075 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1076 BIT(IIO_EV_INFO_PERIOD) |
1077 BIT(IIO_EV_INFO_HIGH_PASS_FILTER_3DB)
1081 static const struct iio_event_spec mma8452_motion_event[] = {
1083 .type = IIO_EV_TYPE_MAG,
1084 .dir = IIO_EV_DIR_RISING,
1085 .mask_separate = BIT(IIO_EV_INFO_ENABLE),
1086 .mask_shared_by_type = BIT(IIO_EV_INFO_VALUE) |
1087 BIT(IIO_EV_INFO_PERIOD)
1092 * Threshold is configured in fixed 8G/127 steps regardless of
1093 * currently selected scale for measurement.
1095 static IIO_CONST_ATTR_NAMED(accel_transient_scale, in_accel_scale, "0.617742");
1097 static struct attribute *mma8452_event_attributes[] = {
1098 &iio_const_attr_accel_transient_scale.dev_attr.attr,
1102 static struct attribute_group mma8452_event_attribute_group = {
1103 .attrs = mma8452_event_attributes,
1106 #define MMA8452_FREEFALL_CHANNEL(modifier) { \
1107 .type = IIO_ACCEL, \
1109 .channel2 = modifier, \
1111 .event_spec = mma8452_freefall_event, \
1112 .num_event_specs = ARRAY_SIZE(mma8452_freefall_event), \
1115 #define MMA8652_FREEFALL_CHANNEL(modifier) { \
1116 .type = IIO_ACCEL, \
1118 .channel2 = modifier, \
1120 .event_spec = mma8652_freefall_event, \
1121 .num_event_specs = ARRAY_SIZE(mma8652_freefall_event), \
1124 #define MMA8452_CHANNEL(axis, idx, bits) { \
1125 .type = IIO_ACCEL, \
1127 .channel2 = IIO_MOD_##axis, \
1128 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1129 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1130 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1131 BIT(IIO_CHAN_INFO_SCALE) | \
1132 BIT(IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY) | \
1133 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1134 .scan_index = idx, \
1137 .realbits = (bits), \
1138 .storagebits = 16, \
1139 .shift = 16 - (bits), \
1140 .endianness = IIO_BE, \
1142 .event_spec = mma8452_transient_event, \
1143 .num_event_specs = ARRAY_SIZE(mma8452_transient_event), \
1146 #define MMA8652_CHANNEL(axis, idx, bits) { \
1147 .type = IIO_ACCEL, \
1149 .channel2 = IIO_MOD_##axis, \
1150 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1151 BIT(IIO_CHAN_INFO_CALIBBIAS), \
1152 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SAMP_FREQ) | \
1153 BIT(IIO_CHAN_INFO_SCALE) | \
1154 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
1155 .scan_index = idx, \
1158 .realbits = (bits), \
1159 .storagebits = 16, \
1160 .shift = 16 - (bits), \
1161 .endianness = IIO_BE, \
1163 .event_spec = mma8452_motion_event, \
1164 .num_event_specs = ARRAY_SIZE(mma8452_motion_event), \
1167 static const struct iio_chan_spec mma8451_channels[] = {
1168 MMA8452_CHANNEL(X, idx_x, 14),
1169 MMA8452_CHANNEL(Y, idx_y, 14),
1170 MMA8452_CHANNEL(Z, idx_z, 14),
1171 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1172 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1175 static const struct iio_chan_spec mma8452_channels[] = {
1176 MMA8452_CHANNEL(X, idx_x, 12),
1177 MMA8452_CHANNEL(Y, idx_y, 12),
1178 MMA8452_CHANNEL(Z, idx_z, 12),
1179 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1180 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1183 static const struct iio_chan_spec mma8453_channels[] = {
1184 MMA8452_CHANNEL(X, idx_x, 10),
1185 MMA8452_CHANNEL(Y, idx_y, 10),
1186 MMA8452_CHANNEL(Z, idx_z, 10),
1187 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1188 MMA8452_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1191 static const struct iio_chan_spec mma8652_channels[] = {
1192 MMA8652_CHANNEL(X, idx_x, 12),
1193 MMA8652_CHANNEL(Y, idx_y, 12),
1194 MMA8652_CHANNEL(Z, idx_z, 12),
1195 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1196 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1199 static const struct iio_chan_spec mma8653_channels[] = {
1200 MMA8652_CHANNEL(X, idx_x, 10),
1201 MMA8652_CHANNEL(Y, idx_y, 10),
1202 MMA8652_CHANNEL(Z, idx_z, 10),
1203 IIO_CHAN_SOFT_TIMESTAMP(idx_ts),
1204 MMA8652_FREEFALL_CHANNEL(IIO_MOD_X_AND_Y_AND_Z),
1216 static const struct mma_chip_info mma_chip_info_table[] = {
1218 .chip_id = MMA8451_DEVICE_ID,
1219 .channels = mma8451_channels,
1220 .num_channels = ARRAY_SIZE(mma8451_channels),
1222 * Hardware has fullscale of -2G, -4G, -8G corresponding to
1223 * raw value -8192 for 14 bit, -2048 for 12 bit or -512 for 10
1225 * The userspace interface uses m/s^2 and we declare micro units
1226 * So scale factor for 12 bit here is given by:
1227 * g * N * 1000000 / 2048 for N = 2, 4, 8 and g=9.80665
1229 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1230 .ev_cfg = MMA8452_TRANSIENT_CFG,
1231 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1232 .ev_cfg_chan_shift = 1,
1233 .ev_src = MMA8452_TRANSIENT_SRC,
1234 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1235 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1236 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1237 .ev_ths = MMA8452_TRANSIENT_THS,
1238 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1239 .ev_count = MMA8452_TRANSIENT_COUNT,
1242 .chip_id = MMA8452_DEVICE_ID,
1243 .channels = mma8452_channels,
1244 .num_channels = ARRAY_SIZE(mma8452_channels),
1245 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1246 .ev_cfg = MMA8452_TRANSIENT_CFG,
1247 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1248 .ev_cfg_chan_shift = 1,
1249 .ev_src = MMA8452_TRANSIENT_SRC,
1250 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1251 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1252 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1253 .ev_ths = MMA8452_TRANSIENT_THS,
1254 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1255 .ev_count = MMA8452_TRANSIENT_COUNT,
1258 .chip_id = MMA8453_DEVICE_ID,
1259 .channels = mma8453_channels,
1260 .num_channels = ARRAY_SIZE(mma8453_channels),
1261 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1262 .ev_cfg = MMA8452_TRANSIENT_CFG,
1263 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1264 .ev_cfg_chan_shift = 1,
1265 .ev_src = MMA8452_TRANSIENT_SRC,
1266 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1267 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1268 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1269 .ev_ths = MMA8452_TRANSIENT_THS,
1270 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1271 .ev_count = MMA8452_TRANSIENT_COUNT,
1274 .chip_id = MMA8652_DEVICE_ID,
1275 .channels = mma8652_channels,
1276 .num_channels = ARRAY_SIZE(mma8652_channels),
1277 .mma_scales = { {0, 9577}, {0, 19154}, {0, 38307} },
1278 .ev_cfg = MMA8452_FF_MT_CFG,
1279 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1280 .ev_cfg_chan_shift = 3,
1281 .ev_src = MMA8452_FF_MT_SRC,
1282 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1283 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1284 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1285 .ev_ths = MMA8452_FF_MT_THS,
1286 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1287 .ev_count = MMA8452_FF_MT_COUNT,
1290 .chip_id = MMA8653_DEVICE_ID,
1291 .channels = mma8653_channels,
1292 .num_channels = ARRAY_SIZE(mma8653_channels),
1293 .mma_scales = { {0, 38307}, {0, 76614}, {0, 153228} },
1294 .ev_cfg = MMA8452_FF_MT_CFG,
1295 .ev_cfg_ele = MMA8452_FF_MT_CFG_ELE,
1296 .ev_cfg_chan_shift = 3,
1297 .ev_src = MMA8452_FF_MT_SRC,
1298 .ev_src_xe = MMA8452_FF_MT_SRC_XHE,
1299 .ev_src_ye = MMA8452_FF_MT_SRC_YHE,
1300 .ev_src_ze = MMA8452_FF_MT_SRC_ZHE,
1301 .ev_ths = MMA8452_FF_MT_THS,
1302 .ev_ths_mask = MMA8452_FF_MT_THS_MASK,
1303 .ev_count = MMA8452_FF_MT_COUNT,
1306 .chip_id = FXLS8471_DEVICE_ID,
1307 .channels = mma8451_channels,
1308 .num_channels = ARRAY_SIZE(mma8451_channels),
1309 .mma_scales = { {0, 2394}, {0, 4788}, {0, 9577} },
1310 .ev_cfg = MMA8452_TRANSIENT_CFG,
1311 .ev_cfg_ele = MMA8452_TRANSIENT_CFG_ELE,
1312 .ev_cfg_chan_shift = 1,
1313 .ev_src = MMA8452_TRANSIENT_SRC,
1314 .ev_src_xe = MMA8452_TRANSIENT_SRC_XTRANSE,
1315 .ev_src_ye = MMA8452_TRANSIENT_SRC_YTRANSE,
1316 .ev_src_ze = MMA8452_TRANSIENT_SRC_ZTRANSE,
1317 .ev_ths = MMA8452_TRANSIENT_THS,
1318 .ev_ths_mask = MMA8452_TRANSIENT_THS_MASK,
1319 .ev_count = MMA8452_TRANSIENT_COUNT,
1323 static struct attribute *mma8452_attributes[] = {
1324 &iio_dev_attr_sampling_frequency_available.dev_attr.attr,
1325 &iio_dev_attr_in_accel_scale_available.dev_attr.attr,
1326 &iio_dev_attr_in_accel_filter_high_pass_3db_frequency_available.dev_attr.attr,
1327 &iio_dev_attr_in_accel_oversampling_ratio_available.dev_attr.attr,
1331 static const struct attribute_group mma8452_group = {
1332 .attrs = mma8452_attributes,
1335 static const struct iio_info mma8452_info = {
1336 .attrs = &mma8452_group,
1337 .read_raw = &mma8452_read_raw,
1338 .write_raw = &mma8452_write_raw,
1339 .event_attrs = &mma8452_event_attribute_group,
1340 .read_event_value = &mma8452_read_thresh,
1341 .write_event_value = &mma8452_write_thresh,
1342 .read_event_config = &mma8452_read_event_config,
1343 .write_event_config = &mma8452_write_event_config,
1344 .debugfs_reg_access = &mma8452_reg_access_dbg,
1345 .driver_module = THIS_MODULE,
1348 static const unsigned long mma8452_scan_masks[] = {0x7, 0};
1350 static int mma8452_data_rdy_trigger_set_state(struct iio_trigger *trig,
1353 struct iio_dev *indio_dev = iio_trigger_get_drvdata(trig);
1354 struct mma8452_data *data = iio_priv(indio_dev);
1357 ret = mma8452_set_runtime_pm_state(data->client, state);
1361 reg = i2c_smbus_read_byte_data(data->client, MMA8452_CTRL_REG4);
1366 reg |= MMA8452_INT_DRDY;
1368 reg &= ~MMA8452_INT_DRDY;
1370 return mma8452_change_config(data, MMA8452_CTRL_REG4, reg);
1373 static const struct iio_trigger_ops mma8452_trigger_ops = {
1374 .set_trigger_state = mma8452_data_rdy_trigger_set_state,
1375 .validate_device = iio_trigger_validate_own_device,
1376 .owner = THIS_MODULE,
1379 static int mma8452_trigger_setup(struct iio_dev *indio_dev)
1381 struct mma8452_data *data = iio_priv(indio_dev);
1382 struct iio_trigger *trig;
1385 trig = devm_iio_trigger_alloc(&data->client->dev, "%s-dev%d",
1391 trig->dev.parent = &data->client->dev;
1392 trig->ops = &mma8452_trigger_ops;
1393 iio_trigger_set_drvdata(trig, indio_dev);
1395 ret = iio_trigger_register(trig);
1399 indio_dev->trig = trig;
1404 static void mma8452_trigger_cleanup(struct iio_dev *indio_dev)
1406 if (indio_dev->trig)
1407 iio_trigger_unregister(indio_dev->trig);
1410 static int mma8452_reset(struct i2c_client *client)
1415 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG2,
1416 MMA8452_CTRL_REG2_RST);
1420 for (i = 0; i < 10; i++) {
1421 usleep_range(100, 200);
1422 ret = i2c_smbus_read_byte_data(client, MMA8452_CTRL_REG2);
1424 continue; /* I2C comm reset */
1427 if (!(ret & MMA8452_CTRL_REG2_RST))
1434 static const struct of_device_id mma8452_dt_ids[] = {
1435 { .compatible = "fsl,mma8451", .data = &mma_chip_info_table[mma8451] },
1436 { .compatible = "fsl,mma8452", .data = &mma_chip_info_table[mma8452] },
1437 { .compatible = "fsl,mma8453", .data = &mma_chip_info_table[mma8453] },
1438 { .compatible = "fsl,mma8652", .data = &mma_chip_info_table[mma8652] },
1439 { .compatible = "fsl,mma8653", .data = &mma_chip_info_table[mma8653] },
1440 { .compatible = "fsl,fxls8471", .data = &mma_chip_info_table[fxls8471] },
1443 MODULE_DEVICE_TABLE(of, mma8452_dt_ids);
1445 static int mma8452_probe(struct i2c_client *client,
1446 const struct i2c_device_id *id)
1448 struct mma8452_data *data;
1449 struct iio_dev *indio_dev;
1451 const struct of_device_id *match;
1453 match = of_match_device(mma8452_dt_ids, &client->dev);
1455 dev_err(&client->dev, "unknown device model\n");
1459 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
1463 data = iio_priv(indio_dev);
1464 data->client = client;
1465 mutex_init(&data->lock);
1466 data->chip_info = match->data;
1468 ret = i2c_smbus_read_byte_data(client, MMA8452_WHO_AM_I);
1473 case MMA8451_DEVICE_ID:
1474 case MMA8452_DEVICE_ID:
1475 case MMA8453_DEVICE_ID:
1476 case MMA8652_DEVICE_ID:
1477 case MMA8653_DEVICE_ID:
1478 case FXLS8471_DEVICE_ID:
1479 if (ret == data->chip_info->chip_id)
1485 dev_info(&client->dev, "registering %s accelerometer; ID 0x%x\n",
1486 match->compatible, data->chip_info->chip_id);
1488 i2c_set_clientdata(client, indio_dev);
1489 indio_dev->info = &mma8452_info;
1490 indio_dev->name = id->name;
1491 indio_dev->dev.parent = &client->dev;
1492 indio_dev->modes = INDIO_DIRECT_MODE;
1493 indio_dev->channels = data->chip_info->channels;
1494 indio_dev->num_channels = data->chip_info->num_channels;
1495 indio_dev->available_scan_masks = mma8452_scan_masks;
1497 ret = mma8452_reset(client);
1501 data->data_cfg = MMA8452_DATA_CFG_FS_2G;
1502 ret = i2c_smbus_write_byte_data(client, MMA8452_DATA_CFG,
1508 * By default set transient threshold to max to avoid events if
1509 * enabling without configuring threshold.
1511 ret = i2c_smbus_write_byte_data(client, MMA8452_TRANSIENT_THS,
1512 MMA8452_TRANSIENT_THS_MASK);
1518 * Although we enable the interrupt sources once and for
1519 * all here the event detection itself is not enabled until
1520 * userspace asks for it by mma8452_write_event_config()
1522 int supported_interrupts = MMA8452_INT_DRDY |
1525 int enabled_interrupts = MMA8452_INT_TRANS |
1529 irq2 = of_irq_get_byname(client->dev.of_node, "INT2");
1531 if (irq2 == client->irq) {
1532 dev_dbg(&client->dev, "using interrupt line INT2\n");
1534 ret = i2c_smbus_write_byte_data(client,
1536 supported_interrupts);
1540 dev_dbg(&client->dev, "using interrupt line INT1\n");
1543 ret = i2c_smbus_write_byte_data(client,
1545 enabled_interrupts);
1549 ret = mma8452_trigger_setup(indio_dev);
1554 data->ctrl_reg1 = MMA8452_CTRL_ACTIVE |
1555 (MMA8452_CTRL_DR_DEFAULT << MMA8452_CTRL_DR_SHIFT);
1556 ret = i2c_smbus_write_byte_data(client, MMA8452_CTRL_REG1,
1559 goto trigger_cleanup;
1561 ret = iio_triggered_buffer_setup(indio_dev, NULL,
1562 mma8452_trigger_handler, NULL);
1564 goto trigger_cleanup;
1567 ret = devm_request_threaded_irq(&client->dev,
1569 NULL, mma8452_interrupt,
1570 IRQF_TRIGGER_LOW | IRQF_ONESHOT,
1571 client->name, indio_dev);
1573 goto buffer_cleanup;
1576 ret = pm_runtime_set_active(&client->dev);
1578 goto buffer_cleanup;
1580 pm_runtime_enable(&client->dev);
1581 pm_runtime_set_autosuspend_delay(&client->dev,
1582 MMA8452_AUTO_SUSPEND_DELAY_MS);
1583 pm_runtime_use_autosuspend(&client->dev);
1585 ret = iio_device_register(indio_dev);
1587 goto buffer_cleanup;
1589 ret = mma8452_set_freefall_mode(data, false);
1591 goto unregister_device;
1596 iio_device_unregister(indio_dev);
1599 iio_triggered_buffer_cleanup(indio_dev);
1602 mma8452_trigger_cleanup(indio_dev);
1607 static int mma8452_remove(struct i2c_client *client)
1609 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1611 iio_device_unregister(indio_dev);
1613 pm_runtime_disable(&client->dev);
1614 pm_runtime_set_suspended(&client->dev);
1615 pm_runtime_put_noidle(&client->dev);
1617 iio_triggered_buffer_cleanup(indio_dev);
1618 mma8452_trigger_cleanup(indio_dev);
1619 mma8452_standby(iio_priv(indio_dev));
1625 static int mma8452_runtime_suspend(struct device *dev)
1627 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1628 struct mma8452_data *data = iio_priv(indio_dev);
1631 mutex_lock(&data->lock);
1632 ret = mma8452_standby(data);
1633 mutex_unlock(&data->lock);
1635 dev_err(&data->client->dev, "powering off device failed\n");
1642 static int mma8452_runtime_resume(struct device *dev)
1644 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1645 struct mma8452_data *data = iio_priv(indio_dev);
1648 ret = mma8452_active(data);
1652 ret = mma8452_get_odr_index(data);
1653 sleep_val = 1000 / mma8452_samp_freq[ret][0];
1655 usleep_range(sleep_val * 1000, 20000);
1657 msleep_interruptible(sleep_val);
1663 #ifdef CONFIG_PM_SLEEP
1664 static int mma8452_suspend(struct device *dev)
1666 return mma8452_standby(iio_priv(i2c_get_clientdata(
1667 to_i2c_client(dev))));
1670 static int mma8452_resume(struct device *dev)
1672 return mma8452_active(iio_priv(i2c_get_clientdata(
1673 to_i2c_client(dev))));
1677 static const struct dev_pm_ops mma8452_pm_ops = {
1678 SET_SYSTEM_SLEEP_PM_OPS(mma8452_suspend, mma8452_resume)
1679 SET_RUNTIME_PM_OPS(mma8452_runtime_suspend,
1680 mma8452_runtime_resume, NULL)
1683 static const struct i2c_device_id mma8452_id[] = {
1684 { "mma8451", mma8451 },
1685 { "mma8452", mma8452 },
1686 { "mma8453", mma8453 },
1687 { "mma8652", mma8652 },
1688 { "mma8653", mma8653 },
1689 { "fxls8471", fxls8471 },
1692 MODULE_DEVICE_TABLE(i2c, mma8452_id);
1694 static struct i2c_driver mma8452_driver = {
1697 .of_match_table = of_match_ptr(mma8452_dt_ids),
1698 .pm = &mma8452_pm_ops,
1700 .probe = mma8452_probe,
1701 .remove = mma8452_remove,
1702 .id_table = mma8452_id,
1704 module_i2c_driver(mma8452_driver);
1706 MODULE_AUTHOR("Peter Meerwald <pmeerw@pmeerw.net>");
1707 MODULE_DESCRIPTION("Freescale / NXP MMA8452 accelerometer driver");
1708 MODULE_LICENSE("GPL");