1 // SPDX-License-Identifier: GPL-2.0-only
3 * 3-axis accelerometer driver supporting many Bosch-Sensortec chips
4 * Copyright (c) 2014, Intel Corporation.
7 #include <linux/module.h>
9 #include <linux/interrupt.h>
10 #include <linux/delay.h>
11 #include <linux/slab.h>
12 #include <linux/acpi.h>
13 #include <linux/of_irq.h>
15 #include <linux/pm_runtime.h>
16 #include <linux/iio/iio.h>
17 #include <linux/iio/sysfs.h>
18 #include <linux/iio/buffer.h>
19 #include <linux/iio/events.h>
20 #include <linux/iio/trigger.h>
21 #include <linux/iio/trigger_consumer.h>
22 #include <linux/iio/triggered_buffer.h>
23 #include <linux/regmap.h>
24 #include <linux/regulator/consumer.h>
26 #include "bmc150-accel.h"
28 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
29 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
31 #define BMC150_ACCEL_REG_CHIP_ID 0x00
33 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
34 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
35 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
36 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
37 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
38 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
40 #define BMC150_ACCEL_REG_PMU_LPW 0x11
41 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
42 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
43 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
44 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
46 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
48 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
49 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
50 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
51 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
53 /* Default BW: 125Hz */
54 #define BMC150_ACCEL_REG_PMU_BW 0x10
55 #define BMC150_ACCEL_DEF_BW 125
57 #define BMC150_ACCEL_REG_RESET 0x14
58 #define BMC150_ACCEL_RESET_VAL 0xB6
60 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
61 #define BMC150_ACCEL_INT_MAP_0_BIT_INT1_SLOPE BIT(2)
63 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
64 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_DATA BIT(0)
65 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_FWM BIT(1)
66 #define BMC150_ACCEL_INT_MAP_1_BIT_INT1_FFULL BIT(2)
67 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_FFULL BIT(5)
68 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_FWM BIT(6)
69 #define BMC150_ACCEL_INT_MAP_1_BIT_INT2_DATA BIT(7)
71 #define BMC150_ACCEL_REG_INT_MAP_2 0x1B
72 #define BMC150_ACCEL_INT_MAP_2_BIT_INT2_SLOPE BIT(2)
74 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
75 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
76 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
77 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
79 #define BMC150_ACCEL_REG_INT_EN_0 0x16
80 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
81 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
82 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
84 #define BMC150_ACCEL_REG_INT_EN_1 0x17
85 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
86 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
87 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
89 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
90 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
91 #define BMC150_ACCEL_INT_OUT_CTRL_INT2_LVL BIT(2)
93 #define BMC150_ACCEL_REG_INT_5 0x27
94 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
96 #define BMC150_ACCEL_REG_INT_6 0x28
97 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
99 /* Slope duration in terms of number of samples */
100 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
101 /* in terms of multiples of g's/LSB, based on range */
102 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
104 #define BMC150_ACCEL_REG_XOUT_L 0x02
106 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
108 /* Sleep Duration values */
109 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
110 #define BMC150_ACCEL_SLEEP_1_MS 0x06
111 #define BMC150_ACCEL_SLEEP_2_MS 0x07
112 #define BMC150_ACCEL_SLEEP_4_MS 0x08
113 #define BMC150_ACCEL_SLEEP_6_MS 0x09
114 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
115 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
116 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
117 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
118 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
119 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
121 #define BMC150_ACCEL_REG_TEMP 0x08
122 #define BMC150_ACCEL_TEMP_CENTER_VAL 23
124 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
125 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
127 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
128 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
129 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
130 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
131 #define BMC150_ACCEL_FIFO_LENGTH 32
133 enum bmc150_accel_axis {
140 enum bmc150_power_modes {
141 BMC150_ACCEL_SLEEP_MODE_NORMAL,
142 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
143 BMC150_ACCEL_SLEEP_MODE_LPM,
144 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
147 struct bmc150_scale_info {
152 struct bmc150_accel_chip_info {
155 const struct iio_chan_spec *channels;
157 const struct bmc150_scale_info scale_table[4];
160 static const struct {
164 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
173 static const struct {
176 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
185 static const struct {
188 } bmc150_accel_sleep_value_table[] = { {0, 0},
189 {500, BMC150_ACCEL_SLEEP_500_MICRO},
190 {1000, BMC150_ACCEL_SLEEP_1_MS},
191 {2000, BMC150_ACCEL_SLEEP_2_MS},
192 {4000, BMC150_ACCEL_SLEEP_4_MS},
193 {6000, BMC150_ACCEL_SLEEP_6_MS},
194 {10000, BMC150_ACCEL_SLEEP_10_MS},
195 {25000, BMC150_ACCEL_SLEEP_25_MS},
196 {50000, BMC150_ACCEL_SLEEP_50_MS},
197 {100000, BMC150_ACCEL_SLEEP_100_MS},
198 {500000, BMC150_ACCEL_SLEEP_500_MS},
199 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
201 const struct regmap_config bmc150_regmap_conf = {
204 .max_register = 0x3f,
206 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
208 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
209 enum bmc150_power_modes mode,
212 struct device *dev = regmap_get_device(data->regmap);
219 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
221 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
224 bmc150_accel_sleep_value_table[i].reg_value;
233 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
234 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
236 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
238 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
240 dev_err(dev, "Error writing reg_pmu_lpw\n");
247 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
253 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
254 if (bmc150_accel_samp_freq_table[i].val == val &&
255 bmc150_accel_samp_freq_table[i].val2 == val2) {
256 ret = regmap_write(data->regmap,
257 BMC150_ACCEL_REG_PMU_BW,
258 bmc150_accel_samp_freq_table[i].bw_bits);
263 bmc150_accel_samp_freq_table[i].bw_bits;
271 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
273 struct device *dev = regmap_get_device(data->regmap);
276 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
279 dev_err(dev, "Error writing reg_int_6\n");
283 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
284 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
286 dev_err(dev, "Error updating reg_int_5\n");
290 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur);
295 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
299 return bmc150_accel_update_slope(t->data);
304 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
309 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
310 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
311 *val = bmc150_accel_samp_freq_table[i].val;
312 *val2 = bmc150_accel_samp_freq_table[i].val2;
313 return IIO_VAL_INT_PLUS_MICRO;
321 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
325 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
326 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
327 return bmc150_accel_sample_upd_time[i].msec;
330 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
333 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
335 struct device *dev = regmap_get_device(data->regmap);
339 ret = pm_runtime_resume_and_get(dev);
341 pm_runtime_mark_last_busy(dev);
342 ret = pm_runtime_put_autosuspend(dev);
347 "Failed: %s for %d\n", __func__, on);
354 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
362 * Support for getting accelerometer information from BOSC0200 ACPI nodes.
364 * There are 2 variants of the BOSC0200 ACPI node. Some 2-in-1s with 360 degree
365 * hinges declare 2 I2C ACPI-resources for 2 accelerometers, 1 in the display
366 * and 1 in the base of the 2-in-1. On these 2-in-1s the ROMS ACPI object
367 * contains the mount-matrix for the sensor in the display and ROMK contains
368 * the mount-matrix for the sensor in the base. On devices using a single
369 * sensor there is a ROTM ACPI object which contains the mount-matrix.
371 * Here is an incomplete list of devices known to use 1 of these setups:
373 * Yoga devices with 2 accelerometers using ROMS + ROMK for the mount-matrices:
374 * Lenovo Thinkpad Yoga 11e 3th gen
375 * Lenovo Thinkpad Yoga 11e 4th gen
377 * Tablets using a single accelerometer using ROTM for the mount-matrix:
378 * Chuwi Hi8 Pro (CWI513)
379 * Chuwi Vi8 Plus (CWI519)
382 * Jumper EZpad mini 3
384 * Predia Basic Tablet
386 static bool bmc150_apply_bosc0200_acpi_orientation(struct device *dev,
387 struct iio_mount_matrix *orientation)
389 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
390 struct iio_dev *indio_dev = dev_get_drvdata(dev);
391 struct acpi_device *adev = ACPI_COMPANION(dev);
392 char *name, *alt_name, *label, *str;
393 union acpi_object *obj, *elements;
397 if (strcmp(dev_name(dev), "i2c-BOSC0200:base") == 0) {
399 label = "accel-base";
402 label = "accel-display";
405 if (acpi_has_method(adev->handle, "ROTM")) {
407 } else if (acpi_has_method(adev->handle, alt_name)) {
409 indio_dev->label = label;
414 status = acpi_evaluate_object(adev->handle, name, NULL, &buffer);
415 if (ACPI_FAILURE(status)) {
416 dev_warn(dev, "Failed to get ACPI mount matrix: %d\n", status);
420 obj = buffer.pointer;
421 if (obj->type != ACPI_TYPE_PACKAGE || obj->package.count != 3)
424 elements = obj->package.elements;
425 for (i = 0; i < 3; i++) {
426 if (elements[i].type != ACPI_TYPE_STRING)
429 str = elements[i].string.pointer;
430 if (sscanf(str, "%d %d %d", &val[0], &val[1], &val[2]) != 3)
433 for (j = 0; j < 3; j++) {
435 case -1: str = "-1"; break;
436 case 0: str = "0"; break;
437 case 1: str = "1"; break;
438 default: goto unknown_format;
440 orientation->rotation[i * 3 + j] = str;
444 kfree(buffer.pointer);
448 dev_warn(dev, "Unknown ACPI mount matrix format, ignoring\n");
449 kfree(buffer.pointer);
453 static bool bmc150_apply_dual250e_acpi_orientation(struct device *dev,
454 struct iio_mount_matrix *orientation)
456 struct iio_dev *indio_dev = dev_get_drvdata(dev);
458 if (strcmp(dev_name(dev), "i2c-DUAL250E:base") == 0)
459 indio_dev->label = "accel-base";
461 indio_dev->label = "accel-display";
463 return false; /* DUAL250E fwnodes have no mount matrix info */
466 static bool bmc150_apply_acpi_orientation(struct device *dev,
467 struct iio_mount_matrix *orientation)
469 struct acpi_device *adev = ACPI_COMPANION(dev);
471 if (adev && acpi_dev_hid_uid_match(adev, "BOSC0200", NULL))
472 return bmc150_apply_bosc0200_acpi_orientation(dev, orientation);
474 if (adev && acpi_dev_hid_uid_match(adev, "DUAL250E", NULL))
475 return bmc150_apply_dual250e_acpi_orientation(dev, orientation);
480 static bool bmc150_apply_acpi_orientation(struct device *dev,
481 struct iio_mount_matrix *orientation)
487 struct bmc150_accel_interrupt_info {
494 static const struct bmc150_accel_interrupt_info
495 bmc150_accel_interrupts_int1[BMC150_ACCEL_INTERRUPTS] = {
496 { /* data ready interrupt */
497 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
498 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT1_DATA,
499 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
500 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
502 { /* motion interrupt */
503 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
504 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_INT1_SLOPE,
505 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
506 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
507 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
508 BMC150_ACCEL_INT_EN_BIT_SLP_Z
510 { /* fifo watermark interrupt */
511 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
512 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT1_FWM,
513 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
514 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
518 static const struct bmc150_accel_interrupt_info
519 bmc150_accel_interrupts_int2[BMC150_ACCEL_INTERRUPTS] = {
520 { /* data ready interrupt */
521 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
522 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT2_DATA,
523 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
524 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
526 { /* motion interrupt */
527 .map_reg = BMC150_ACCEL_REG_INT_MAP_2,
528 .map_bitmask = BMC150_ACCEL_INT_MAP_2_BIT_INT2_SLOPE,
529 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
530 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
531 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
532 BMC150_ACCEL_INT_EN_BIT_SLP_Z
534 { /* fifo watermark interrupt */
535 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
536 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_INT2_FWM,
537 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
538 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
542 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
543 struct bmc150_accel_data *data, int irq)
545 const struct bmc150_accel_interrupt_info *irq_info = NULL;
546 struct device *dev = regmap_get_device(data->regmap);
550 * For now we map all interrupts to the same output pin.
551 * However, some boards may have just INT2 (and not INT1) connected,
552 * so we try to detect which IRQ it is based on the interrupt-names.
553 * Without interrupt-names, we assume the irq belongs to INT1.
555 irq_info = bmc150_accel_interrupts_int1;
556 if (data->type == BOSCH_BMC156 ||
557 irq == of_irq_get_byname(dev->of_node, "INT2"))
558 irq_info = bmc150_accel_interrupts_int2;
560 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
561 data->interrupts[i].info = &irq_info[i];
564 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
567 struct device *dev = regmap_get_device(data->regmap);
568 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
569 const struct bmc150_accel_interrupt_info *info = intr->info;
573 if (atomic_inc_return(&intr->users) > 1)
576 if (atomic_dec_return(&intr->users) > 0)
581 * We will expect the enable and disable to do operation in reverse
582 * order. This will happen here anyway, as our resume operation uses
583 * sync mode runtime pm calls. The suspend operation will be delayed
584 * by autosuspend delay.
585 * So the disable operation will still happen in reverse order of
586 * enable operation. When runtime pm is disabled the mode is always on,
587 * so sequence doesn't matter.
589 ret = bmc150_accel_set_power_state(data, state);
593 /* map the interrupt to the appropriate pins */
594 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
595 (state ? info->map_bitmask : 0));
597 dev_err(dev, "Error updating reg_int_map\n");
598 goto out_fix_power_state;
601 /* enable/disable the interrupt */
602 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
603 (state ? info->en_bitmask : 0));
605 dev_err(dev, "Error updating reg_int_en\n");
606 goto out_fix_power_state;
612 bmc150_accel_set_power_state(data, false);
616 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
618 struct device *dev = regmap_get_device(data->regmap);
621 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
622 if (data->chip_info->scale_table[i].scale == val) {
623 ret = regmap_write(data->regmap,
624 BMC150_ACCEL_REG_PMU_RANGE,
625 data->chip_info->scale_table[i].reg_range);
627 dev_err(dev, "Error writing pmu_range\n");
631 data->range = data->chip_info->scale_table[i].reg_range;
639 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
641 struct device *dev = regmap_get_device(data->regmap);
645 mutex_lock(&data->mutex);
647 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
649 dev_err(dev, "Error reading reg_temp\n");
650 mutex_unlock(&data->mutex);
653 *val = sign_extend32(value, 7);
655 mutex_unlock(&data->mutex);
660 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
661 struct iio_chan_spec const *chan,
664 struct device *dev = regmap_get_device(data->regmap);
666 int axis = chan->scan_index;
669 mutex_lock(&data->mutex);
670 ret = bmc150_accel_set_power_state(data, true);
672 mutex_unlock(&data->mutex);
676 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
677 &raw_val, sizeof(raw_val));
679 dev_err(dev, "Error reading axis %d\n", axis);
680 bmc150_accel_set_power_state(data, false);
681 mutex_unlock(&data->mutex);
684 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
685 chan->scan_type.realbits - 1);
686 ret = bmc150_accel_set_power_state(data, false);
687 mutex_unlock(&data->mutex);
694 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
695 struct iio_chan_spec const *chan,
696 int *val, int *val2, long mask)
698 struct bmc150_accel_data *data = iio_priv(indio_dev);
702 case IIO_CHAN_INFO_RAW:
703 switch (chan->type) {
705 return bmc150_accel_get_temp(data, val);
707 if (iio_buffer_enabled(indio_dev))
710 return bmc150_accel_get_axis(data, chan, val);
714 case IIO_CHAN_INFO_OFFSET:
715 if (chan->type == IIO_TEMP) {
716 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
721 case IIO_CHAN_INFO_SCALE:
723 switch (chan->type) {
726 return IIO_VAL_INT_PLUS_MICRO;
730 const struct bmc150_scale_info *si;
731 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
733 for (i = 0; i < st_size; ++i) {
734 si = &data->chip_info->scale_table[i];
735 if (si->reg_range == data->range) {
737 return IIO_VAL_INT_PLUS_MICRO;
745 case IIO_CHAN_INFO_SAMP_FREQ:
746 mutex_lock(&data->mutex);
747 ret = bmc150_accel_get_bw(data, val, val2);
748 mutex_unlock(&data->mutex);
755 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
756 struct iio_chan_spec const *chan,
757 int val, int val2, long mask)
759 struct bmc150_accel_data *data = iio_priv(indio_dev);
763 case IIO_CHAN_INFO_SAMP_FREQ:
764 mutex_lock(&data->mutex);
765 ret = bmc150_accel_set_bw(data, val, val2);
766 mutex_unlock(&data->mutex);
768 case IIO_CHAN_INFO_SCALE:
772 mutex_lock(&data->mutex);
773 ret = bmc150_accel_set_scale(data, val2);
774 mutex_unlock(&data->mutex);
783 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
784 const struct iio_chan_spec *chan,
785 enum iio_event_type type,
786 enum iio_event_direction dir,
787 enum iio_event_info info,
790 struct bmc150_accel_data *data = iio_priv(indio_dev);
794 case IIO_EV_INFO_VALUE:
795 *val = data->slope_thres;
797 case IIO_EV_INFO_PERIOD:
798 *val = data->slope_dur;
807 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
808 const struct iio_chan_spec *chan,
809 enum iio_event_type type,
810 enum iio_event_direction dir,
811 enum iio_event_info info,
814 struct bmc150_accel_data *data = iio_priv(indio_dev);
816 if (data->ev_enable_state)
820 case IIO_EV_INFO_VALUE:
821 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
823 case IIO_EV_INFO_PERIOD:
824 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
833 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
834 const struct iio_chan_spec *chan,
835 enum iio_event_type type,
836 enum iio_event_direction dir)
838 struct bmc150_accel_data *data = iio_priv(indio_dev);
840 return data->ev_enable_state;
843 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
844 const struct iio_chan_spec *chan,
845 enum iio_event_type type,
846 enum iio_event_direction dir,
849 struct bmc150_accel_data *data = iio_priv(indio_dev);
852 if (state == data->ev_enable_state)
855 mutex_lock(&data->mutex);
857 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
860 mutex_unlock(&data->mutex);
864 data->ev_enable_state = state;
865 mutex_unlock(&data->mutex);
870 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
871 struct iio_trigger *trig)
873 struct bmc150_accel_data *data = iio_priv(indio_dev);
876 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
877 if (data->triggers[i].indio_trig == trig)
884 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
885 struct device_attribute *attr,
888 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
889 struct bmc150_accel_data *data = iio_priv(indio_dev);
892 mutex_lock(&data->mutex);
893 wm = data->watermark;
894 mutex_unlock(&data->mutex);
896 return sprintf(buf, "%d\n", wm);
899 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
900 struct device_attribute *attr,
903 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
904 struct bmc150_accel_data *data = iio_priv(indio_dev);
907 mutex_lock(&data->mutex);
908 state = data->fifo_mode;
909 mutex_unlock(&data->mutex);
911 return sprintf(buf, "%d\n", state);
914 static const struct iio_mount_matrix *
915 bmc150_accel_get_mount_matrix(const struct iio_dev *indio_dev,
916 const struct iio_chan_spec *chan)
918 struct bmc150_accel_data *data = iio_priv(indio_dev);
920 return &data->orientation;
923 static const struct iio_chan_spec_ext_info bmc150_accel_ext_info[] = {
924 IIO_MOUNT_MATRIX(IIO_SHARED_BY_DIR, bmc150_accel_get_mount_matrix),
928 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
929 static IIO_CONST_ATTR(hwfifo_watermark_max,
930 __stringify(BMC150_ACCEL_FIFO_LENGTH));
931 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
932 bmc150_accel_get_fifo_state, NULL, 0);
933 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
934 bmc150_accel_get_fifo_watermark, NULL, 0);
936 static const struct attribute *bmc150_accel_fifo_attributes[] = {
937 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
938 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
939 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
940 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
944 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
946 struct bmc150_accel_data *data = iio_priv(indio_dev);
948 if (val > BMC150_ACCEL_FIFO_LENGTH)
949 val = BMC150_ACCEL_FIFO_LENGTH;
951 mutex_lock(&data->mutex);
952 data->watermark = val;
953 mutex_unlock(&data->mutex);
959 * We must read at least one full frame in one burst, otherwise the rest of the
960 * frame data is discarded.
962 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
963 char *buffer, int samples)
965 struct device *dev = regmap_get_device(data->regmap);
966 int sample_length = 3 * 2;
968 int total_length = samples * sample_length;
970 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
971 buffer, total_length);
974 "Error transferring data from fifo: %d\n", ret);
979 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
980 unsigned samples, bool irq)
982 struct bmc150_accel_data *data = iio_priv(indio_dev);
983 struct device *dev = regmap_get_device(data->regmap);
986 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
988 uint64_t sample_period;
991 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
993 dev_err(dev, "Error reading reg_fifo_status\n");
1003 * If we getting called from IRQ handler we know the stored timestamp is
1004 * fairly accurate for the last stored sample. Otherwise, if we are
1005 * called as a result of a read operation from userspace and hence
1006 * before the watermark interrupt was triggered, take a timestamp
1007 * now. We can fall anywhere in between two samples so the error in this
1008 * case is at most one sample period.
1011 data->old_timestamp = data->timestamp;
1012 data->timestamp = iio_get_time_ns(indio_dev);
1016 * Approximate timestamps for each of the sample based on the sampling
1017 * frequency, timestamp for last sample and number of samples.
1019 * Note that we can't use the current bandwidth settings to compute the
1020 * sample period because the sample rate varies with the device
1021 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
1022 * small variation adds when we store a large number of samples and
1023 * creates significant jitter between the last and first samples in
1024 * different batches (e.g. 32ms vs 21ms).
1026 * To avoid this issue we compute the actual sample period ourselves
1027 * based on the timestamp delta between the last two flush operations.
1029 sample_period = (data->timestamp - data->old_timestamp);
1030 do_div(sample_period, count);
1031 tstamp = data->timestamp - (count - 1) * sample_period;
1033 if (samples && count > samples)
1036 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
1041 * Ideally we want the IIO core to handle the demux when running in fifo
1042 * mode but not when running in triggered buffer mode. Unfortunately
1043 * this does not seem to be possible, so stick with driver demux for
1046 for (i = 0; i < count; i++) {
1050 for_each_set_bit(bit, indio_dev->active_scan_mask,
1051 indio_dev->masklength)
1052 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
1053 sizeof(data->scan.channels[0]));
1055 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
1058 tstamp += sample_period;
1064 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
1066 struct bmc150_accel_data *data = iio_priv(indio_dev);
1069 mutex_lock(&data->mutex);
1070 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
1071 mutex_unlock(&data->mutex);
1076 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
1077 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
1079 static struct attribute *bmc150_accel_attributes[] = {
1080 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
1084 static const struct attribute_group bmc150_accel_attrs_group = {
1085 .attrs = bmc150_accel_attributes,
1088 static const struct iio_event_spec bmc150_accel_event = {
1089 .type = IIO_EV_TYPE_ROC,
1090 .dir = IIO_EV_DIR_EITHER,
1091 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
1092 BIT(IIO_EV_INFO_ENABLE) |
1093 BIT(IIO_EV_INFO_PERIOD)
1096 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
1097 .type = IIO_ACCEL, \
1099 .channel2 = IIO_MOD_##_axis, \
1100 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
1101 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
1102 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1103 .scan_index = AXIS_##_axis, \
1106 .realbits = (bits), \
1107 .storagebits = 16, \
1108 .shift = 16 - (bits), \
1109 .endianness = IIO_LE, \
1111 .ext_info = bmc150_accel_ext_info, \
1112 .event_spec = &bmc150_accel_event, \
1113 .num_event_specs = 1 \
1116 #define BMC150_ACCEL_CHANNELS(bits) { \
1119 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1120 BIT(IIO_CHAN_INFO_SCALE) | \
1121 BIT(IIO_CHAN_INFO_OFFSET), \
1124 BMC150_ACCEL_CHANNEL(X, bits), \
1125 BMC150_ACCEL_CHANNEL(Y, bits), \
1126 BMC150_ACCEL_CHANNEL(Z, bits), \
1127 IIO_CHAN_SOFT_TIMESTAMP(3), \
1130 static const struct iio_chan_spec bma222e_accel_channels[] =
1131 BMC150_ACCEL_CHANNELS(8);
1132 static const struct iio_chan_spec bma250e_accel_channels[] =
1133 BMC150_ACCEL_CHANNELS(10);
1134 static const struct iio_chan_spec bmc150_accel_channels[] =
1135 BMC150_ACCEL_CHANNELS(12);
1136 static const struct iio_chan_spec bma280_accel_channels[] =
1137 BMC150_ACCEL_CHANNELS(14);
1140 * The range for the Bosch sensors is typically +-2g/4g/8g/16g, distributed
1141 * over the amount of bits (see above). The scale table can be calculated using
1142 * (range / 2^bits) * g = (range / 2^bits) * 9.80665 m/s^2
1143 * e.g. for +-2g and 12 bits: (4 / 2^12) * 9.80665 m/s^2 = 0.0095768... m/s^2
1144 * Multiply 10^6 and round to get the values listed below.
1146 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1150 .channels = bma222e_accel_channels,
1151 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1152 .scale_table = { {153229, BMC150_ACCEL_DEF_RANGE_2G},
1153 {306458, BMC150_ACCEL_DEF_RANGE_4G},
1154 {612916, BMC150_ACCEL_DEF_RANGE_8G},
1155 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1160 .channels = bma222e_accel_channels,
1161 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1162 .scale_table = { {153229, BMC150_ACCEL_DEF_RANGE_2G},
1163 {306458, BMC150_ACCEL_DEF_RANGE_4G},
1164 {612916, BMC150_ACCEL_DEF_RANGE_8G},
1165 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1170 .channels = bma250e_accel_channels,
1171 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1172 .scale_table = { {38307, BMC150_ACCEL_DEF_RANGE_2G},
1173 {76614, BMC150_ACCEL_DEF_RANGE_4G},
1174 {153229, BMC150_ACCEL_DEF_RANGE_8G},
1175 {306458, BMC150_ACCEL_DEF_RANGE_16G} },
1178 .name = "BMA253/BMA254/BMA255/BMC150/BMC156/BMI055",
1180 .channels = bmc150_accel_channels,
1181 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1182 .scale_table = { {9577, BMC150_ACCEL_DEF_RANGE_2G},
1183 {19154, BMC150_ACCEL_DEF_RANGE_4G},
1184 {38307, BMC150_ACCEL_DEF_RANGE_8G},
1185 {76614, BMC150_ACCEL_DEF_RANGE_16G} },
1190 .channels = bma280_accel_channels,
1191 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1192 .scale_table = { {2394, BMC150_ACCEL_DEF_RANGE_2G},
1193 {4788, BMC150_ACCEL_DEF_RANGE_4G},
1194 {9577, BMC150_ACCEL_DEF_RANGE_8G},
1195 {19154, BMC150_ACCEL_DEF_RANGE_16G} },
1199 static const struct iio_info bmc150_accel_info = {
1200 .attrs = &bmc150_accel_attrs_group,
1201 .read_raw = bmc150_accel_read_raw,
1202 .write_raw = bmc150_accel_write_raw,
1203 .read_event_value = bmc150_accel_read_event,
1204 .write_event_value = bmc150_accel_write_event,
1205 .write_event_config = bmc150_accel_write_event_config,
1206 .read_event_config = bmc150_accel_read_event_config,
1209 static const struct iio_info bmc150_accel_info_fifo = {
1210 .attrs = &bmc150_accel_attrs_group,
1211 .read_raw = bmc150_accel_read_raw,
1212 .write_raw = bmc150_accel_write_raw,
1213 .read_event_value = bmc150_accel_read_event,
1214 .write_event_value = bmc150_accel_write_event,
1215 .write_event_config = bmc150_accel_write_event_config,
1216 .read_event_config = bmc150_accel_read_event_config,
1217 .validate_trigger = bmc150_accel_validate_trigger,
1218 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1219 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1222 static const unsigned long bmc150_accel_scan_masks[] = {
1223 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1226 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1228 struct iio_poll_func *pf = p;
1229 struct iio_dev *indio_dev = pf->indio_dev;
1230 struct bmc150_accel_data *data = iio_priv(indio_dev);
1233 mutex_lock(&data->mutex);
1234 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1235 data->buffer, AXIS_MAX * 2);
1236 mutex_unlock(&data->mutex);
1240 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1243 iio_trigger_notify_done(indio_dev->trig);
1248 static void bmc150_accel_trig_reen(struct iio_trigger *trig)
1250 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1251 struct bmc150_accel_data *data = t->data;
1252 struct device *dev = regmap_get_device(data->regmap);
1255 /* new data interrupts don't need ack */
1256 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1259 mutex_lock(&data->mutex);
1260 /* clear any latched interrupt */
1261 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1262 BMC150_ACCEL_INT_MODE_LATCH_INT |
1263 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1264 mutex_unlock(&data->mutex);
1266 dev_err(dev, "Error writing reg_int_rst_latch\n");
1269 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1272 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1273 struct bmc150_accel_data *data = t->data;
1276 mutex_lock(&data->mutex);
1278 if (t->enabled == state) {
1279 mutex_unlock(&data->mutex);
1284 ret = t->setup(t, state);
1286 mutex_unlock(&data->mutex);
1291 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1293 mutex_unlock(&data->mutex);
1299 mutex_unlock(&data->mutex);
1304 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1305 .set_trigger_state = bmc150_accel_trigger_set_state,
1306 .reenable = bmc150_accel_trig_reen,
1309 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1311 struct bmc150_accel_data *data = iio_priv(indio_dev);
1312 struct device *dev = regmap_get_device(data->regmap);
1317 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1319 dev_err(dev, "Error reading reg_int_status_2\n");
1323 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1324 dir = IIO_EV_DIR_FALLING;
1326 dir = IIO_EV_DIR_RISING;
1328 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1329 iio_push_event(indio_dev,
1330 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1337 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1338 iio_push_event(indio_dev,
1339 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1346 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1347 iio_push_event(indio_dev,
1348 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1358 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1360 struct iio_dev *indio_dev = private;
1361 struct bmc150_accel_data *data = iio_priv(indio_dev);
1362 struct device *dev = regmap_get_device(data->regmap);
1366 mutex_lock(&data->mutex);
1368 if (data->fifo_mode) {
1369 ret = __bmc150_accel_fifo_flush(indio_dev,
1370 BMC150_ACCEL_FIFO_LENGTH, true);
1375 if (data->ev_enable_state) {
1376 ret = bmc150_accel_handle_roc_event(indio_dev);
1382 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1383 BMC150_ACCEL_INT_MODE_LATCH_INT |
1384 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1386 dev_err(dev, "Error writing reg_int_rst_latch\n");
1393 mutex_unlock(&data->mutex);
1398 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1400 struct iio_dev *indio_dev = private;
1401 struct bmc150_accel_data *data = iio_priv(indio_dev);
1405 data->old_timestamp = data->timestamp;
1406 data->timestamp = iio_get_time_ns(indio_dev);
1408 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1409 if (data->triggers[i].enabled) {
1410 iio_trigger_poll(data->triggers[i].indio_trig);
1416 if (data->ev_enable_state || data->fifo_mode)
1417 return IRQ_WAKE_THREAD;
1425 static const struct {
1428 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1429 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1436 .name = "%s-any-motion-dev%d",
1437 .setup = bmc150_accel_any_motion_setup,
1441 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1446 for (i = from; i >= 0; i--) {
1447 if (data->triggers[i].indio_trig) {
1448 iio_trigger_unregister(data->triggers[i].indio_trig);
1449 data->triggers[i].indio_trig = NULL;
1454 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1455 struct bmc150_accel_data *data)
1457 struct device *dev = regmap_get_device(data->regmap);
1460 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1461 struct bmc150_accel_trigger *t = &data->triggers[i];
1463 t->indio_trig = devm_iio_trigger_alloc(dev,
1464 bmc150_accel_triggers[i].name,
1466 iio_device_id(indio_dev));
1467 if (!t->indio_trig) {
1472 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1473 t->intr = bmc150_accel_triggers[i].intr;
1475 t->setup = bmc150_accel_triggers[i].setup;
1476 iio_trigger_set_drvdata(t->indio_trig, t);
1478 ret = iio_trigger_register(t->indio_trig);
1484 bmc150_accel_unregister_triggers(data, i - 1);
1489 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1490 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1491 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1493 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1495 struct device *dev = regmap_get_device(data->regmap);
1496 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1499 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1501 dev_err(dev, "Error writing reg_fifo_config1\n");
1505 if (!data->fifo_mode)
1508 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1511 dev_err(dev, "Error writing reg_fifo_config0\n");
1516 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1518 struct bmc150_accel_data *data = iio_priv(indio_dev);
1520 return bmc150_accel_set_power_state(data, true);
1523 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1525 struct bmc150_accel_data *data = iio_priv(indio_dev);
1528 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1531 mutex_lock(&data->mutex);
1533 if (!data->watermark)
1536 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1541 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1543 ret = bmc150_accel_fifo_set_mode(data);
1545 data->fifo_mode = 0;
1546 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1551 mutex_unlock(&data->mutex);
1556 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1558 struct bmc150_accel_data *data = iio_priv(indio_dev);
1560 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1563 mutex_lock(&data->mutex);
1565 if (!data->fifo_mode)
1568 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1569 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1570 data->fifo_mode = 0;
1571 bmc150_accel_fifo_set_mode(data);
1574 mutex_unlock(&data->mutex);
1579 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1581 struct bmc150_accel_data *data = iio_priv(indio_dev);
1583 return bmc150_accel_set_power_state(data, false);
1586 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1587 .preenable = bmc150_accel_buffer_preenable,
1588 .postenable = bmc150_accel_buffer_postenable,
1589 .predisable = bmc150_accel_buffer_predisable,
1590 .postdisable = bmc150_accel_buffer_postdisable,
1593 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1595 struct device *dev = regmap_get_device(data->regmap);
1600 * Reset chip to get it in a known good state. A delay of 1.8ms after
1601 * reset is required according to the data sheets of supported chips.
1603 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1604 BMC150_ACCEL_RESET_VAL);
1605 usleep_range(1800, 2500);
1607 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1609 dev_err(dev, "Error: Reading chip id\n");
1613 dev_dbg(dev, "Chip Id %x\n", val);
1614 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1615 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1616 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1621 if (!data->chip_info) {
1622 dev_err(dev, "Invalid chip %x\n", val);
1626 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1631 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1635 /* Set Default Range */
1636 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1637 BMC150_ACCEL_DEF_RANGE_4G);
1639 dev_err(dev, "Error writing reg_pmu_range\n");
1643 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1645 /* Set default slope duration and thresholds */
1646 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1647 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1648 ret = bmc150_accel_update_slope(data);
1652 /* Set default as latched interrupts */
1653 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1654 BMC150_ACCEL_INT_MODE_LATCH_INT |
1655 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1657 dev_err(dev, "Error writing reg_int_rst_latch\n");
1664 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1665 enum bmc150_type type, const char *name,
1666 bool block_supported)
1668 const struct attribute **fifo_attrs;
1669 struct bmc150_accel_data *data;
1670 struct iio_dev *indio_dev;
1673 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1677 data = iio_priv(indio_dev);
1678 dev_set_drvdata(dev, indio_dev);
1680 data->regmap = regmap;
1683 if (!bmc150_apply_acpi_orientation(dev, &data->orientation)) {
1684 ret = iio_read_mount_matrix(dev, &data->orientation);
1690 * VDD is the analog and digital domain voltage supply
1691 * VDDIO is the digital I/O voltage supply
1693 data->regulators[0].supply = "vdd";
1694 data->regulators[1].supply = "vddio";
1695 ret = devm_regulator_bulk_get(dev,
1696 ARRAY_SIZE(data->regulators),
1699 return dev_err_probe(dev, ret, "failed to get regulators\n");
1701 ret = regulator_bulk_enable(ARRAY_SIZE(data->regulators),
1704 dev_err(dev, "failed to enable regulators: %d\n", ret);
1708 * 2ms or 3ms power-on time according to datasheets, let's better
1709 * be safe than sorry and set this delay to 5ms.
1713 ret = bmc150_accel_chip_init(data);
1715 goto err_disable_regulators;
1717 mutex_init(&data->mutex);
1719 indio_dev->channels = data->chip_info->channels;
1720 indio_dev->num_channels = data->chip_info->num_channels;
1721 indio_dev->name = name ? name : data->chip_info->name;
1722 indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1723 indio_dev->modes = INDIO_DIRECT_MODE;
1724 indio_dev->info = &bmc150_accel_info;
1726 if (block_supported) {
1727 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1728 indio_dev->info = &bmc150_accel_info_fifo;
1729 fifo_attrs = bmc150_accel_fifo_attributes;
1734 ret = iio_triggered_buffer_setup_ext(indio_dev,
1735 &iio_pollfunc_store_time,
1736 bmc150_accel_trigger_handler,
1737 &bmc150_accel_buffer_ops,
1740 dev_err(dev, "Failed: iio triggered buffer setup\n");
1741 goto err_disable_regulators;
1745 ret = devm_request_threaded_irq(dev, irq,
1746 bmc150_accel_irq_handler,
1747 bmc150_accel_irq_thread_handler,
1748 IRQF_TRIGGER_RISING,
1749 BMC150_ACCEL_IRQ_NAME,
1752 goto err_buffer_cleanup;
1755 * Set latched mode interrupt. While certain interrupts are
1756 * non-latched regardless of this settings (e.g. new data) we
1757 * want to use latch mode when we can to prevent interrupt
1760 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1761 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1763 dev_err(dev, "Error writing reg_int_rst_latch\n");
1764 goto err_buffer_cleanup;
1767 bmc150_accel_interrupts_setup(indio_dev, data, irq);
1769 ret = bmc150_accel_triggers_setup(indio_dev, data);
1771 goto err_buffer_cleanup;
1774 ret = pm_runtime_set_active(dev);
1776 goto err_trigger_unregister;
1778 pm_runtime_enable(dev);
1779 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1780 pm_runtime_use_autosuspend(dev);
1782 ret = iio_device_register(indio_dev);
1784 dev_err(dev, "Unable to register iio device\n");
1785 goto err_pm_cleanup;
1791 pm_runtime_dont_use_autosuspend(dev);
1792 pm_runtime_disable(dev);
1793 err_trigger_unregister:
1794 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1796 iio_triggered_buffer_cleanup(indio_dev);
1797 err_disable_regulators:
1798 regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1803 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1805 int bmc150_accel_core_remove(struct device *dev)
1807 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1808 struct bmc150_accel_data *data = iio_priv(indio_dev);
1810 iio_device_unregister(indio_dev);
1812 pm_runtime_disable(dev);
1813 pm_runtime_set_suspended(dev);
1815 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1817 iio_triggered_buffer_cleanup(indio_dev);
1819 mutex_lock(&data->mutex);
1820 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1821 mutex_unlock(&data->mutex);
1823 regulator_bulk_disable(ARRAY_SIZE(data->regulators),
1828 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1830 #ifdef CONFIG_PM_SLEEP
1831 static int bmc150_accel_suspend(struct device *dev)
1833 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1834 struct bmc150_accel_data *data = iio_priv(indio_dev);
1836 mutex_lock(&data->mutex);
1837 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1838 mutex_unlock(&data->mutex);
1843 static int bmc150_accel_resume(struct device *dev)
1845 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1846 struct bmc150_accel_data *data = iio_priv(indio_dev);
1848 mutex_lock(&data->mutex);
1849 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1850 bmc150_accel_fifo_set_mode(data);
1851 mutex_unlock(&data->mutex);
1853 if (data->resume_callback)
1854 data->resume_callback(dev);
1861 static int bmc150_accel_runtime_suspend(struct device *dev)
1863 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1864 struct bmc150_accel_data *data = iio_priv(indio_dev);
1867 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1874 static int bmc150_accel_runtime_resume(struct device *dev)
1876 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1877 struct bmc150_accel_data *data = iio_priv(indio_dev);
1881 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1884 ret = bmc150_accel_fifo_set_mode(data);
1888 sleep_val = bmc150_accel_get_startup_times(data);
1890 usleep_range(sleep_val * 1000, 20000);
1892 msleep_interruptible(sleep_val);
1898 const struct dev_pm_ops bmc150_accel_pm_ops = {
1899 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1900 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1901 bmc150_accel_runtime_resume, NULL)
1903 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1905 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1906 MODULE_LICENSE("GPL v2");
1907 MODULE_DESCRIPTION("BMC150 accelerometer driver");