drivers/iio/accel/bmc150-accel-core.c

   1 /*
   2  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
   3  *  - BMC150
   4  *  - BMI055
   5  *  - BMA255
   6  *  - BMA250E
   7  *  - BMA222E
   8  *  - BMA280
   9  *
  10  * Copyright (c) 2014, Intel Corporation.
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms and conditions of the GNU General Public License,
  14  * version 2, as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/i2c.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/acpi.h>
  28 #include <linux/gpio/consumer.h>
  29 #include <linux/pm.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/iio/iio.h>
  32 #include <linux/iio/sysfs.h>
  33 #include <linux/iio/buffer.h>
  34 #include <linux/iio/events.h>
  35 #include <linux/iio/trigger.h>
  36 #include <linux/iio/trigger_consumer.h>
  37 #include <linux/iio/triggered_buffer.h>
  38 #include <linux/regmap.h>
  39
  40 #include "bmc150-accel.h"
  41
  42 #define BMC150_ACCEL_DRV_NAME                   "bmc150_accel"
  43 #define BMC150_ACCEL_IRQ_NAME                   "bmc150_accel_event"
  44
  45 #define BMC150_ACCEL_REG_CHIP_ID                0x00
  46
  47 #define BMC150_ACCEL_REG_INT_STATUS_2           0x0B
  48 #define BMC150_ACCEL_ANY_MOTION_MASK            0x07
  49 #define BMC150_ACCEL_ANY_MOTION_BIT_X           BIT(0)
  50 #define BMC150_ACCEL_ANY_MOTION_BIT_Y           BIT(1)
  51 #define BMC150_ACCEL_ANY_MOTION_BIT_Z           BIT(2)
  52 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN        BIT(3)
  53
  54 #define BMC150_ACCEL_REG_PMU_LPW                0x11
  55 #define BMC150_ACCEL_PMU_MODE_MASK              0xE0
  56 #define BMC150_ACCEL_PMU_MODE_SHIFT             5
  57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK     0x17
  58 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT    1
  59
  60 #define BMC150_ACCEL_REG_PMU_RANGE              0x0F
  61
  62 #define BMC150_ACCEL_DEF_RANGE_2G               0x03
  63 #define BMC150_ACCEL_DEF_RANGE_4G               0x05
  64 #define BMC150_ACCEL_DEF_RANGE_8G               0x08
  65 #define BMC150_ACCEL_DEF_RANGE_16G              0x0C
  66
  67 /* Default BW: 125Hz */
  68 #define BMC150_ACCEL_REG_PMU_BW         0x10
  69 #define BMC150_ACCEL_DEF_BW                     125
  70
  71 #define BMC150_ACCEL_REG_RESET                  0x14
  72 #define BMC150_ACCEL_RESET_VAL                  0xB6
  73
  74 #define BMC150_ACCEL_REG_INT_MAP_0              0x19
  75 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE        BIT(2)
  76
  77 #define BMC150_ACCEL_REG_INT_MAP_1              0x1A
  78 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA         BIT(0)
  79 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM          BIT(1)
  80 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL        BIT(2)
  81
  82 #define BMC150_ACCEL_REG_INT_RST_LATCH          0x21
  83 #define BMC150_ACCEL_INT_MODE_LATCH_RESET       0x80
  84 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
  85 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT     0x00
  86
  87 #define BMC150_ACCEL_REG_INT_EN_0               0x16
  88 #define BMC150_ACCEL_INT_EN_BIT_SLP_X           BIT(0)
  89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y           BIT(1)
  90 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z           BIT(2)
  91
  92 #define BMC150_ACCEL_REG_INT_EN_1               0x17
  93 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN         BIT(4)
  94 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN        BIT(5)
  95 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN          BIT(6)
  96
  97 #define BMC150_ACCEL_REG_INT_OUT_CTRL           0x20
  98 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL      BIT(0)
  99
 100 #define BMC150_ACCEL_REG_INT_5                  0x27
 101 #define BMC150_ACCEL_SLOPE_DUR_MASK             0x03
 102
 103 #define BMC150_ACCEL_REG_INT_6                  0x28
 104 #define BMC150_ACCEL_SLOPE_THRES_MASK           0xFF
 105
 106 /* Slope duration in terms of number of samples */
 107 #define BMC150_ACCEL_DEF_SLOPE_DURATION         1
 108 /* in terms of multiples of g's/LSB, based on range */
 109 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD        1
 110
 111 #define BMC150_ACCEL_REG_XOUT_L         0x02
 112
 113 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS        100
 114
 115 /* Sleep Duration values */
 116 #define BMC150_ACCEL_SLEEP_500_MICRO            0x05
 117 #define BMC150_ACCEL_SLEEP_1_MS         0x06
 118 #define BMC150_ACCEL_SLEEP_2_MS         0x07
 119 #define BMC150_ACCEL_SLEEP_4_MS         0x08
 120 #define BMC150_ACCEL_SLEEP_6_MS         0x09
 121 #define BMC150_ACCEL_SLEEP_10_MS                0x0A
 122 #define BMC150_ACCEL_SLEEP_25_MS                0x0B
 123 #define BMC150_ACCEL_SLEEP_50_MS                0x0C
 124 #define BMC150_ACCEL_SLEEP_100_MS               0x0D
 125 #define BMC150_ACCEL_SLEEP_500_MS               0x0E
 126 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 127
 128 #define BMC150_ACCEL_REG_TEMP                   0x08
 129 #define BMC150_ACCEL_TEMP_CENTER_VAL            23
 130
 131 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 132 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
 133
 134 #define BMC150_ACCEL_REG_FIFO_STATUS            0x0E
 135 #define BMC150_ACCEL_REG_FIFO_CONFIG0           0x30
 136 #define BMC150_ACCEL_REG_FIFO_CONFIG1           0x3E
 137 #define BMC150_ACCEL_REG_FIFO_DATA              0x3F
 138 #define BMC150_ACCEL_FIFO_LENGTH                32
 139
 140 enum bmc150_accel_axis {
 141         AXIS_X,
 142         AXIS_Y,
 143         AXIS_Z,
 144 };
 145
 146 enum bmc150_power_modes {
 147         BMC150_ACCEL_SLEEP_MODE_NORMAL,
 148         BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
 149         BMC150_ACCEL_SLEEP_MODE_LPM,
 150         BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
 151 };
 152
 153 struct bmc150_scale_info {
 154         int scale;
 155         u8 reg_range;
 156 };
 157
 158 struct bmc150_accel_chip_info {
 159         const char *name;
 160         u8 chip_id;
 161         const struct iio_chan_spec *channels;
 162         int num_channels;
 163         const struct bmc150_scale_info scale_table[4];
 164 };
 165
 166 struct bmc150_accel_interrupt {
 167         const struct bmc150_accel_interrupt_info *info;
 168         atomic_t users;
 169 };
 170
 171 struct bmc150_accel_trigger {
 172         struct bmc150_accel_data *data;
 173         struct iio_trigger *indio_trig;
 174         int (*setup)(struct bmc150_accel_trigger *t, bool state);
 175         int intr;
 176         bool enabled;
 177 };
 178
 179 enum bmc150_accel_interrupt_id {
 180         BMC150_ACCEL_INT_DATA_READY,
 181         BMC150_ACCEL_INT_ANY_MOTION,
 182         BMC150_ACCEL_INT_WATERMARK,
 183         BMC150_ACCEL_INTERRUPTS,
 184 };
 185
 186 enum bmc150_accel_trigger_id {
 187         BMC150_ACCEL_TRIGGER_DATA_READY,
 188         BMC150_ACCEL_TRIGGER_ANY_MOTION,
 189         BMC150_ACCEL_TRIGGERS,
 190 };
 191
 192 struct bmc150_accel_data {
 193         struct regmap *regmap;
 194         struct device *dev;
 195         int irq;
 196         struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
 197         struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
 198         struct mutex mutex;
 199         u8 fifo_mode, watermark;
 200         s16 buffer[8];
 201         /*
 202          * Ensure there is sufficient space and correct alignment for
 203          * the timestamp if enabled
 204          */
 205         struct {
 206                 __le16 channels[3];
 207                 s64 ts __aligned(8);
 208         } scan;
 209         u8 bw_bits;
 210         u32 slope_dur;
 211         u32 slope_thres;
 212         u32 range;
 213         int ev_enable_state;
 214         int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
 215         const struct bmc150_accel_chip_info *chip_info;
 216 };
 217
 218 static const struct {
 219         int val;
 220         int val2;
 221         u8 bw_bits;
 222 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
 223                                      {31, 260000, 0x09},
 224                                      {62, 500000, 0x0A},
 225                                      {125, 0, 0x0B},
 226                                      {250, 0, 0x0C},
 227                                      {500, 0, 0x0D},
 228                                      {1000, 0, 0x0E},
 229                                      {2000, 0, 0x0F} };
 230
 231 static const struct {
 232         int bw_bits;
 233         int msec;
 234 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
 235                                      {0x09, 32},
 236                                      {0x0A, 16},
 237                                      {0x0B, 8},
 238                                      {0x0C, 4},
 239                                      {0x0D, 2},
 240                                      {0x0E, 1},
 241                                      {0x0F, 1} };
 242
 243 static const struct {
 244         int sleep_dur;
 245         u8 reg_value;
 246 } bmc150_accel_sleep_value_table[] = { {0, 0},
 247                                        {500, BMC150_ACCEL_SLEEP_500_MICRO},
 248                                        {1000, BMC150_ACCEL_SLEEP_1_MS},
 249                                        {2000, BMC150_ACCEL_SLEEP_2_MS},
 250                                        {4000, BMC150_ACCEL_SLEEP_4_MS},
 251                                        {6000, BMC150_ACCEL_SLEEP_6_MS},
 252                                        {10000, BMC150_ACCEL_SLEEP_10_MS},
 253                                        {25000, BMC150_ACCEL_SLEEP_25_MS},
 254                                        {50000, BMC150_ACCEL_SLEEP_50_MS},
 255                                        {100000, BMC150_ACCEL_SLEEP_100_MS},
 256                                        {500000, BMC150_ACCEL_SLEEP_500_MS},
 257                                        {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
 258
 259 static const struct regmap_config bmc150_i2c_regmap_conf = {
 260         .reg_bits = 8,
 261         .val_bits = 8,
 262         .max_register = 0x3f,
 263 };
 264
 265 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
 266                                  enum bmc150_power_modes mode,
 267                                  int dur_us)
 268 {
 269         int i;
 270         int ret;
 271         u8 lpw_bits;
 272         int dur_val = -1;
 273
 274         if (dur_us > 0) {
 275                 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
 276                                                                          ++i) {
 277                         if (bmc150_accel_sleep_value_table[i].sleep_dur ==
 278                                                                         dur_us)
 279                                 dur_val =
 280                                 bmc150_accel_sleep_value_table[i].reg_value;
 281                 }
 282         } else {
 283                 dur_val = 0;
 284         }
 285
 286         if (dur_val < 0)
 287                 return -EINVAL;
 288
 289         lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
 290         lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
 291
 292         dev_dbg(data->dev, "Set Mode bits %x\n", lpw_bits);
 293
 294         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
 295         if (ret < 0) {
 296                 dev_err(data->dev, "Error writing reg_pmu_lpw\n");
 297                 return ret;
 298         }
 299
 300         return 0;
 301 }
 302
 303 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
 304                                int val2)
 305 {
 306         int i;
 307         int ret;
 308
 309         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 310                 if (bmc150_accel_samp_freq_table[i].val == val &&
 311                     bmc150_accel_samp_freq_table[i].val2 == val2) {
 312                         ret = regmap_write(data->regmap,
 313                                 BMC150_ACCEL_REG_PMU_BW,
 314                                 bmc150_accel_samp_freq_table[i].bw_bits);
 315                         if (ret < 0)
 316                                 return ret;
 317
 318                         data->bw_bits =
 319                                 bmc150_accel_samp_freq_table[i].bw_bits;
 320                         return 0;
 321                 }
 322         }
 323
 324         return -EINVAL;
 325 }
 326
 327 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
 328 {
 329         int ret;
 330
 331         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
 332                                         data->slope_thres);
 333         if (ret < 0) {
 334                 dev_err(data->dev, "Error writing reg_int_6\n");
 335                 return ret;
 336         }
 337
 338         ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
 339                                  BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
 340         if (ret < 0) {
 341                 dev_err(data->dev, "Error updating reg_int_5\n");
 342                 return ret;
 343         }
 344
 345         dev_dbg(data->dev, "%s: %x %x\n", __func__, data->slope_thres,
 346                 data->slope_dur);
 347
 348         return ret;
 349 }
 350
 351 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
 352                                          bool state)
 353 {
 354         if (state)
 355                 return bmc150_accel_update_slope(t->data);
 356
 357         return 0;
 358 }
 359
 360 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
 361                                int *val2)
 362 {
 363         int i;
 364
 365         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 366                 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
 367                         *val = bmc150_accel_samp_freq_table[i].val;
 368                         *val2 = bmc150_accel_samp_freq_table[i].val2;
 369                         return IIO_VAL_INT_PLUS_MICRO;
 370                 }
 371         }
 372
 373         return -EINVAL;
 374 }
 375
 376 #ifdef CONFIG_PM
 377 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
 378 {
 379         int i;
 380
 381         for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
 382                 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
 383                         return bmc150_accel_sample_upd_time[i].msec;
 384         }
 385
 386         return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
 387 }
 388
 389 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 390 {
 391         int ret;
 392
 393         if (on) {
 394                 ret = pm_runtime_get_sync(data->dev);
 395         } else {
 396                 pm_runtime_mark_last_busy(data->dev);
 397                 ret = pm_runtime_put_autosuspend(data->dev);
 398         }
 399
 400         if (ret < 0) {
 401                 dev_err(data->dev,
 402                         "Failed: bmc150_accel_set_power_state for %d\n", on);
 403                 if (on)
 404                         pm_runtime_put_noidle(data->dev);
 405
 406                 return ret;
 407         }
 408
 409         return 0;
 410 }
 411 #else
 412 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 413 {
 414         return 0;
 415 }
 416 #endif
 417
 418 static const struct bmc150_accel_interrupt_info {
 419         u8 map_reg;
 420         u8 map_bitmask;
 421         u8 en_reg;
 422         u8 en_bitmask;
 423 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
 424         { /* data ready interrupt */
 425                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 426                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
 427                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 428                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
 429         },
 430         {  /* motion interrupt */
 431                 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
 432                 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
 433                 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
 434                 .en_bitmask =  BMC150_ACCEL_INT_EN_BIT_SLP_X |
 435                         BMC150_ACCEL_INT_EN_BIT_SLP_Y |
 436                         BMC150_ACCEL_INT_EN_BIT_SLP_Z
 437         },
 438         { /* fifo watermark interrupt */
 439                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 440                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
 441                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 442                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
 443         },
 444 };
 445
 446 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
 447                                           struct bmc150_accel_data *data)
 448 {
 449         int i;
 450
 451         for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
 452                 data->interrupts[i].info = &bmc150_accel_interrupts[i];
 453 }
 454
 455 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
 456                                       bool state)
 457 {
 458         struct bmc150_accel_interrupt *intr = &data->interrupts[i];
 459         const struct bmc150_accel_interrupt_info *info = intr->info;
 460         int ret;
 461
 462         if (state) {
 463                 if (atomic_inc_return(&intr->users) > 1)
 464                         return 0;
 465         } else {
 466                 if (atomic_dec_return(&intr->users) > 0)
 467                         return 0;
 468         }
 469
 470         /*
 471          * We will expect the enable and disable to do operation in reverse
 472          * order. This will happen here anyway, as our resume operation uses
 473          * sync mode runtime pm calls. The suspend operation will be delayed
 474          * by autosuspend delay.
 475          * So the disable operation will still happen in reverse order of
 476          * enable operation. When runtime pm is disabled the mode is always on,
 477          * so sequence doesn't matter.
 478          */
 479         ret = bmc150_accel_set_power_state(data, state);
 480         if (ret < 0)
 481                 return ret;
 482
 483         /* map the interrupt to the appropriate pins */
 484         ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
 485                                  (state ? info->map_bitmask : 0));
 486         if (ret < 0) {
 487                 dev_err(data->dev, "Error updating reg_int_map\n");
 488                 goto out_fix_power_state;
 489         }
 490
 491         /* enable/disable the interrupt */
 492         ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
 493                                  (state ? info->en_bitmask : 0));
 494         if (ret < 0) {
 495                 dev_err(data->dev, "Error updating reg_int_en\n");
 496                 goto out_fix_power_state;
 497         }
 498
 499         return 0;
 500
 501 out_fix_power_state:
 502         bmc150_accel_set_power_state(data, false);
 503         return ret;
 504 }
 505
 506 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
 507 {
 508         int ret, i;
 509
 510         for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
 511                 if (data->chip_info->scale_table[i].scale == val) {
 512                         ret = regmap_write(data->regmap,
 513                                      BMC150_ACCEL_REG_PMU_RANGE,
 514                                      data->chip_info->scale_table[i].reg_range);
 515                         if (ret < 0) {
 516                                 dev_err(data->dev,
 517                                         "Error writing pmu_range\n");
 518                                 return ret;
 519                         }
 520
 521                         data->range = data->chip_info->scale_table[i].reg_range;
 522                         return 0;
 523                 }
 524         }
 525
 526         return -EINVAL;
 527 }
 528
 529 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
 530 {
 531         int ret;
 532         unsigned int value;
 533
 534         mutex_lock(&data->mutex);
 535
 536         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
 537         if (ret < 0) {
 538                 dev_err(data->dev, "Error reading reg_temp\n");
 539                 mutex_unlock(&data->mutex);
 540                 return ret;
 541         }
 542         *val = sign_extend32(value, 7);
 543
 544         mutex_unlock(&data->mutex);
 545
 546         return IIO_VAL_INT;
 547 }
 548
 549 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
 550                                  struct iio_chan_spec const *chan,
 551                                  int *val)
 552 {
 553         int ret;
 554         int axis = chan->scan_index;
 555         __le16 raw_val;
 556
 557         mutex_lock(&data->mutex);
 558         ret = bmc150_accel_set_power_state(data, true);
 559         if (ret < 0) {
 560                 mutex_unlock(&data->mutex);
 561                 return ret;
 562         }
 563
 564         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
 565                                &raw_val, sizeof(raw_val));
 566         if (ret < 0) {
 567                 dev_err(data->dev, "Error reading axis %d\n", axis);
 568                 bmc150_accel_set_power_state(data, false);
 569                 mutex_unlock(&data->mutex);
 570                 return ret;
 571         }
 572         *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
 573                              chan->scan_type.realbits - 1);
 574         ret = bmc150_accel_set_power_state(data, false);
 575         mutex_unlock(&data->mutex);
 576         if (ret < 0)
 577                 return ret;
 578
 579         return IIO_VAL_INT;
 580 }
 581
 582 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
 583                                  struct iio_chan_spec const *chan,
 584                                  int *val, int *val2, long mask)
 585 {
 586         struct bmc150_accel_data *data = iio_priv(indio_dev);
 587         int ret;
 588
 589         switch (mask) {
 590         case IIO_CHAN_INFO_RAW:
 591                 switch (chan->type) {
 592                 case IIO_TEMP:
 593                         return bmc150_accel_get_temp(data, val);
 594                 case IIO_ACCEL:
 595                         if (iio_buffer_enabled(indio_dev))
 596                                 return -EBUSY;
 597                         else
 598                                 return bmc150_accel_get_axis(data, chan, val);
 599                 default:
 600                         return -EINVAL;
 601                 }
 602         case IIO_CHAN_INFO_OFFSET:
 603                 if (chan->type == IIO_TEMP) {
 604                         *val = BMC150_ACCEL_TEMP_CENTER_VAL;
 605                         return IIO_VAL_INT;
 606                 } else {
 607                         return -EINVAL;
 608                 }
 609         case IIO_CHAN_INFO_SCALE:
 610                 *val = 0;
 611                 switch (chan->type) {
 612                 case IIO_TEMP:
 613                         *val2 = 500000;
 614                         return IIO_VAL_INT_PLUS_MICRO;
 615                 case IIO_ACCEL:
 616                 {
 617                         int i;
 618                         const struct bmc150_scale_info *si;
 619                         int st_size = ARRAY_SIZE(data->chip_info->scale_table);
 620
 621                         for (i = 0; i < st_size; ++i) {
 622                                 si = &data->chip_info->scale_table[i];
 623                                 if (si->reg_range == data->range) {
 624                                         *val2 = si->scale;
 625                                         return IIO_VAL_INT_PLUS_MICRO;
 626                                 }
 627                         }
 628                         return -EINVAL;
 629                 }
 630                 default:
 631                         return -EINVAL;
 632                 }
 633         case IIO_CHAN_INFO_SAMP_FREQ:
 634                 mutex_lock(&data->mutex);
 635                 ret = bmc150_accel_get_bw(data, val, val2);
 636                 mutex_unlock(&data->mutex);
 637                 return ret;
 638         default:
 639                 return -EINVAL;
 640         }
 641 }
 642
 643 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
 644                                   struct iio_chan_spec const *chan,
 645                                   int val, int val2, long mask)
 646 {
 647         struct bmc150_accel_data *data = iio_priv(indio_dev);
 648         int ret;
 649
 650         switch (mask) {
 651         case IIO_CHAN_INFO_SAMP_FREQ:
 652                 mutex_lock(&data->mutex);
 653                 ret = bmc150_accel_set_bw(data, val, val2);
 654                 mutex_unlock(&data->mutex);
 655                 break;
 656         case IIO_CHAN_INFO_SCALE:
 657                 if (val)
 658                         return -EINVAL;
 659
 660                 mutex_lock(&data->mutex);
 661                 ret = bmc150_accel_set_scale(data, val2);
 662                 mutex_unlock(&data->mutex);
 663                 return ret;
 664         default:
 665                 ret = -EINVAL;
 666         }
 667
 668         return ret;
 669 }
 670
 671 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
 672                                    const struct iio_chan_spec *chan,
 673                                    enum iio_event_type type,
 674                                    enum iio_event_direction dir,
 675                                    enum iio_event_info info,
 676                                    int *val, int *val2)
 677 {
 678         struct bmc150_accel_data *data = iio_priv(indio_dev);
 679
 680         *val2 = 0;
 681         switch (info) {
 682         case IIO_EV_INFO_VALUE:
 683                 *val = data->slope_thres;
 684                 break;
 685         case IIO_EV_INFO_PERIOD:
 686                 *val = data->slope_dur;
 687                 break;
 688         default:
 689                 return -EINVAL;
 690         }
 691
 692         return IIO_VAL_INT;
 693 }
 694
 695 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
 696                                     const struct iio_chan_spec *chan,
 697                                     enum iio_event_type type,
 698                                     enum iio_event_direction dir,
 699                                     enum iio_event_info info,
 700                                     int val, int val2)
 701 {
 702         struct bmc150_accel_data *data = iio_priv(indio_dev);
 703
 704         if (data->ev_enable_state)
 705                 return -EBUSY;
 706
 707         switch (info) {
 708         case IIO_EV_INFO_VALUE:
 709                 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
 710                 break;
 711         case IIO_EV_INFO_PERIOD:
 712                 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
 713                 break;
 714         default:
 715                 return -EINVAL;
 716         }
 717
 718         return 0;
 719 }
 720
 721 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
 722                                           const struct iio_chan_spec *chan,
 723                                           enum iio_event_type type,
 724                                           enum iio_event_direction dir)
 725 {
 726         struct bmc150_accel_data *data = iio_priv(indio_dev);
 727
 728         return data->ev_enable_state;
 729 }
 730
 731 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
 732                                            const struct iio_chan_spec *chan,
 733                                            enum iio_event_type type,
 734                                            enum iio_event_direction dir,
 735                                            int state)
 736 {
 737         struct bmc150_accel_data *data = iio_priv(indio_dev);
 738         int ret;
 739
 740         if (state == data->ev_enable_state)
 741                 return 0;
 742
 743         mutex_lock(&data->mutex);
 744
 745         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
 746                                          state);
 747         if (ret < 0) {
 748                 mutex_unlock(&data->mutex);
 749                 return ret;
 750         }
 751
 752         data->ev_enable_state = state;
 753         mutex_unlock(&data->mutex);
 754
 755         return 0;
 756 }
 757
 758 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
 759                                          struct iio_trigger *trig)
 760 {
 761         struct bmc150_accel_data *data = iio_priv(indio_dev);
 762         int i;
 763
 764         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
 765                 if (data->triggers[i].indio_trig == trig)
 766                         return 0;
 767         }
 768
 769         return -EINVAL;
 770 }
 771
 772 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
 773                                                struct device_attribute *attr,
 774                                                char *buf)
 775 {
 776         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 777         struct bmc150_accel_data *data = iio_priv(indio_dev);
 778         int wm;
 779
 780         mutex_lock(&data->mutex);
 781         wm = data->watermark;
 782         mutex_unlock(&data->mutex);
 783
 784         return sprintf(buf, "%d\n", wm);
 785 }
 786
 787 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
 788                                            struct device_attribute *attr,
 789                                            char *buf)
 790 {
 791         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 792         struct bmc150_accel_data *data = iio_priv(indio_dev);
 793         bool state;
 794
 795         mutex_lock(&data->mutex);
 796         state = data->fifo_mode;
 797         mutex_unlock(&data->mutex);
 798
 799         return sprintf(buf, "%d\n", state);
 800 }
 801
 802 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
 803 static IIO_CONST_ATTR(hwfifo_watermark_max,
 804                       __stringify(BMC150_ACCEL_FIFO_LENGTH));
 805 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
 806                        bmc150_accel_get_fifo_state, NULL, 0);
 807 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
 808                        bmc150_accel_get_fifo_watermark, NULL, 0);
 809
 810 static const struct attribute *bmc150_accel_fifo_attributes[] = {
 811         &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
 812         &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
 813         &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
 814         &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
 815         NULL,
 816 };
 817
 818 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
 819 {
 820         struct bmc150_accel_data *data = iio_priv(indio_dev);
 821
 822         if (val > BMC150_ACCEL_FIFO_LENGTH)
 823                 val = BMC150_ACCEL_FIFO_LENGTH;
 824
 825         mutex_lock(&data->mutex);
 826         data->watermark = val;
 827         mutex_unlock(&data->mutex);
 828
 829         return 0;
 830 }
 831
 832 /*
 833  * We must read at least one full frame in one burst, otherwise the rest of the
 834  * frame data is discarded.
 835  */
 836 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
 837                                       char *buffer, int samples)
 838 {
 839         int sample_length = 3 * 2;
 840         int ret;
 841         int total_length = samples * sample_length;
 842         int i;
 843         size_t step = regmap_get_raw_read_max(data->regmap);
 844
 845         if (!step || step > total_length)
 846                 step = total_length;
 847         else if (step < total_length)
 848                 step = sample_length;
 849
 850         /*
 851          * Seems we have a bus with size limitation so we have to execute
 852          * multiple reads
 853          */
 854         for (i = 0; i < total_length; i += step) {
 855                 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
 856                                       &buffer[i], step);
 857                 if (ret)
 858                         break;
 859         }
 860
 861         if (ret)
 862                 dev_err(data->dev, "Error transferring data from fifo in single steps of %zu\n",
 863                         step);
 864
 865         return ret;
 866 }
 867
 868 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
 869                                      unsigned samples, bool irq)
 870 {
 871         struct bmc150_accel_data *data = iio_priv(indio_dev);
 872         int ret, i;
 873         u8 count;
 874         u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
 875         int64_t tstamp;
 876         uint64_t sample_period;
 877         unsigned int val;
 878
 879         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
 880         if (ret < 0) {
 881                 dev_err(data->dev, "Error reading reg_fifo_status\n");
 882                 return ret;
 883         }
 884
 885         count = val & 0x7F;
 886
 887         if (!count)
 888                 return 0;
 889
 890         /*
 891          * If we getting called from IRQ handler we know the stored timestamp is
 892          * fairly accurate for the last stored sample. Otherwise, if we are
 893          * called as a result of a read operation from userspace and hence
 894          * before the watermark interrupt was triggered, take a timestamp
 895          * now. We can fall anywhere in between two samples so the error in this
 896          * case is at most one sample period.
 897          */
 898         if (!irq) {
 899                 data->old_timestamp = data->timestamp;
 900                 data->timestamp = iio_get_time_ns();
 901         }
 902
 903         /*
 904          * Approximate timestamps for each of the sample based on the sampling
 905          * frequency, timestamp for last sample and number of samples.
 906          *
 907          * Note that we can't use the current bandwidth settings to compute the
 908          * sample period because the sample rate varies with the device
 909          * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
 910          * small variation adds when we store a large number of samples and
 911          * creates significant jitter between the last and first samples in
 912          * different batches (e.g. 32ms vs 21ms).
 913          *
 914          * To avoid this issue we compute the actual sample period ourselves
 915          * based on the timestamp delta between the last two flush operations.
 916          */
 917         sample_period = (data->timestamp - data->old_timestamp);
 918         do_div(sample_period, count);
 919         tstamp = data->timestamp - (count - 1) * sample_period;
 920
 921         if (samples && count > samples)
 922                 count = samples;
 923
 924         ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
 925         if (ret)
 926                 return ret;
 927
 928         /*
 929          * Ideally we want the IIO core to handle the demux when running in fifo
 930          * mode but not when running in triggered buffer mode. Unfortunately
 931          * this does not seem to be possible, so stick with driver demux for
 932          * now.
 933          */
 934         for (i = 0; i < count; i++) {
 935                 int j, bit;
 936
 937                 j = 0;
 938                 for_each_set_bit(bit, indio_dev->active_scan_mask,
 939                                  indio_dev->masklength)
 940                         memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
 941                                sizeof(data->scan.channels[0]));
 942
 943                 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
 944                                                    tstamp);
 945
 946                 tstamp += sample_period;
 947         }
 948
 949         return count;
 950 }
 951
 952 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
 953 {
 954         struct bmc150_accel_data *data = iio_priv(indio_dev);
 955         int ret;
 956
 957         mutex_lock(&data->mutex);
 958         ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
 959         mutex_unlock(&data->mutex);
 960
 961         return ret;
 962 }
 963
 964 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
 965                 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
 966
 967 static struct attribute *bmc150_accel_attributes[] = {
 968         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 969         NULL,
 970 };
 971
 972 static const struct attribute_group bmc150_accel_attrs_group = {
 973         .attrs = bmc150_accel_attributes,
 974 };
 975
 976 static const struct iio_event_spec bmc150_accel_event = {
 977                 .type = IIO_EV_TYPE_ROC,
 978                 .dir = IIO_EV_DIR_EITHER,
 979                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 980                                  BIT(IIO_EV_INFO_ENABLE) |
 981                                  BIT(IIO_EV_INFO_PERIOD)
 982 };
 983
 984 #define BMC150_ACCEL_CHANNEL(_axis, bits) {                             \
 985         .type = IIO_ACCEL,                                              \
 986         .modified = 1,                                                  \
 987         .channel2 = IIO_MOD_##_axis,                                    \
 988         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
 989         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
 990                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),           \
 991         .scan_index = AXIS_##_axis,                                     \
 992         .scan_type = {                                                  \
 993                 .sign = 's',                                            \
 994                 .realbits = (bits),                                     \
 995                 .storagebits = 16,                                      \
 996                 .shift = 16 - (bits),                                   \
 997                 .endianness = IIO_LE,                                   \
 998         },                                                              \
 999         .event_spec = &bmc150_accel_event,                              \
1000         .num_event_specs = 1                                            \
1001 }
1002
1003 #define BMC150_ACCEL_CHANNELS(bits) {                                   \
1004         {                                                               \
1005                 .type = IIO_TEMP,                                       \
1006                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
1007                                       BIT(IIO_CHAN_INFO_SCALE) |        \
1008                                       BIT(IIO_CHAN_INFO_OFFSET),        \
1009                 .scan_index = -1,                                       \
1010         },                                                              \
1011         BMC150_ACCEL_CHANNEL(X, bits),                                  \
1012         BMC150_ACCEL_CHANNEL(Y, bits),                                  \
1013         BMC150_ACCEL_CHANNEL(Z, bits),                                  \
1014         IIO_CHAN_SOFT_TIMESTAMP(3),                                     \
1015 }
1016
1017 static const struct iio_chan_spec bma222e_accel_channels[] =
1018         BMC150_ACCEL_CHANNELS(8);
1019 static const struct iio_chan_spec bma250e_accel_channels[] =
1020         BMC150_ACCEL_CHANNELS(10);
1021 static const struct iio_chan_spec bmc150_accel_channels[] =
1022         BMC150_ACCEL_CHANNELS(12);
1023 static const struct iio_chan_spec bma280_accel_channels[] =
1024         BMC150_ACCEL_CHANNELS(14);
1025
1026 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1027         [bmc150] = {
1028                 .name = "BMC150A",
1029                 .chip_id = 0xFA,
1030                 .channels = bmc150_accel_channels,
1031                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1032                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1033                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1034                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1035                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1036         },
1037         [bmi055] = {
1038                 .name = "BMI055A",
1039                 .chip_id = 0xFA,
1040                 .channels = bmc150_accel_channels,
1041                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1042                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1043                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1044                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1045                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1046         },
1047         [bma255] = {
1048                 .name = "BMA0255",
1049                 .chip_id = 0xFA,
1050                 .channels = bmc150_accel_channels,
1051                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1052                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1053                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1054                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1055                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1056         },
1057         [bma250e] = {
1058                 .name = "BMA250E",
1059                 .chip_id = 0xF9,
1060                 .channels = bma250e_accel_channels,
1061                 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1062                 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1063                                  {76590, BMC150_ACCEL_DEF_RANGE_4G},
1064                                  {153277, BMC150_ACCEL_DEF_RANGE_8G},
1065                                  {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1066         },
1067         [bma222e] = {
1068                 .name = "BMA222E",
1069                 .chip_id = 0xF8,
1070                 .channels = bma222e_accel_channels,
1071                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1072                 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1073                                  {306457, BMC150_ACCEL_DEF_RANGE_4G},
1074                                  {612915, BMC150_ACCEL_DEF_RANGE_8G},
1075                                  {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1076         },
1077         [bma280] = {
1078                 .name = "BMA0280",
1079                 .chip_id = 0xFB,
1080                 .channels = bma280_accel_channels,
1081                 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1082                 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1083                                  {4785, BMC150_ACCEL_DEF_RANGE_4G},
1084                                  {9581, BMC150_ACCEL_DEF_RANGE_8G},
1085                                  {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1086         },
1087 };
1088
1089 static const struct iio_info bmc150_accel_info = {
1090         .attrs                  = &bmc150_accel_attrs_group,
1091         .read_raw               = bmc150_accel_read_raw,
1092         .write_raw              = bmc150_accel_write_raw,
1093         .read_event_value       = bmc150_accel_read_event,
1094         .write_event_value      = bmc150_accel_write_event,
1095         .write_event_config     = bmc150_accel_write_event_config,
1096         .read_event_config      = bmc150_accel_read_event_config,
1097         .driver_module          = THIS_MODULE,
1098 };
1099
1100 static const struct iio_info bmc150_accel_info_fifo = {
1101         .attrs                  = &bmc150_accel_attrs_group,
1102         .read_raw               = bmc150_accel_read_raw,
1103         .write_raw              = bmc150_accel_write_raw,
1104         .read_event_value       = bmc150_accel_read_event,
1105         .write_event_value      = bmc150_accel_write_event,
1106         .write_event_config     = bmc150_accel_write_event_config,
1107         .read_event_config      = bmc150_accel_read_event_config,
1108         .validate_trigger       = bmc150_accel_validate_trigger,
1109         .hwfifo_set_watermark   = bmc150_accel_set_watermark,
1110         .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1111         .driver_module          = THIS_MODULE,
1112 };
1113
1114 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1115 {
1116         struct iio_poll_func *pf = p;
1117         struct iio_dev *indio_dev = pf->indio_dev;
1118         struct bmc150_accel_data *data = iio_priv(indio_dev);
1119         int bit, ret, i = 0;
1120         unsigned int raw_val;
1121
1122         mutex_lock(&data->mutex);
1123         for_each_set_bit(bit, indio_dev->active_scan_mask,
1124                          indio_dev->masklength) {
1125                 ret = regmap_bulk_read(data->regmap,
1126                                        BMC150_ACCEL_AXIS_TO_REG(bit), &raw_val,
1127                                        2);
1128                 if (ret < 0) {
1129                         mutex_unlock(&data->mutex);
1130                         goto err_read;
1131                 }
1132                 data->buffer[i++] = raw_val;
1133         }
1134         mutex_unlock(&data->mutex);
1135
1136         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1137                                            pf->timestamp);
1138 err_read:
1139         iio_trigger_notify_done(indio_dev->trig);
1140
1141         return IRQ_HANDLED;
1142 }
1143
1144 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1145 {
1146         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1147         struct bmc150_accel_data *data = t->data;
1148         int ret;
1149
1150         /* new data interrupts don't need ack */
1151         if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1152                 return 0;
1153
1154         mutex_lock(&data->mutex);
1155         /* clear any latched interrupt */
1156         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1157                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1158                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1159         mutex_unlock(&data->mutex);
1160         if (ret < 0) {
1161                 dev_err(data->dev,
1162                         "Error writing reg_int_rst_latch\n");
1163                 return ret;
1164         }
1165
1166         return 0;
1167 }
1168
1169 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1170                                           bool state)
1171 {
1172         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1173         struct bmc150_accel_data *data = t->data;
1174         int ret;
1175
1176         mutex_lock(&data->mutex);
1177
1178         if (t->enabled == state) {
1179                 mutex_unlock(&data->mutex);
1180                 return 0;
1181         }
1182
1183         if (t->setup) {
1184                 ret = t->setup(t, state);
1185                 if (ret < 0) {
1186                         mutex_unlock(&data->mutex);
1187                         return ret;
1188                 }
1189         }
1190
1191         ret = bmc150_accel_set_interrupt(data, t->intr, state);
1192         if (ret < 0) {
1193                 mutex_unlock(&data->mutex);
1194                 return ret;
1195         }
1196
1197         t->enabled = state;
1198
1199         mutex_unlock(&data->mutex);
1200
1201         return ret;
1202 }
1203
1204 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1205         .set_trigger_state = bmc150_accel_trigger_set_state,
1206         .try_reenable = bmc150_accel_trig_try_reen,
1207         .owner = THIS_MODULE,
1208 };
1209
1210 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1211 {
1212         struct bmc150_accel_data *data = iio_priv(indio_dev);
1213         int dir;
1214         int ret;
1215         unsigned int val;
1216
1217         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1218         if (ret < 0) {
1219                 dev_err(data->dev, "Error reading reg_int_status_2\n");
1220                 return ret;
1221         }
1222
1223         if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1224                 dir = IIO_EV_DIR_FALLING;
1225         else
1226                 dir = IIO_EV_DIR_RISING;
1227
1228         if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1229                 iio_push_event(indio_dev,
1230                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1231                                                   0,
1232                                                   IIO_MOD_X,
1233                                                   IIO_EV_TYPE_ROC,
1234                                                   dir),
1235                                data->timestamp);
1236
1237         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1238                 iio_push_event(indio_dev,
1239                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1240                                                   0,
1241                                                   IIO_MOD_Y,
1242                                                   IIO_EV_TYPE_ROC,
1243                                                   dir),
1244                                data->timestamp);
1245
1246         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1247                 iio_push_event(indio_dev,
1248                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1249                                                   0,
1250                                                   IIO_MOD_Z,
1251                                                   IIO_EV_TYPE_ROC,
1252                                                   dir),
1253                                data->timestamp);
1254
1255         return ret;
1256 }
1257
1258 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1259 {
1260         struct iio_dev *indio_dev = private;
1261         struct bmc150_accel_data *data = iio_priv(indio_dev);
1262         bool ack = false;
1263         int ret;
1264
1265         mutex_lock(&data->mutex);
1266
1267         if (data->fifo_mode) {
1268                 ret = __bmc150_accel_fifo_flush(indio_dev,
1269                                                 BMC150_ACCEL_FIFO_LENGTH, true);
1270                 if (ret > 0)
1271                         ack = true;
1272         }
1273
1274         if (data->ev_enable_state) {
1275                 ret = bmc150_accel_handle_roc_event(indio_dev);
1276                 if (ret > 0)
1277                         ack = true;
1278         }
1279
1280         if (ack) {
1281                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1282                                    BMC150_ACCEL_INT_MODE_LATCH_INT |
1283                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1284                 if (ret)
1285                         dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1286
1287                 ret = IRQ_HANDLED;
1288         } else {
1289                 ret = IRQ_NONE;
1290         }
1291
1292         mutex_unlock(&data->mutex);
1293
1294         return ret;
1295 }
1296
1297 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1298 {
1299         struct iio_dev *indio_dev = private;
1300         struct bmc150_accel_data *data = iio_priv(indio_dev);
1301         bool ack = false;
1302         int i;
1303
1304         data->old_timestamp = data->timestamp;
1305         data->timestamp = iio_get_time_ns();
1306
1307         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1308                 if (data->triggers[i].enabled) {
1309                         iio_trigger_poll(data->triggers[i].indio_trig);
1310                         ack = true;
1311                         break;
1312                 }
1313         }
1314
1315         if (data->ev_enable_state || data->fifo_mode)
1316                 return IRQ_WAKE_THREAD;
1317
1318         if (ack)
1319                 return IRQ_HANDLED;
1320
1321         return IRQ_NONE;
1322 }
1323
1324 static const struct {
1325         int intr;
1326         const char *name;
1327         int (*setup)(struct bmc150_accel_trigger *t, bool state);
1328 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1329         {
1330                 .intr = 0,
1331                 .name = "%s-dev%d",
1332         },
1333         {
1334                 .intr = 1,
1335                 .name = "%s-any-motion-dev%d",
1336                 .setup = bmc150_accel_any_motion_setup,
1337         },
1338 };
1339
1340 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1341                                              int from)
1342 {
1343         int i;
1344
1345         for (i = from; i >= 0; i--) {
1346                 if (data->triggers[i].indio_trig) {
1347                         iio_trigger_unregister(data->triggers[i].indio_trig);
1348                         data->triggers[i].indio_trig = NULL;
1349                 }
1350         }
1351 }
1352
1353 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1354                                        struct bmc150_accel_data *data)
1355 {
1356         int i, ret;
1357
1358         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1359                 struct bmc150_accel_trigger *t = &data->triggers[i];
1360
1361                 t->indio_trig = devm_iio_trigger_alloc(data->dev,
1362                                                bmc150_accel_triggers[i].name,
1363                                                        indio_dev->name,
1364                                                        indio_dev->id);
1365                 if (!t->indio_trig) {
1366                         ret = -ENOMEM;
1367                         break;
1368                 }
1369
1370                 t->indio_trig->dev.parent = data->dev;
1371                 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1372                 t->intr = bmc150_accel_triggers[i].intr;
1373                 t->data = data;
1374                 t->setup = bmc150_accel_triggers[i].setup;
1375                 iio_trigger_set_drvdata(t->indio_trig, t);
1376
1377                 ret = iio_trigger_register(t->indio_trig);
1378                 if (ret)
1379                         break;
1380         }
1381
1382         if (ret)
1383                 bmc150_accel_unregister_triggers(data, i - 1);
1384
1385         return ret;
1386 }
1387
1388 #define BMC150_ACCEL_FIFO_MODE_STREAM          0x80
1389 #define BMC150_ACCEL_FIFO_MODE_FIFO            0x40
1390 #define BMC150_ACCEL_FIFO_MODE_BYPASS          0x00
1391
1392 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1393 {
1394         u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1395         int ret;
1396
1397         ret = regmap_write(data->regmap, reg, data->fifo_mode);
1398         if (ret < 0) {
1399                 dev_err(data->dev, "Error writing reg_fifo_config1\n");
1400                 return ret;
1401         }
1402
1403         if (!data->fifo_mode)
1404                 return 0;
1405
1406         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1407                            data->watermark);
1408         if (ret < 0)
1409                 dev_err(data->dev, "Error writing reg_fifo_config0\n");
1410
1411         return ret;
1412 }
1413
1414 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1415 {
1416         struct bmc150_accel_data *data = iio_priv(indio_dev);
1417
1418         return bmc150_accel_set_power_state(data, true);
1419 }
1420
1421 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1422 {
1423         struct bmc150_accel_data *data = iio_priv(indio_dev);
1424         int ret = 0;
1425
1426         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1427                 return iio_triggered_buffer_postenable(indio_dev);
1428
1429         mutex_lock(&data->mutex);
1430
1431         if (!data->watermark)
1432                 goto out;
1433
1434         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1435                                          true);
1436         if (ret)
1437                 goto out;
1438
1439         data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1440
1441         ret = bmc150_accel_fifo_set_mode(data);
1442         if (ret) {
1443                 data->fifo_mode = 0;
1444                 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1445                                            false);
1446         }
1447
1448 out:
1449         mutex_unlock(&data->mutex);
1450
1451         return ret;
1452 }
1453
1454 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1455 {
1456         struct bmc150_accel_data *data = iio_priv(indio_dev);
1457
1458         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1459                 return iio_triggered_buffer_predisable(indio_dev);
1460
1461         mutex_lock(&data->mutex);
1462
1463         if (!data->fifo_mode)
1464                 goto out;
1465
1466         bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1467         __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1468         data->fifo_mode = 0;
1469         bmc150_accel_fifo_set_mode(data);
1470
1471 out:
1472         mutex_unlock(&data->mutex);
1473
1474         return 0;
1475 }
1476
1477 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1478 {
1479         struct bmc150_accel_data *data = iio_priv(indio_dev);
1480
1481         return bmc150_accel_set_power_state(data, false);
1482 }
1483
1484 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1485         .preenable = bmc150_accel_buffer_preenable,
1486         .postenable = bmc150_accel_buffer_postenable,
1487         .predisable = bmc150_accel_buffer_predisable,
1488         .postdisable = bmc150_accel_buffer_postdisable,
1489 };
1490
1491 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1492 {
1493         int ret, i;
1494         unsigned int val;
1495
1496         /*
1497          * Reset chip to get it in a known good state. A delay of 1.8ms after
1498          * reset is required according to the data sheets of supported chips.
1499          */
1500         regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1501                      BMC150_ACCEL_RESET_VAL);
1502         usleep_range(1800, 2500);
1503
1504         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1505         if (ret < 0) {
1506                 dev_err(data->dev,
1507                         "Error: Reading chip id\n");
1508                 return ret;
1509         }
1510
1511         dev_dbg(data->dev, "Chip Id %x\n", val);
1512         for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1513                 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1514                         data->chip_info = &bmc150_accel_chip_info_tbl[i];
1515                         break;
1516                 }
1517         }
1518
1519         if (!data->chip_info) {
1520                 dev_err(data->dev, "Invalid chip %x\n", val);
1521                 return -ENODEV;
1522         }
1523
1524         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1525         if (ret < 0)
1526                 return ret;
1527
1528         /* Set Bandwidth */
1529         ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1530         if (ret < 0)
1531                 return ret;
1532
1533         /* Set Default Range */
1534         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1535                            BMC150_ACCEL_DEF_RANGE_4G);
1536         if (ret < 0) {
1537                 dev_err(data->dev,
1538                                         "Error writing reg_pmu_range\n");
1539                 return ret;
1540         }
1541
1542         data->range = BMC150_ACCEL_DEF_RANGE_4G;
1543
1544         /* Set default slope duration and thresholds */
1545         data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1546         data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1547         ret = bmc150_accel_update_slope(data);
1548         if (ret < 0)
1549                 return ret;
1550
1551         /* Set default as latched interrupts */
1552         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1553                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1554                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1555         if (ret < 0) {
1556                 dev_err(data->dev,
1557                         "Error writing reg_int_rst_latch\n");
1558                 return ret;
1559         }
1560
1561         return 0;
1562 }
1563
1564 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1565                             const char *name, bool block_supported)
1566 {
1567         struct bmc150_accel_data *data;
1568         struct iio_dev *indio_dev;
1569         int ret;
1570
1571         indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1572         if (!indio_dev)
1573                 return -ENOMEM;
1574
1575         data = iio_priv(indio_dev);
1576         dev_set_drvdata(dev, indio_dev);
1577         data->dev = dev;
1578         data->irq = irq;
1579
1580         data->regmap = regmap;
1581
1582         ret = bmc150_accel_chip_init(data);
1583         if (ret < 0)
1584                 return ret;
1585
1586         mutex_init(&data->mutex);
1587
1588         indio_dev->dev.parent = dev;
1589         indio_dev->channels = data->chip_info->channels;
1590         indio_dev->num_channels = data->chip_info->num_channels;
1591         indio_dev->name = name ? name : data->chip_info->name;
1592         indio_dev->modes = INDIO_DIRECT_MODE;
1593         indio_dev->info = &bmc150_accel_info;
1594
1595         ret = iio_triggered_buffer_setup(indio_dev,
1596                                          &iio_pollfunc_store_time,
1597                                          bmc150_accel_trigger_handler,
1598                                          &bmc150_accel_buffer_ops);
1599         if (ret < 0) {
1600                 dev_err(data->dev, "Failed: iio triggered buffer setup\n");
1601                 return ret;
1602         }
1603
1604         if (data->irq > 0) {
1605                 ret = devm_request_threaded_irq(
1606                                                 data->dev, data->irq,
1607                                                 bmc150_accel_irq_handler,
1608                                                 bmc150_accel_irq_thread_handler,
1609                                                 IRQF_TRIGGER_RISING,
1610                                                 BMC150_ACCEL_IRQ_NAME,
1611                                                 indio_dev);
1612                 if (ret)
1613                         goto err_buffer_cleanup;
1614
1615                 /*
1616                  * Set latched mode interrupt. While certain interrupts are
1617                  * non-latched regardless of this settings (e.g. new data) we
1618                  * want to use latch mode when we can to prevent interrupt
1619                  * flooding.
1620                  */
1621                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1622                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1623                 if (ret < 0) {
1624                         dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1625                         goto err_buffer_cleanup;
1626                 }
1627
1628                 bmc150_accel_interrupts_setup(indio_dev, data);
1629
1630                 ret = bmc150_accel_triggers_setup(indio_dev, data);
1631                 if (ret)
1632                         goto err_buffer_cleanup;
1633
1634                 if (block_supported) {
1635                         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1636                         indio_dev->info = &bmc150_accel_info_fifo;
1637                         indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1638                 }
1639         }
1640
1641         ret = iio_device_register(indio_dev);
1642         if (ret < 0) {
1643                 dev_err(dev, "Unable to register iio device\n");
1644                 goto err_trigger_unregister;
1645         }
1646
1647         ret = pm_runtime_set_active(dev);
1648         if (ret)
1649                 goto err_iio_unregister;
1650
1651         pm_runtime_enable(dev);
1652         pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1653         pm_runtime_use_autosuspend(dev);
1654
1655         return 0;
1656
1657 err_iio_unregister:
1658         iio_device_unregister(indio_dev);
1659 err_trigger_unregister:
1660         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1661 err_buffer_cleanup:
1662         iio_triggered_buffer_cleanup(indio_dev);
1663
1664         return ret;
1665 }
1666 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1667
1668 int bmc150_accel_core_remove(struct device *dev)
1669 {
1670         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1671         struct bmc150_accel_data *data = iio_priv(indio_dev);
1672
1673         pm_runtime_disable(data->dev);
1674         pm_runtime_set_suspended(data->dev);
1675         pm_runtime_put_noidle(data->dev);
1676
1677         iio_device_unregister(indio_dev);
1678
1679         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1680
1681         iio_triggered_buffer_cleanup(indio_dev);
1682
1683         mutex_lock(&data->mutex);
1684         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1685         mutex_unlock(&data->mutex);
1686
1687         return 0;
1688 }
1689 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1690
1691 #ifdef CONFIG_PM_SLEEP
1692 static int bmc150_accel_suspend(struct device *dev)
1693 {
1694         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1695         struct bmc150_accel_data *data = iio_priv(indio_dev);
1696
1697         mutex_lock(&data->mutex);
1698         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1699         mutex_unlock(&data->mutex);
1700
1701         return 0;
1702 }
1703
1704 static int bmc150_accel_resume(struct device *dev)
1705 {
1706         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1707         struct bmc150_accel_data *data = iio_priv(indio_dev);
1708
1709         mutex_lock(&data->mutex);
1710         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1711         bmc150_accel_fifo_set_mode(data);
1712         mutex_unlock(&data->mutex);
1713
1714         return 0;
1715 }
1716 #endif
1717
1718 #ifdef CONFIG_PM
1719 static int bmc150_accel_runtime_suspend(struct device *dev)
1720 {
1721         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1722         struct bmc150_accel_data *data = iio_priv(indio_dev);
1723         int ret;
1724
1725         dev_dbg(data->dev,  __func__);
1726         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1727         if (ret < 0)
1728                 return -EAGAIN;
1729
1730         return 0;
1731 }
1732
1733 static int bmc150_accel_runtime_resume(struct device *dev)
1734 {
1735         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1736         struct bmc150_accel_data *data = iio_priv(indio_dev);
1737         int ret;
1738         int sleep_val;
1739
1740         dev_dbg(data->dev,  __func__);
1741
1742         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1743         if (ret < 0)
1744                 return ret;
1745         ret = bmc150_accel_fifo_set_mode(data);
1746         if (ret < 0)
1747                 return ret;
1748
1749         sleep_val = bmc150_accel_get_startup_times(data);
1750         if (sleep_val < 20)
1751                 usleep_range(sleep_val * 1000, 20000);
1752         else
1753                 msleep_interruptible(sleep_val);
1754
1755         return 0;
1756 }
1757 #endif
1758
1759 const struct dev_pm_ops bmc150_accel_pm_ops = {
1760         SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1761         SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1762                            bmc150_accel_runtime_resume, NULL)
1763 };
1764 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1765
1766 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1767 MODULE_LICENSE("GPL v2");
1768 MODULE_DESCRIPTION("BMC150 accelerometer driver");