2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
10 * Copyright (c) 2014, Intel Corporation.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
28 #include <linux/gpio/consumer.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/iio/iio.h>
32 #include <linux/iio/sysfs.h>
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/events.h>
35 #include <linux/iio/trigger.h>
36 #include <linux/iio/trigger_consumer.h>
37 #include <linux/iio/triggered_buffer.h>
38 #include <linux/regmap.h>
40 #include "bmc150-accel.h"
42 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
43 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
45 #define BMC150_ACCEL_REG_CHIP_ID 0x00
47 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
48 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
49 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
50 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
51 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
52 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
54 #define BMC150_ACCEL_REG_PMU_LPW 0x11
55 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
56 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
58 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
60 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
62 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
63 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
64 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
65 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
67 /* Default BW: 125Hz */
68 #define BMC150_ACCEL_REG_PMU_BW 0x10
69 #define BMC150_ACCEL_DEF_BW 125
71 #define BMC150_ACCEL_REG_RESET 0x14
72 #define BMC150_ACCEL_RESET_VAL 0xB6
74 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
75 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
77 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
78 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
79 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
80 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
82 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
83 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
84 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
85 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
87 #define BMC150_ACCEL_REG_INT_EN_0 0x16
88 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
90 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
92 #define BMC150_ACCEL_REG_INT_EN_1 0x17
93 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
94 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
95 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
97 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
98 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
100 #define BMC150_ACCEL_REG_INT_5 0x27
101 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
103 #define BMC150_ACCEL_REG_INT_6 0x28
104 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
106 /* Slope duration in terms of number of samples */
107 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
108 /* in terms of multiples of g's/LSB, based on range */
109 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
111 #define BMC150_ACCEL_REG_XOUT_L 0x02
113 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
115 /* Sleep Duration values */
116 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
117 #define BMC150_ACCEL_SLEEP_1_MS 0x06
118 #define BMC150_ACCEL_SLEEP_2_MS 0x07
119 #define BMC150_ACCEL_SLEEP_4_MS 0x08
120 #define BMC150_ACCEL_SLEEP_6_MS 0x09
121 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
122 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
123 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
124 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
125 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
126 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
128 #define BMC150_ACCEL_REG_TEMP 0x08
129 #define BMC150_ACCEL_TEMP_CENTER_VAL 23
131 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
132 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
134 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
135 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
136 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
137 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
138 #define BMC150_ACCEL_FIFO_LENGTH 32
140 enum bmc150_accel_axis {
146 enum bmc150_power_modes {
147 BMC150_ACCEL_SLEEP_MODE_NORMAL,
148 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
149 BMC150_ACCEL_SLEEP_MODE_LPM,
150 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
153 struct bmc150_scale_info {
158 struct bmc150_accel_chip_info {
161 const struct iio_chan_spec *channels;
163 const struct bmc150_scale_info scale_table[4];
166 struct bmc150_accel_interrupt {
167 const struct bmc150_accel_interrupt_info *info;
171 struct bmc150_accel_trigger {
172 struct bmc150_accel_data *data;
173 struct iio_trigger *indio_trig;
174 int (*setup)(struct bmc150_accel_trigger *t, bool state);
179 enum bmc150_accel_interrupt_id {
180 BMC150_ACCEL_INT_DATA_READY,
181 BMC150_ACCEL_INT_ANY_MOTION,
182 BMC150_ACCEL_INT_WATERMARK,
183 BMC150_ACCEL_INTERRUPTS,
186 enum bmc150_accel_trigger_id {
187 BMC150_ACCEL_TRIGGER_DATA_READY,
188 BMC150_ACCEL_TRIGGER_ANY_MOTION,
189 BMC150_ACCEL_TRIGGERS,
192 struct bmc150_accel_data {
193 struct regmap *regmap;
196 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
197 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
199 u8 fifo_mode, watermark;
202 * Ensure there is sufficient space and correct alignment for
203 * the timestamp if enabled
214 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
215 const struct bmc150_accel_chip_info *chip_info;
218 static const struct {
222 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
231 static const struct {
234 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
243 static const struct {
246 } bmc150_accel_sleep_value_table[] = { {0, 0},
247 {500, BMC150_ACCEL_SLEEP_500_MICRO},
248 {1000, BMC150_ACCEL_SLEEP_1_MS},
249 {2000, BMC150_ACCEL_SLEEP_2_MS},
250 {4000, BMC150_ACCEL_SLEEP_4_MS},
251 {6000, BMC150_ACCEL_SLEEP_6_MS},
252 {10000, BMC150_ACCEL_SLEEP_10_MS},
253 {25000, BMC150_ACCEL_SLEEP_25_MS},
254 {50000, BMC150_ACCEL_SLEEP_50_MS},
255 {100000, BMC150_ACCEL_SLEEP_100_MS},
256 {500000, BMC150_ACCEL_SLEEP_500_MS},
257 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
259 static const struct regmap_config bmc150_i2c_regmap_conf = {
262 .max_register = 0x3f,
265 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
266 enum bmc150_power_modes mode,
275 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
277 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
280 bmc150_accel_sleep_value_table[i].reg_value;
289 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
290 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
292 dev_dbg(data->dev, "Set Mode bits %x\n", lpw_bits);
294 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
296 dev_err(data->dev, "Error writing reg_pmu_lpw\n");
303 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
309 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
310 if (bmc150_accel_samp_freq_table[i].val == val &&
311 bmc150_accel_samp_freq_table[i].val2 == val2) {
312 ret = regmap_write(data->regmap,
313 BMC150_ACCEL_REG_PMU_BW,
314 bmc150_accel_samp_freq_table[i].bw_bits);
319 bmc150_accel_samp_freq_table[i].bw_bits;
327 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
331 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
334 dev_err(data->dev, "Error writing reg_int_6\n");
338 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
339 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
341 dev_err(data->dev, "Error updating reg_int_5\n");
345 dev_dbg(data->dev, "%s: %x %x\n", __func__, data->slope_thres,
351 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
355 return bmc150_accel_update_slope(t->data);
360 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
365 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
366 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
367 *val = bmc150_accel_samp_freq_table[i].val;
368 *val2 = bmc150_accel_samp_freq_table[i].val2;
369 return IIO_VAL_INT_PLUS_MICRO;
377 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
381 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
382 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
383 return bmc150_accel_sample_upd_time[i].msec;
386 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
389 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
394 ret = pm_runtime_get_sync(data->dev);
396 pm_runtime_mark_last_busy(data->dev);
397 ret = pm_runtime_put_autosuspend(data->dev);
402 "Failed: bmc150_accel_set_power_state for %d\n", on);
404 pm_runtime_put_noidle(data->dev);
412 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
418 static const struct bmc150_accel_interrupt_info {
423 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
424 { /* data ready interrupt */
425 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
426 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
427 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
428 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
430 { /* motion interrupt */
431 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
432 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
433 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
434 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
435 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
436 BMC150_ACCEL_INT_EN_BIT_SLP_Z
438 { /* fifo watermark interrupt */
439 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
440 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
441 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
442 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
446 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
447 struct bmc150_accel_data *data)
451 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
452 data->interrupts[i].info = &bmc150_accel_interrupts[i];
455 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
458 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
459 const struct bmc150_accel_interrupt_info *info = intr->info;
463 if (atomic_inc_return(&intr->users) > 1)
466 if (atomic_dec_return(&intr->users) > 0)
471 * We will expect the enable and disable to do operation in reverse
472 * order. This will happen here anyway, as our resume operation uses
473 * sync mode runtime pm calls. The suspend operation will be delayed
474 * by autosuspend delay.
475 * So the disable operation will still happen in reverse order of
476 * enable operation. When runtime pm is disabled the mode is always on,
477 * so sequence doesn't matter.
479 ret = bmc150_accel_set_power_state(data, state);
483 /* map the interrupt to the appropriate pins */
484 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
485 (state ? info->map_bitmask : 0));
487 dev_err(data->dev, "Error updating reg_int_map\n");
488 goto out_fix_power_state;
491 /* enable/disable the interrupt */
492 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
493 (state ? info->en_bitmask : 0));
495 dev_err(data->dev, "Error updating reg_int_en\n");
496 goto out_fix_power_state;
502 bmc150_accel_set_power_state(data, false);
506 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
510 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
511 if (data->chip_info->scale_table[i].scale == val) {
512 ret = regmap_write(data->regmap,
513 BMC150_ACCEL_REG_PMU_RANGE,
514 data->chip_info->scale_table[i].reg_range);
517 "Error writing pmu_range\n");
521 data->range = data->chip_info->scale_table[i].reg_range;
529 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
534 mutex_lock(&data->mutex);
536 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
538 dev_err(data->dev, "Error reading reg_temp\n");
539 mutex_unlock(&data->mutex);
542 *val = sign_extend32(value, 7);
544 mutex_unlock(&data->mutex);
549 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
550 struct iio_chan_spec const *chan,
554 int axis = chan->scan_index;
557 mutex_lock(&data->mutex);
558 ret = bmc150_accel_set_power_state(data, true);
560 mutex_unlock(&data->mutex);
564 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
565 &raw_val, sizeof(raw_val));
567 dev_err(data->dev, "Error reading axis %d\n", axis);
568 bmc150_accel_set_power_state(data, false);
569 mutex_unlock(&data->mutex);
572 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
573 chan->scan_type.realbits - 1);
574 ret = bmc150_accel_set_power_state(data, false);
575 mutex_unlock(&data->mutex);
582 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
583 struct iio_chan_spec const *chan,
584 int *val, int *val2, long mask)
586 struct bmc150_accel_data *data = iio_priv(indio_dev);
590 case IIO_CHAN_INFO_RAW:
591 switch (chan->type) {
593 return bmc150_accel_get_temp(data, val);
595 if (iio_buffer_enabled(indio_dev))
598 return bmc150_accel_get_axis(data, chan, val);
602 case IIO_CHAN_INFO_OFFSET:
603 if (chan->type == IIO_TEMP) {
604 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
609 case IIO_CHAN_INFO_SCALE:
611 switch (chan->type) {
614 return IIO_VAL_INT_PLUS_MICRO;
618 const struct bmc150_scale_info *si;
619 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
621 for (i = 0; i < st_size; ++i) {
622 si = &data->chip_info->scale_table[i];
623 if (si->reg_range == data->range) {
625 return IIO_VAL_INT_PLUS_MICRO;
633 case IIO_CHAN_INFO_SAMP_FREQ:
634 mutex_lock(&data->mutex);
635 ret = bmc150_accel_get_bw(data, val, val2);
636 mutex_unlock(&data->mutex);
643 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
644 struct iio_chan_spec const *chan,
645 int val, int val2, long mask)
647 struct bmc150_accel_data *data = iio_priv(indio_dev);
651 case IIO_CHAN_INFO_SAMP_FREQ:
652 mutex_lock(&data->mutex);
653 ret = bmc150_accel_set_bw(data, val, val2);
654 mutex_unlock(&data->mutex);
656 case IIO_CHAN_INFO_SCALE:
660 mutex_lock(&data->mutex);
661 ret = bmc150_accel_set_scale(data, val2);
662 mutex_unlock(&data->mutex);
671 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
672 const struct iio_chan_spec *chan,
673 enum iio_event_type type,
674 enum iio_event_direction dir,
675 enum iio_event_info info,
678 struct bmc150_accel_data *data = iio_priv(indio_dev);
682 case IIO_EV_INFO_VALUE:
683 *val = data->slope_thres;
685 case IIO_EV_INFO_PERIOD:
686 *val = data->slope_dur;
695 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
696 const struct iio_chan_spec *chan,
697 enum iio_event_type type,
698 enum iio_event_direction dir,
699 enum iio_event_info info,
702 struct bmc150_accel_data *data = iio_priv(indio_dev);
704 if (data->ev_enable_state)
708 case IIO_EV_INFO_VALUE:
709 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
711 case IIO_EV_INFO_PERIOD:
712 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
721 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
722 const struct iio_chan_spec *chan,
723 enum iio_event_type type,
724 enum iio_event_direction dir)
726 struct bmc150_accel_data *data = iio_priv(indio_dev);
728 return data->ev_enable_state;
731 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
732 const struct iio_chan_spec *chan,
733 enum iio_event_type type,
734 enum iio_event_direction dir,
737 struct bmc150_accel_data *data = iio_priv(indio_dev);
740 if (state == data->ev_enable_state)
743 mutex_lock(&data->mutex);
745 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
748 mutex_unlock(&data->mutex);
752 data->ev_enable_state = state;
753 mutex_unlock(&data->mutex);
758 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
759 struct iio_trigger *trig)
761 struct bmc150_accel_data *data = iio_priv(indio_dev);
764 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
765 if (data->triggers[i].indio_trig == trig)
772 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
773 struct device_attribute *attr,
776 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
777 struct bmc150_accel_data *data = iio_priv(indio_dev);
780 mutex_lock(&data->mutex);
781 wm = data->watermark;
782 mutex_unlock(&data->mutex);
784 return sprintf(buf, "%d\n", wm);
787 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
788 struct device_attribute *attr,
791 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
792 struct bmc150_accel_data *data = iio_priv(indio_dev);
795 mutex_lock(&data->mutex);
796 state = data->fifo_mode;
797 mutex_unlock(&data->mutex);
799 return sprintf(buf, "%d\n", state);
802 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
803 static IIO_CONST_ATTR(hwfifo_watermark_max,
804 __stringify(BMC150_ACCEL_FIFO_LENGTH));
805 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
806 bmc150_accel_get_fifo_state, NULL, 0);
807 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
808 bmc150_accel_get_fifo_watermark, NULL, 0);
810 static const struct attribute *bmc150_accel_fifo_attributes[] = {
811 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
812 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
813 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
814 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
818 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
820 struct bmc150_accel_data *data = iio_priv(indio_dev);
822 if (val > BMC150_ACCEL_FIFO_LENGTH)
823 val = BMC150_ACCEL_FIFO_LENGTH;
825 mutex_lock(&data->mutex);
826 data->watermark = val;
827 mutex_unlock(&data->mutex);
833 * We must read at least one full frame in one burst, otherwise the rest of the
834 * frame data is discarded.
836 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
837 char *buffer, int samples)
839 int sample_length = 3 * 2;
841 int total_length = samples * sample_length;
843 size_t step = regmap_get_raw_read_max(data->regmap);
845 if (!step || step > total_length)
847 else if (step < total_length)
848 step = sample_length;
851 * Seems we have a bus with size limitation so we have to execute
854 for (i = 0; i < total_length; i += step) {
855 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
862 dev_err(data->dev, "Error transferring data from fifo in single steps of %zu\n",
868 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
869 unsigned samples, bool irq)
871 struct bmc150_accel_data *data = iio_priv(indio_dev);
874 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
876 uint64_t sample_period;
879 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
881 dev_err(data->dev, "Error reading reg_fifo_status\n");
891 * If we getting called from IRQ handler we know the stored timestamp is
892 * fairly accurate for the last stored sample. Otherwise, if we are
893 * called as a result of a read operation from userspace and hence
894 * before the watermark interrupt was triggered, take a timestamp
895 * now. We can fall anywhere in between two samples so the error in this
896 * case is at most one sample period.
899 data->old_timestamp = data->timestamp;
900 data->timestamp = iio_get_time_ns();
904 * Approximate timestamps for each of the sample based on the sampling
905 * frequency, timestamp for last sample and number of samples.
907 * Note that we can't use the current bandwidth settings to compute the
908 * sample period because the sample rate varies with the device
909 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
910 * small variation adds when we store a large number of samples and
911 * creates significant jitter between the last and first samples in
912 * different batches (e.g. 32ms vs 21ms).
914 * To avoid this issue we compute the actual sample period ourselves
915 * based on the timestamp delta between the last two flush operations.
917 sample_period = (data->timestamp - data->old_timestamp);
918 do_div(sample_period, count);
919 tstamp = data->timestamp - (count - 1) * sample_period;
921 if (samples && count > samples)
924 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
929 * Ideally we want the IIO core to handle the demux when running in fifo
930 * mode but not when running in triggered buffer mode. Unfortunately
931 * this does not seem to be possible, so stick with driver demux for
934 for (i = 0; i < count; i++) {
938 for_each_set_bit(bit, indio_dev->active_scan_mask,
939 indio_dev->masklength)
940 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
941 sizeof(data->scan.channels[0]));
943 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
946 tstamp += sample_period;
952 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
954 struct bmc150_accel_data *data = iio_priv(indio_dev);
957 mutex_lock(&data->mutex);
958 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
959 mutex_unlock(&data->mutex);
964 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
965 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
967 static struct attribute *bmc150_accel_attributes[] = {
968 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
972 static const struct attribute_group bmc150_accel_attrs_group = {
973 .attrs = bmc150_accel_attributes,
976 static const struct iio_event_spec bmc150_accel_event = {
977 .type = IIO_EV_TYPE_ROC,
978 .dir = IIO_EV_DIR_EITHER,
979 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
980 BIT(IIO_EV_INFO_ENABLE) |
981 BIT(IIO_EV_INFO_PERIOD)
984 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
987 .channel2 = IIO_MOD_##_axis, \
988 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
989 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
990 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
991 .scan_index = AXIS_##_axis, \
994 .realbits = (bits), \
996 .shift = 16 - (bits), \
997 .endianness = IIO_LE, \
999 .event_spec = &bmc150_accel_event, \
1000 .num_event_specs = 1 \
1003 #define BMC150_ACCEL_CHANNELS(bits) { \
1006 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1007 BIT(IIO_CHAN_INFO_SCALE) | \
1008 BIT(IIO_CHAN_INFO_OFFSET), \
1011 BMC150_ACCEL_CHANNEL(X, bits), \
1012 BMC150_ACCEL_CHANNEL(Y, bits), \
1013 BMC150_ACCEL_CHANNEL(Z, bits), \
1014 IIO_CHAN_SOFT_TIMESTAMP(3), \
1017 static const struct iio_chan_spec bma222e_accel_channels[] =
1018 BMC150_ACCEL_CHANNELS(8);
1019 static const struct iio_chan_spec bma250e_accel_channels[] =
1020 BMC150_ACCEL_CHANNELS(10);
1021 static const struct iio_chan_spec bmc150_accel_channels[] =
1022 BMC150_ACCEL_CHANNELS(12);
1023 static const struct iio_chan_spec bma280_accel_channels[] =
1024 BMC150_ACCEL_CHANNELS(14);
1026 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1030 .channels = bmc150_accel_channels,
1031 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1032 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1033 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1034 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1035 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1040 .channels = bmc150_accel_channels,
1041 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1042 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1043 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1044 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1045 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1050 .channels = bmc150_accel_channels,
1051 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1052 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1053 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1054 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1055 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1060 .channels = bma250e_accel_channels,
1061 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1062 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1063 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1064 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1065 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1070 .channels = bma222e_accel_channels,
1071 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1072 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1073 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1074 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1075 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1080 .channels = bma280_accel_channels,
1081 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1082 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1083 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1084 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1085 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1089 static const struct iio_info bmc150_accel_info = {
1090 .attrs = &bmc150_accel_attrs_group,
1091 .read_raw = bmc150_accel_read_raw,
1092 .write_raw = bmc150_accel_write_raw,
1093 .read_event_value = bmc150_accel_read_event,
1094 .write_event_value = bmc150_accel_write_event,
1095 .write_event_config = bmc150_accel_write_event_config,
1096 .read_event_config = bmc150_accel_read_event_config,
1097 .driver_module = THIS_MODULE,
1100 static const struct iio_info bmc150_accel_info_fifo = {
1101 .attrs = &bmc150_accel_attrs_group,
1102 .read_raw = bmc150_accel_read_raw,
1103 .write_raw = bmc150_accel_write_raw,
1104 .read_event_value = bmc150_accel_read_event,
1105 .write_event_value = bmc150_accel_write_event,
1106 .write_event_config = bmc150_accel_write_event_config,
1107 .read_event_config = bmc150_accel_read_event_config,
1108 .validate_trigger = bmc150_accel_validate_trigger,
1109 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1110 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1111 .driver_module = THIS_MODULE,
1114 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1116 struct iio_poll_func *pf = p;
1117 struct iio_dev *indio_dev = pf->indio_dev;
1118 struct bmc150_accel_data *data = iio_priv(indio_dev);
1119 int bit, ret, i = 0;
1120 unsigned int raw_val;
1122 mutex_lock(&data->mutex);
1123 for_each_set_bit(bit, indio_dev->active_scan_mask,
1124 indio_dev->masklength) {
1125 ret = regmap_bulk_read(data->regmap,
1126 BMC150_ACCEL_AXIS_TO_REG(bit), &raw_val,
1129 mutex_unlock(&data->mutex);
1132 data->buffer[i++] = raw_val;
1134 mutex_unlock(&data->mutex);
1136 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1139 iio_trigger_notify_done(indio_dev->trig);
1144 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1146 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1147 struct bmc150_accel_data *data = t->data;
1150 /* new data interrupts don't need ack */
1151 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1154 mutex_lock(&data->mutex);
1155 /* clear any latched interrupt */
1156 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1157 BMC150_ACCEL_INT_MODE_LATCH_INT |
1158 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1159 mutex_unlock(&data->mutex);
1162 "Error writing reg_int_rst_latch\n");
1169 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1172 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1173 struct bmc150_accel_data *data = t->data;
1176 mutex_lock(&data->mutex);
1178 if (t->enabled == state) {
1179 mutex_unlock(&data->mutex);
1184 ret = t->setup(t, state);
1186 mutex_unlock(&data->mutex);
1191 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1193 mutex_unlock(&data->mutex);
1199 mutex_unlock(&data->mutex);
1204 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1205 .set_trigger_state = bmc150_accel_trigger_set_state,
1206 .try_reenable = bmc150_accel_trig_try_reen,
1207 .owner = THIS_MODULE,
1210 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1212 struct bmc150_accel_data *data = iio_priv(indio_dev);
1217 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1219 dev_err(data->dev, "Error reading reg_int_status_2\n");
1223 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1224 dir = IIO_EV_DIR_FALLING;
1226 dir = IIO_EV_DIR_RISING;
1228 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1229 iio_push_event(indio_dev,
1230 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1237 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1238 iio_push_event(indio_dev,
1239 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1246 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1247 iio_push_event(indio_dev,
1248 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1258 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1260 struct iio_dev *indio_dev = private;
1261 struct bmc150_accel_data *data = iio_priv(indio_dev);
1265 mutex_lock(&data->mutex);
1267 if (data->fifo_mode) {
1268 ret = __bmc150_accel_fifo_flush(indio_dev,
1269 BMC150_ACCEL_FIFO_LENGTH, true);
1274 if (data->ev_enable_state) {
1275 ret = bmc150_accel_handle_roc_event(indio_dev);
1281 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1282 BMC150_ACCEL_INT_MODE_LATCH_INT |
1283 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1285 dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1292 mutex_unlock(&data->mutex);
1297 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1299 struct iio_dev *indio_dev = private;
1300 struct bmc150_accel_data *data = iio_priv(indio_dev);
1304 data->old_timestamp = data->timestamp;
1305 data->timestamp = iio_get_time_ns();
1307 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1308 if (data->triggers[i].enabled) {
1309 iio_trigger_poll(data->triggers[i].indio_trig);
1315 if (data->ev_enable_state || data->fifo_mode)
1316 return IRQ_WAKE_THREAD;
1324 static const struct {
1327 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1328 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1335 .name = "%s-any-motion-dev%d",
1336 .setup = bmc150_accel_any_motion_setup,
1340 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1345 for (i = from; i >= 0; i--) {
1346 if (data->triggers[i].indio_trig) {
1347 iio_trigger_unregister(data->triggers[i].indio_trig);
1348 data->triggers[i].indio_trig = NULL;
1353 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1354 struct bmc150_accel_data *data)
1358 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1359 struct bmc150_accel_trigger *t = &data->triggers[i];
1361 t->indio_trig = devm_iio_trigger_alloc(data->dev,
1362 bmc150_accel_triggers[i].name,
1365 if (!t->indio_trig) {
1370 t->indio_trig->dev.parent = data->dev;
1371 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1372 t->intr = bmc150_accel_triggers[i].intr;
1374 t->setup = bmc150_accel_triggers[i].setup;
1375 iio_trigger_set_drvdata(t->indio_trig, t);
1377 ret = iio_trigger_register(t->indio_trig);
1383 bmc150_accel_unregister_triggers(data, i - 1);
1388 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1389 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1390 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1392 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1394 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1397 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1399 dev_err(data->dev, "Error writing reg_fifo_config1\n");
1403 if (!data->fifo_mode)
1406 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1409 dev_err(data->dev, "Error writing reg_fifo_config0\n");
1414 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1416 struct bmc150_accel_data *data = iio_priv(indio_dev);
1418 return bmc150_accel_set_power_state(data, true);
1421 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1423 struct bmc150_accel_data *data = iio_priv(indio_dev);
1426 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1427 return iio_triggered_buffer_postenable(indio_dev);
1429 mutex_lock(&data->mutex);
1431 if (!data->watermark)
1434 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1439 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1441 ret = bmc150_accel_fifo_set_mode(data);
1443 data->fifo_mode = 0;
1444 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1449 mutex_unlock(&data->mutex);
1454 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1456 struct bmc150_accel_data *data = iio_priv(indio_dev);
1458 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1459 return iio_triggered_buffer_predisable(indio_dev);
1461 mutex_lock(&data->mutex);
1463 if (!data->fifo_mode)
1466 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1467 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1468 data->fifo_mode = 0;
1469 bmc150_accel_fifo_set_mode(data);
1472 mutex_unlock(&data->mutex);
1477 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1479 struct bmc150_accel_data *data = iio_priv(indio_dev);
1481 return bmc150_accel_set_power_state(data, false);
1484 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1485 .preenable = bmc150_accel_buffer_preenable,
1486 .postenable = bmc150_accel_buffer_postenable,
1487 .predisable = bmc150_accel_buffer_predisable,
1488 .postdisable = bmc150_accel_buffer_postdisable,
1491 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1497 * Reset chip to get it in a known good state. A delay of 1.8ms after
1498 * reset is required according to the data sheets of supported chips.
1500 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1501 BMC150_ACCEL_RESET_VAL);
1502 usleep_range(1800, 2500);
1504 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1507 "Error: Reading chip id\n");
1511 dev_dbg(data->dev, "Chip Id %x\n", val);
1512 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1513 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1514 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1519 if (!data->chip_info) {
1520 dev_err(data->dev, "Invalid chip %x\n", val);
1524 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1529 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1533 /* Set Default Range */
1534 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1535 BMC150_ACCEL_DEF_RANGE_4G);
1538 "Error writing reg_pmu_range\n");
1542 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1544 /* Set default slope duration and thresholds */
1545 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1546 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1547 ret = bmc150_accel_update_slope(data);
1551 /* Set default as latched interrupts */
1552 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1553 BMC150_ACCEL_INT_MODE_LATCH_INT |
1554 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1557 "Error writing reg_int_rst_latch\n");
1564 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1565 const char *name, bool block_supported)
1567 struct bmc150_accel_data *data;
1568 struct iio_dev *indio_dev;
1571 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1575 data = iio_priv(indio_dev);
1576 dev_set_drvdata(dev, indio_dev);
1580 data->regmap = regmap;
1582 ret = bmc150_accel_chip_init(data);
1586 mutex_init(&data->mutex);
1588 indio_dev->dev.parent = dev;
1589 indio_dev->channels = data->chip_info->channels;
1590 indio_dev->num_channels = data->chip_info->num_channels;
1591 indio_dev->name = name ? name : data->chip_info->name;
1592 indio_dev->modes = INDIO_DIRECT_MODE;
1593 indio_dev->info = &bmc150_accel_info;
1595 ret = iio_triggered_buffer_setup(indio_dev,
1596 &iio_pollfunc_store_time,
1597 bmc150_accel_trigger_handler,
1598 &bmc150_accel_buffer_ops);
1600 dev_err(data->dev, "Failed: iio triggered buffer setup\n");
1604 if (data->irq > 0) {
1605 ret = devm_request_threaded_irq(
1606 data->dev, data->irq,
1607 bmc150_accel_irq_handler,
1608 bmc150_accel_irq_thread_handler,
1609 IRQF_TRIGGER_RISING,
1610 BMC150_ACCEL_IRQ_NAME,
1613 goto err_buffer_cleanup;
1616 * Set latched mode interrupt. While certain interrupts are
1617 * non-latched regardless of this settings (e.g. new data) we
1618 * want to use latch mode when we can to prevent interrupt
1621 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1622 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1624 dev_err(data->dev, "Error writing reg_int_rst_latch\n");
1625 goto err_buffer_cleanup;
1628 bmc150_accel_interrupts_setup(indio_dev, data);
1630 ret = bmc150_accel_triggers_setup(indio_dev, data);
1632 goto err_buffer_cleanup;
1634 if (block_supported) {
1635 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1636 indio_dev->info = &bmc150_accel_info_fifo;
1637 indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1641 ret = iio_device_register(indio_dev);
1643 dev_err(dev, "Unable to register iio device\n");
1644 goto err_trigger_unregister;
1647 ret = pm_runtime_set_active(dev);
1649 goto err_iio_unregister;
1651 pm_runtime_enable(dev);
1652 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1653 pm_runtime_use_autosuspend(dev);
1658 iio_device_unregister(indio_dev);
1659 err_trigger_unregister:
1660 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1662 iio_triggered_buffer_cleanup(indio_dev);
1666 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1668 int bmc150_accel_core_remove(struct device *dev)
1670 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1671 struct bmc150_accel_data *data = iio_priv(indio_dev);
1673 pm_runtime_disable(data->dev);
1674 pm_runtime_set_suspended(data->dev);
1675 pm_runtime_put_noidle(data->dev);
1677 iio_device_unregister(indio_dev);
1679 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1681 iio_triggered_buffer_cleanup(indio_dev);
1683 mutex_lock(&data->mutex);
1684 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1685 mutex_unlock(&data->mutex);
1689 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1691 #ifdef CONFIG_PM_SLEEP
1692 static int bmc150_accel_suspend(struct device *dev)
1694 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1695 struct bmc150_accel_data *data = iio_priv(indio_dev);
1697 mutex_lock(&data->mutex);
1698 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1699 mutex_unlock(&data->mutex);
1704 static int bmc150_accel_resume(struct device *dev)
1706 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1707 struct bmc150_accel_data *data = iio_priv(indio_dev);
1709 mutex_lock(&data->mutex);
1710 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1711 bmc150_accel_fifo_set_mode(data);
1712 mutex_unlock(&data->mutex);
1719 static int bmc150_accel_runtime_suspend(struct device *dev)
1721 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1722 struct bmc150_accel_data *data = iio_priv(indio_dev);
1725 dev_dbg(data->dev, __func__);
1726 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1733 static int bmc150_accel_runtime_resume(struct device *dev)
1735 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1736 struct bmc150_accel_data *data = iio_priv(indio_dev);
1740 dev_dbg(data->dev, __func__);
1742 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1745 ret = bmc150_accel_fifo_set_mode(data);
1749 sleep_val = bmc150_accel_get_startup_times(data);
1751 usleep_range(sleep_val * 1000, 20000);
1753 msleep_interruptible(sleep_val);
1759 const struct dev_pm_ops bmc150_accel_pm_ops = {
1760 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1761 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1762 bmc150_accel_runtime_resume, NULL)
1764 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1766 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1767 MODULE_LICENSE("GPL v2");
1768 MODULE_DESCRIPTION("BMC150 accelerometer driver");