drivers/iio/accel/bmc150-accel-core.c

   1 /*
   2  * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
   3  *  - BMC150
   4  *  - BMI055
   5  *  - BMA255
   6  *  - BMA250E
   7  *  - BMA222E
   8  *  - BMA280
   9  *
  10  * Copyright (c) 2014, Intel Corporation.
  11  *
  12  * This program is free software; you can redistribute it and/or modify it
  13  * under the terms and conditions of the GNU General Public License,
  14  * version 2, as published by the Free Software Foundation.
  15  *
  16  * This program is distributed in the hope it will be useful, but WITHOUT
  17  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  * more details.
  20  */
  21
  22 #include <linux/module.h>
  23 #include <linux/i2c.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/delay.h>
  26 #include <linux/slab.h>
  27 #include <linux/acpi.h>
  28 #include <linux/pm.h>
  29 #include <linux/pm_runtime.h>
  30 #include <linux/iio/iio.h>
  31 #include <linux/iio/sysfs.h>
  32 #include <linux/iio/buffer.h>
  33 #include <linux/iio/events.h>
  34 #include <linux/iio/trigger.h>
  35 #include <linux/iio/trigger_consumer.h>
  36 #include <linux/iio/triggered_buffer.h>
  37 #include <linux/regmap.h>
  38
  39 #include "bmc150-accel.h"
  40
  41 #define BMC150_ACCEL_DRV_NAME                   "bmc150_accel"
  42 #define BMC150_ACCEL_IRQ_NAME                   "bmc150_accel_event"
  43
  44 #define BMC150_ACCEL_REG_CHIP_ID                0x00
  45
  46 #define BMC150_ACCEL_REG_INT_STATUS_2           0x0B
  47 #define BMC150_ACCEL_ANY_MOTION_MASK            0x07
  48 #define BMC150_ACCEL_ANY_MOTION_BIT_X           BIT(0)
  49 #define BMC150_ACCEL_ANY_MOTION_BIT_Y           BIT(1)
  50 #define BMC150_ACCEL_ANY_MOTION_BIT_Z           BIT(2)
  51 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN        BIT(3)
  52
  53 #define BMC150_ACCEL_REG_PMU_LPW                0x11
  54 #define BMC150_ACCEL_PMU_MODE_MASK              0xE0
  55 #define BMC150_ACCEL_PMU_MODE_SHIFT             5
  56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK     0x17
  57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT    1
  58
  59 #define BMC150_ACCEL_REG_PMU_RANGE              0x0F
  60
  61 #define BMC150_ACCEL_DEF_RANGE_2G               0x03
  62 #define BMC150_ACCEL_DEF_RANGE_4G               0x05
  63 #define BMC150_ACCEL_DEF_RANGE_8G               0x08
  64 #define BMC150_ACCEL_DEF_RANGE_16G              0x0C
  65
  66 /* Default BW: 125Hz */
  67 #define BMC150_ACCEL_REG_PMU_BW         0x10
  68 #define BMC150_ACCEL_DEF_BW                     125
  69
  70 #define BMC150_ACCEL_REG_RESET                  0x14
  71 #define BMC150_ACCEL_RESET_VAL                  0xB6
  72
  73 #define BMC150_ACCEL_REG_INT_MAP_0              0x19
  74 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE        BIT(2)
  75
  76 #define BMC150_ACCEL_REG_INT_MAP_1              0x1A
  77 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA         BIT(0)
  78 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM          BIT(1)
  79 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL        BIT(2)
  80
  81 #define BMC150_ACCEL_REG_INT_RST_LATCH          0x21
  82 #define BMC150_ACCEL_INT_MODE_LATCH_RESET       0x80
  83 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
  84 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT     0x00
  85
  86 #define BMC150_ACCEL_REG_INT_EN_0               0x16
  87 #define BMC150_ACCEL_INT_EN_BIT_SLP_X           BIT(0)
  88 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y           BIT(1)
  89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z           BIT(2)
  90
  91 #define BMC150_ACCEL_REG_INT_EN_1               0x17
  92 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN         BIT(4)
  93 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN        BIT(5)
  94 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN          BIT(6)
  95
  96 #define BMC150_ACCEL_REG_INT_OUT_CTRL           0x20
  97 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL      BIT(0)
  98
  99 #define BMC150_ACCEL_REG_INT_5                  0x27
 100 #define BMC150_ACCEL_SLOPE_DUR_MASK             0x03
 101
 102 #define BMC150_ACCEL_REG_INT_6                  0x28
 103 #define BMC150_ACCEL_SLOPE_THRES_MASK           0xFF
 104
 105 /* Slope duration in terms of number of samples */
 106 #define BMC150_ACCEL_DEF_SLOPE_DURATION         1
 107 /* in terms of multiples of g's/LSB, based on range */
 108 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD        1
 109
 110 #define BMC150_ACCEL_REG_XOUT_L         0x02
 111
 112 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS        100
 113
 114 /* Sleep Duration values */
 115 #define BMC150_ACCEL_SLEEP_500_MICRO            0x05
 116 #define BMC150_ACCEL_SLEEP_1_MS         0x06
 117 #define BMC150_ACCEL_SLEEP_2_MS         0x07
 118 #define BMC150_ACCEL_SLEEP_4_MS         0x08
 119 #define BMC150_ACCEL_SLEEP_6_MS         0x09
 120 #define BMC150_ACCEL_SLEEP_10_MS                0x0A
 121 #define BMC150_ACCEL_SLEEP_25_MS                0x0B
 122 #define BMC150_ACCEL_SLEEP_50_MS                0x0C
 123 #define BMC150_ACCEL_SLEEP_100_MS               0x0D
 124 #define BMC150_ACCEL_SLEEP_500_MS               0x0E
 125 #define BMC150_ACCEL_SLEEP_1_SEC                0x0F
 126
 127 #define BMC150_ACCEL_REG_TEMP                   0x08
 128 #define BMC150_ACCEL_TEMP_CENTER_VAL            23
 129
 130 #define BMC150_ACCEL_AXIS_TO_REG(axis)  (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
 131 #define BMC150_AUTO_SUSPEND_DELAY_MS            2000
 132
 133 #define BMC150_ACCEL_REG_FIFO_STATUS            0x0E
 134 #define BMC150_ACCEL_REG_FIFO_CONFIG0           0x30
 135 #define BMC150_ACCEL_REG_FIFO_CONFIG1           0x3E
 136 #define BMC150_ACCEL_REG_FIFO_DATA              0x3F
 137 #define BMC150_ACCEL_FIFO_LENGTH                32
 138
 139 enum bmc150_accel_axis {
 140         AXIS_X,
 141         AXIS_Y,
 142         AXIS_Z,
 143         AXIS_MAX,
 144 };
 145
 146 enum bmc150_power_modes {
 147         BMC150_ACCEL_SLEEP_MODE_NORMAL,
 148         BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
 149         BMC150_ACCEL_SLEEP_MODE_LPM,
 150         BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
 151 };
 152
 153 struct bmc150_scale_info {
 154         int scale;
 155         u8 reg_range;
 156 };
 157
 158 struct bmc150_accel_chip_info {
 159         const char *name;
 160         u8 chip_id;
 161         const struct iio_chan_spec *channels;
 162         int num_channels;
 163         const struct bmc150_scale_info scale_table[4];
 164 };
 165
 166 struct bmc150_accel_interrupt {
 167         const struct bmc150_accel_interrupt_info *info;
 168         atomic_t users;
 169 };
 170
 171 struct bmc150_accel_trigger {
 172         struct bmc150_accel_data *data;
 173         struct iio_trigger *indio_trig;
 174         int (*setup)(struct bmc150_accel_trigger *t, bool state);
 175         int intr;
 176         bool enabled;
 177 };
 178
 179 enum bmc150_accel_interrupt_id {
 180         BMC150_ACCEL_INT_DATA_READY,
 181         BMC150_ACCEL_INT_ANY_MOTION,
 182         BMC150_ACCEL_INT_WATERMARK,
 183         BMC150_ACCEL_INTERRUPTS,
 184 };
 185
 186 enum bmc150_accel_trigger_id {
 187         BMC150_ACCEL_TRIGGER_DATA_READY,
 188         BMC150_ACCEL_TRIGGER_ANY_MOTION,
 189         BMC150_ACCEL_TRIGGERS,
 190 };
 191
 192 struct bmc150_accel_data {
 193         struct regmap *regmap;
 194         int irq;
 195         struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
 196         struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
 197         struct mutex mutex;
 198         u8 fifo_mode, watermark;
 199         s16 buffer[8];
 200         /*
 201          * Ensure there is sufficient space and correct alignment for
 202          * the timestamp if enabled
 203          */
 204         struct {
 205                 __le16 channels[3];
 206                 s64 ts __aligned(8);
 207         } scan;
 208         u8 bw_bits;
 209         u32 slope_dur;
 210         u32 slope_thres;
 211         u32 range;
 212         int ev_enable_state;
 213         int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
 214         const struct bmc150_accel_chip_info *chip_info;
 215 };
 216
 217 static const struct {
 218         int val;
 219         int val2;
 220         u8 bw_bits;
 221 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
 222                                      {31, 260000, 0x09},
 223                                      {62, 500000, 0x0A},
 224                                      {125, 0, 0x0B},
 225                                      {250, 0, 0x0C},
 226                                      {500, 0, 0x0D},
 227                                      {1000, 0, 0x0E},
 228                                      {2000, 0, 0x0F} };
 229
 230 static const struct {
 231         int bw_bits;
 232         int msec;
 233 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
 234                                      {0x09, 32},
 235                                      {0x0A, 16},
 236                                      {0x0B, 8},
 237                                      {0x0C, 4},
 238                                      {0x0D, 2},
 239                                      {0x0E, 1},
 240                                      {0x0F, 1} };
 241
 242 static const struct {
 243         int sleep_dur;
 244         u8 reg_value;
 245 } bmc150_accel_sleep_value_table[] = { {0, 0},
 246                                        {500, BMC150_ACCEL_SLEEP_500_MICRO},
 247                                        {1000, BMC150_ACCEL_SLEEP_1_MS},
 248                                        {2000, BMC150_ACCEL_SLEEP_2_MS},
 249                                        {4000, BMC150_ACCEL_SLEEP_4_MS},
 250                                        {6000, BMC150_ACCEL_SLEEP_6_MS},
 251                                        {10000, BMC150_ACCEL_SLEEP_10_MS},
 252                                        {25000, BMC150_ACCEL_SLEEP_25_MS},
 253                                        {50000, BMC150_ACCEL_SLEEP_50_MS},
 254                                        {100000, BMC150_ACCEL_SLEEP_100_MS},
 255                                        {500000, BMC150_ACCEL_SLEEP_500_MS},
 256                                        {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
 257
 258 const struct regmap_config bmc150_regmap_conf = {
 259         .reg_bits = 8,
 260         .val_bits = 8,
 261         .max_register = 0x3f,
 262 };
 263 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
 264
 265 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
 266                                  enum bmc150_power_modes mode,
 267                                  int dur_us)
 268 {
 269         struct device *dev = regmap_get_device(data->regmap);
 270         int i;
 271         int ret;
 272         u8 lpw_bits;
 273         int dur_val = -1;
 274
 275         if (dur_us > 0) {
 276                 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
 277                                                                          ++i) {
 278                         if (bmc150_accel_sleep_value_table[i].sleep_dur ==
 279                                                                         dur_us)
 280                                 dur_val =
 281                                 bmc150_accel_sleep_value_table[i].reg_value;
 282                 }
 283         } else {
 284                 dur_val = 0;
 285         }
 286
 287         if (dur_val < 0)
 288                 return -EINVAL;
 289
 290         lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
 291         lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
 292
 293         dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
 294
 295         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
 296         if (ret < 0) {
 297                 dev_err(dev, "Error writing reg_pmu_lpw\n");
 298                 return ret;
 299         }
 300
 301         return 0;
 302 }
 303
 304 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
 305                                int val2)
 306 {
 307         int i;
 308         int ret;
 309
 310         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 311                 if (bmc150_accel_samp_freq_table[i].val == val &&
 312                     bmc150_accel_samp_freq_table[i].val2 == val2) {
 313                         ret = regmap_write(data->regmap,
 314                                 BMC150_ACCEL_REG_PMU_BW,
 315                                 bmc150_accel_samp_freq_table[i].bw_bits);
 316                         if (ret < 0)
 317                                 return ret;
 318
 319                         data->bw_bits =
 320                                 bmc150_accel_samp_freq_table[i].bw_bits;
 321                         return 0;
 322                 }
 323         }
 324
 325         return -EINVAL;
 326 }
 327
 328 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
 329 {
 330         struct device *dev = regmap_get_device(data->regmap);
 331         int ret;
 332
 333         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
 334                                         data->slope_thres);
 335         if (ret < 0) {
 336                 dev_err(dev, "Error writing reg_int_6\n");
 337                 return ret;
 338         }
 339
 340         ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
 341                                  BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
 342         if (ret < 0) {
 343                 dev_err(dev, "Error updating reg_int_5\n");
 344                 return ret;
 345         }
 346
 347         dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur);
 348
 349         return ret;
 350 }
 351
 352 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
 353                                          bool state)
 354 {
 355         if (state)
 356                 return bmc150_accel_update_slope(t->data);
 357
 358         return 0;
 359 }
 360
 361 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
 362                                int *val2)
 363 {
 364         int i;
 365
 366         for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
 367                 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
 368                         *val = bmc150_accel_samp_freq_table[i].val;
 369                         *val2 = bmc150_accel_samp_freq_table[i].val2;
 370                         return IIO_VAL_INT_PLUS_MICRO;
 371                 }
 372         }
 373
 374         return -EINVAL;
 375 }
 376
 377 #ifdef CONFIG_PM
 378 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
 379 {
 380         int i;
 381
 382         for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
 383                 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
 384                         return bmc150_accel_sample_upd_time[i].msec;
 385         }
 386
 387         return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
 388 }
 389
 390 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 391 {
 392         struct device *dev = regmap_get_device(data->regmap);
 393         int ret;
 394
 395         if (on) {
 396                 ret = pm_runtime_get_sync(dev);
 397         } else {
 398                 pm_runtime_mark_last_busy(dev);
 399                 ret = pm_runtime_put_autosuspend(dev);
 400         }
 401
 402         if (ret < 0) {
 403                 dev_err(dev,
 404                         "Failed: bmc150_accel_set_power_state for %d\n", on);
 405                 if (on)
 406                         pm_runtime_put_noidle(dev);
 407
 408                 return ret;
 409         }
 410
 411         return 0;
 412 }
 413 #else
 414 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
 415 {
 416         return 0;
 417 }
 418 #endif
 419
 420 static const struct bmc150_accel_interrupt_info {
 421         u8 map_reg;
 422         u8 map_bitmask;
 423         u8 en_reg;
 424         u8 en_bitmask;
 425 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
 426         { /* data ready interrupt */
 427                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 428                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
 429                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 430                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
 431         },
 432         {  /* motion interrupt */
 433                 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
 434                 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
 435                 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
 436                 .en_bitmask =  BMC150_ACCEL_INT_EN_BIT_SLP_X |
 437                         BMC150_ACCEL_INT_EN_BIT_SLP_Y |
 438                         BMC150_ACCEL_INT_EN_BIT_SLP_Z
 439         },
 440         { /* fifo watermark interrupt */
 441                 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
 442                 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
 443                 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
 444                 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
 445         },
 446 };
 447
 448 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
 449                                           struct bmc150_accel_data *data)
 450 {
 451         int i;
 452
 453         for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
 454                 data->interrupts[i].info = &bmc150_accel_interrupts[i];
 455 }
 456
 457 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
 458                                       bool state)
 459 {
 460         struct device *dev = regmap_get_device(data->regmap);
 461         struct bmc150_accel_interrupt *intr = &data->interrupts[i];
 462         const struct bmc150_accel_interrupt_info *info = intr->info;
 463         int ret;
 464
 465         if (state) {
 466                 if (atomic_inc_return(&intr->users) > 1)
 467                         return 0;
 468         } else {
 469                 if (atomic_dec_return(&intr->users) > 0)
 470                         return 0;
 471         }
 472
 473         /*
 474          * We will expect the enable and disable to do operation in reverse
 475          * order. This will happen here anyway, as our resume operation uses
 476          * sync mode runtime pm calls. The suspend operation will be delayed
 477          * by autosuspend delay.
 478          * So the disable operation will still happen in reverse order of
 479          * enable operation. When runtime pm is disabled the mode is always on,
 480          * so sequence doesn't matter.
 481          */
 482         ret = bmc150_accel_set_power_state(data, state);
 483         if (ret < 0)
 484                 return ret;
 485
 486         /* map the interrupt to the appropriate pins */
 487         ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
 488                                  (state ? info->map_bitmask : 0));
 489         if (ret < 0) {
 490                 dev_err(dev, "Error updating reg_int_map\n");
 491                 goto out_fix_power_state;
 492         }
 493
 494         /* enable/disable the interrupt */
 495         ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
 496                                  (state ? info->en_bitmask : 0));
 497         if (ret < 0) {
 498                 dev_err(dev, "Error updating reg_int_en\n");
 499                 goto out_fix_power_state;
 500         }
 501
 502         return 0;
 503
 504 out_fix_power_state:
 505         bmc150_accel_set_power_state(data, false);
 506         return ret;
 507 }
 508
 509 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
 510 {
 511         struct device *dev = regmap_get_device(data->regmap);
 512         int ret, i;
 513
 514         for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
 515                 if (data->chip_info->scale_table[i].scale == val) {
 516                         ret = regmap_write(data->regmap,
 517                                      BMC150_ACCEL_REG_PMU_RANGE,
 518                                      data->chip_info->scale_table[i].reg_range);
 519                         if (ret < 0) {
 520                                 dev_err(dev, "Error writing pmu_range\n");
 521                                 return ret;
 522                         }
 523
 524                         data->range = data->chip_info->scale_table[i].reg_range;
 525                         return 0;
 526                 }
 527         }
 528
 529         return -EINVAL;
 530 }
 531
 532 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
 533 {
 534         struct device *dev = regmap_get_device(data->regmap);
 535         int ret;
 536         unsigned int value;
 537
 538         mutex_lock(&data->mutex);
 539
 540         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
 541         if (ret < 0) {
 542                 dev_err(dev, "Error reading reg_temp\n");
 543                 mutex_unlock(&data->mutex);
 544                 return ret;
 545         }
 546         *val = sign_extend32(value, 7);
 547
 548         mutex_unlock(&data->mutex);
 549
 550         return IIO_VAL_INT;
 551 }
 552
 553 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
 554                                  struct iio_chan_spec const *chan,
 555                                  int *val)
 556 {
 557         struct device *dev = regmap_get_device(data->regmap);
 558         int ret;
 559         int axis = chan->scan_index;
 560         __le16 raw_val;
 561
 562         mutex_lock(&data->mutex);
 563         ret = bmc150_accel_set_power_state(data, true);
 564         if (ret < 0) {
 565                 mutex_unlock(&data->mutex);
 566                 return ret;
 567         }
 568
 569         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
 570                                &raw_val, sizeof(raw_val));
 571         if (ret < 0) {
 572                 dev_err(dev, "Error reading axis %d\n", axis);
 573                 bmc150_accel_set_power_state(data, false);
 574                 mutex_unlock(&data->mutex);
 575                 return ret;
 576         }
 577         *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
 578                              chan->scan_type.realbits - 1);
 579         ret = bmc150_accel_set_power_state(data, false);
 580         mutex_unlock(&data->mutex);
 581         if (ret < 0)
 582                 return ret;
 583
 584         return IIO_VAL_INT;
 585 }
 586
 587 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
 588                                  struct iio_chan_spec const *chan,
 589                                  int *val, int *val2, long mask)
 590 {
 591         struct bmc150_accel_data *data = iio_priv(indio_dev);
 592         int ret;
 593
 594         switch (mask) {
 595         case IIO_CHAN_INFO_RAW:
 596                 switch (chan->type) {
 597                 case IIO_TEMP:
 598                         return bmc150_accel_get_temp(data, val);
 599                 case IIO_ACCEL:
 600                         if (iio_buffer_enabled(indio_dev))
 601                                 return -EBUSY;
 602                         else
 603                                 return bmc150_accel_get_axis(data, chan, val);
 604                 default:
 605                         return -EINVAL;
 606                 }
 607         case IIO_CHAN_INFO_OFFSET:
 608                 if (chan->type == IIO_TEMP) {
 609                         *val = BMC150_ACCEL_TEMP_CENTER_VAL;
 610                         return IIO_VAL_INT;
 611                 } else {
 612                         return -EINVAL;
 613                 }
 614         case IIO_CHAN_INFO_SCALE:
 615                 *val = 0;
 616                 switch (chan->type) {
 617                 case IIO_TEMP:
 618                         *val2 = 500000;
 619                         return IIO_VAL_INT_PLUS_MICRO;
 620                 case IIO_ACCEL:
 621                 {
 622                         int i;
 623                         const struct bmc150_scale_info *si;
 624                         int st_size = ARRAY_SIZE(data->chip_info->scale_table);
 625
 626                         for (i = 0; i < st_size; ++i) {
 627                                 si = &data->chip_info->scale_table[i];
 628                                 if (si->reg_range == data->range) {
 629                                         *val2 = si->scale;
 630                                         return IIO_VAL_INT_PLUS_MICRO;
 631                                 }
 632                         }
 633                         return -EINVAL;
 634                 }
 635                 default:
 636                         return -EINVAL;
 637                 }
 638         case IIO_CHAN_INFO_SAMP_FREQ:
 639                 mutex_lock(&data->mutex);
 640                 ret = bmc150_accel_get_bw(data, val, val2);
 641                 mutex_unlock(&data->mutex);
 642                 return ret;
 643         default:
 644                 return -EINVAL;
 645         }
 646 }
 647
 648 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
 649                                   struct iio_chan_spec const *chan,
 650                                   int val, int val2, long mask)
 651 {
 652         struct bmc150_accel_data *data = iio_priv(indio_dev);
 653         int ret;
 654
 655         switch (mask) {
 656         case IIO_CHAN_INFO_SAMP_FREQ:
 657                 mutex_lock(&data->mutex);
 658                 ret = bmc150_accel_set_bw(data, val, val2);
 659                 mutex_unlock(&data->mutex);
 660                 break;
 661         case IIO_CHAN_INFO_SCALE:
 662                 if (val)
 663                         return -EINVAL;
 664
 665                 mutex_lock(&data->mutex);
 666                 ret = bmc150_accel_set_scale(data, val2);
 667                 mutex_unlock(&data->mutex);
 668                 return ret;
 669         default:
 670                 ret = -EINVAL;
 671         }
 672
 673         return ret;
 674 }
 675
 676 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
 677                                    const struct iio_chan_spec *chan,
 678                                    enum iio_event_type type,
 679                                    enum iio_event_direction dir,
 680                                    enum iio_event_info info,
 681                                    int *val, int *val2)
 682 {
 683         struct bmc150_accel_data *data = iio_priv(indio_dev);
 684
 685         *val2 = 0;
 686         switch (info) {
 687         case IIO_EV_INFO_VALUE:
 688                 *val = data->slope_thres;
 689                 break;
 690         case IIO_EV_INFO_PERIOD:
 691                 *val = data->slope_dur;
 692                 break;
 693         default:
 694                 return -EINVAL;
 695         }
 696
 697         return IIO_VAL_INT;
 698 }
 699
 700 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
 701                                     const struct iio_chan_spec *chan,
 702                                     enum iio_event_type type,
 703                                     enum iio_event_direction dir,
 704                                     enum iio_event_info info,
 705                                     int val, int val2)
 706 {
 707         struct bmc150_accel_data *data = iio_priv(indio_dev);
 708
 709         if (data->ev_enable_state)
 710                 return -EBUSY;
 711
 712         switch (info) {
 713         case IIO_EV_INFO_VALUE:
 714                 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
 715                 break;
 716         case IIO_EV_INFO_PERIOD:
 717                 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
 718                 break;
 719         default:
 720                 return -EINVAL;
 721         }
 722
 723         return 0;
 724 }
 725
 726 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
 727                                           const struct iio_chan_spec *chan,
 728                                           enum iio_event_type type,
 729                                           enum iio_event_direction dir)
 730 {
 731         struct bmc150_accel_data *data = iio_priv(indio_dev);
 732
 733         return data->ev_enable_state;
 734 }
 735
 736 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
 737                                            const struct iio_chan_spec *chan,
 738                                            enum iio_event_type type,
 739                                            enum iio_event_direction dir,
 740                                            int state)
 741 {
 742         struct bmc150_accel_data *data = iio_priv(indio_dev);
 743         int ret;
 744
 745         if (state == data->ev_enable_state)
 746                 return 0;
 747
 748         mutex_lock(&data->mutex);
 749
 750         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
 751                                          state);
 752         if (ret < 0) {
 753                 mutex_unlock(&data->mutex);
 754                 return ret;
 755         }
 756
 757         data->ev_enable_state = state;
 758         mutex_unlock(&data->mutex);
 759
 760         return 0;
 761 }
 762
 763 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
 764                                          struct iio_trigger *trig)
 765 {
 766         struct bmc150_accel_data *data = iio_priv(indio_dev);
 767         int i;
 768
 769         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
 770                 if (data->triggers[i].indio_trig == trig)
 771                         return 0;
 772         }
 773
 774         return -EINVAL;
 775 }
 776
 777 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
 778                                                struct device_attribute *attr,
 779                                                char *buf)
 780 {
 781         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 782         struct bmc150_accel_data *data = iio_priv(indio_dev);
 783         int wm;
 784
 785         mutex_lock(&data->mutex);
 786         wm = data->watermark;
 787         mutex_unlock(&data->mutex);
 788
 789         return sprintf(buf, "%d\n", wm);
 790 }
 791
 792 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
 793                                            struct device_attribute *attr,
 794                                            char *buf)
 795 {
 796         struct iio_dev *indio_dev = dev_to_iio_dev(dev);
 797         struct bmc150_accel_data *data = iio_priv(indio_dev);
 798         bool state;
 799
 800         mutex_lock(&data->mutex);
 801         state = data->fifo_mode;
 802         mutex_unlock(&data->mutex);
 803
 804         return sprintf(buf, "%d\n", state);
 805 }
 806
 807 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
 808 static IIO_CONST_ATTR(hwfifo_watermark_max,
 809                       __stringify(BMC150_ACCEL_FIFO_LENGTH));
 810 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
 811                        bmc150_accel_get_fifo_state, NULL, 0);
 812 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
 813                        bmc150_accel_get_fifo_watermark, NULL, 0);
 814
 815 static const struct attribute *bmc150_accel_fifo_attributes[] = {
 816         &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
 817         &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
 818         &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
 819         &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
 820         NULL,
 821 };
 822
 823 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
 824 {
 825         struct bmc150_accel_data *data = iio_priv(indio_dev);
 826
 827         if (val > BMC150_ACCEL_FIFO_LENGTH)
 828                 val = BMC150_ACCEL_FIFO_LENGTH;
 829
 830         mutex_lock(&data->mutex);
 831         data->watermark = val;
 832         mutex_unlock(&data->mutex);
 833
 834         return 0;
 835 }
 836
 837 /*
 838  * We must read at least one full frame in one burst, otherwise the rest of the
 839  * frame data is discarded.
 840  */
 841 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
 842                                       char *buffer, int samples)
 843 {
 844         struct device *dev = regmap_get_device(data->regmap);
 845         int sample_length = 3 * 2;
 846         int ret;
 847         int total_length = samples * sample_length;
 848
 849         ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
 850                               buffer, total_length);
 851         if (ret)
 852                 dev_err(dev,
 853                         "Error transferring data from fifo: %d\n", ret);
 854
 855         return ret;
 856 }
 857
 858 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
 859                                      unsigned samples, bool irq)
 860 {
 861         struct bmc150_accel_data *data = iio_priv(indio_dev);
 862         struct device *dev = regmap_get_device(data->regmap);
 863         int ret, i;
 864         u8 count;
 865         u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
 866         int64_t tstamp;
 867         uint64_t sample_period;
 868         unsigned int val;
 869
 870         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
 871         if (ret < 0) {
 872                 dev_err(dev, "Error reading reg_fifo_status\n");
 873                 return ret;
 874         }
 875
 876         count = val & 0x7F;
 877
 878         if (!count)
 879                 return 0;
 880
 881         /*
 882          * If we getting called from IRQ handler we know the stored timestamp is
 883          * fairly accurate for the last stored sample. Otherwise, if we are
 884          * called as a result of a read operation from userspace and hence
 885          * before the watermark interrupt was triggered, take a timestamp
 886          * now. We can fall anywhere in between two samples so the error in this
 887          * case is at most one sample period.
 888          */
 889         if (!irq) {
 890                 data->old_timestamp = data->timestamp;
 891                 data->timestamp = iio_get_time_ns(indio_dev);
 892         }
 893
 894         /*
 895          * Approximate timestamps for each of the sample based on the sampling
 896          * frequency, timestamp for last sample and number of samples.
 897          *
 898          * Note that we can't use the current bandwidth settings to compute the
 899          * sample period because the sample rate varies with the device
 900          * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
 901          * small variation adds when we store a large number of samples and
 902          * creates significant jitter between the last and first samples in
 903          * different batches (e.g. 32ms vs 21ms).
 904          *
 905          * To avoid this issue we compute the actual sample period ourselves
 906          * based on the timestamp delta between the last two flush operations.
 907          */
 908         sample_period = (data->timestamp - data->old_timestamp);
 909         do_div(sample_period, count);
 910         tstamp = data->timestamp - (count - 1) * sample_period;
 911
 912         if (samples && count > samples)
 913                 count = samples;
 914
 915         ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
 916         if (ret)
 917                 return ret;
 918
 919         /*
 920          * Ideally we want the IIO core to handle the demux when running in fifo
 921          * mode but not when running in triggered buffer mode. Unfortunately
 922          * this does not seem to be possible, so stick with driver demux for
 923          * now.
 924          */
 925         for (i = 0; i < count; i++) {
 926                 int j, bit;
 927
 928                 j = 0;
 929                 for_each_set_bit(bit, indio_dev->active_scan_mask,
 930                                  indio_dev->masklength)
 931                         memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
 932                                sizeof(data->scan.channels[0]));
 933
 934                 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
 935                                                    tstamp);
 936
 937                 tstamp += sample_period;
 938         }
 939
 940         return count;
 941 }
 942
 943 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
 944 {
 945         struct bmc150_accel_data *data = iio_priv(indio_dev);
 946         int ret;
 947
 948         mutex_lock(&data->mutex);
 949         ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
 950         mutex_unlock(&data->mutex);
 951
 952         return ret;
 953 }
 954
 955 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
 956                 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
 957
 958 static struct attribute *bmc150_accel_attributes[] = {
 959         &iio_const_attr_sampling_frequency_available.dev_attr.attr,
 960         NULL,
 961 };
 962
 963 static const struct attribute_group bmc150_accel_attrs_group = {
 964         .attrs = bmc150_accel_attributes,
 965 };
 966
 967 static const struct iio_event_spec bmc150_accel_event = {
 968                 .type = IIO_EV_TYPE_ROC,
 969                 .dir = IIO_EV_DIR_EITHER,
 970                 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
 971                                  BIT(IIO_EV_INFO_ENABLE) |
 972                                  BIT(IIO_EV_INFO_PERIOD)
 973 };
 974
 975 #define BMC150_ACCEL_CHANNEL(_axis, bits) {                             \
 976         .type = IIO_ACCEL,                                              \
 977         .modified = 1,                                                  \
 978         .channel2 = IIO_MOD_##_axis,                                    \
 979         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW),                   \
 980         .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) |          \
 981                                 BIT(IIO_CHAN_INFO_SAMP_FREQ),           \
 982         .scan_index = AXIS_##_axis,                                     \
 983         .scan_type = {                                                  \
 984                 .sign = 's',                                            \
 985                 .realbits = (bits),                                     \
 986                 .storagebits = 16,                                      \
 987                 .shift = 16 - (bits),                                   \
 988                 .endianness = IIO_LE,                                   \
 989         },                                                              \
 990         .event_spec = &bmc150_accel_event,                              \
 991         .num_event_specs = 1                                            \
 992 }
 993
 994 #define BMC150_ACCEL_CHANNELS(bits) {                                   \
 995         {                                                               \
 996                 .type = IIO_TEMP,                                       \
 997                 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |          \
 998                                       BIT(IIO_CHAN_INFO_SCALE) |        \
 999                                       BIT(IIO_CHAN_INFO_OFFSET),        \
1000                 .scan_index = -1,                                       \
1001         },                                                              \
1002         BMC150_ACCEL_CHANNEL(X, bits),                                  \
1003         BMC150_ACCEL_CHANNEL(Y, bits),                                  \
1004         BMC150_ACCEL_CHANNEL(Z, bits),                                  \
1005         IIO_CHAN_SOFT_TIMESTAMP(3),                                     \
1006 }
1007
1008 static const struct iio_chan_spec bma222e_accel_channels[] =
1009         BMC150_ACCEL_CHANNELS(8);
1010 static const struct iio_chan_spec bma250e_accel_channels[] =
1011         BMC150_ACCEL_CHANNELS(10);
1012 static const struct iio_chan_spec bmc150_accel_channels[] =
1013         BMC150_ACCEL_CHANNELS(12);
1014 static const struct iio_chan_spec bma280_accel_channels[] =
1015         BMC150_ACCEL_CHANNELS(14);
1016
1017 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1018         [bmc150] = {
1019                 .name = "BMC150A",
1020                 .chip_id = 0xFA,
1021                 .channels = bmc150_accel_channels,
1022                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1023                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1024                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1025                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1026                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1027         },
1028         [bmi055] = {
1029                 .name = "BMI055A",
1030                 .chip_id = 0xFA,
1031                 .channels = bmc150_accel_channels,
1032                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1033                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1034                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1035                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1036                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1037         },
1038         [bma255] = {
1039                 .name = "BMA0255",
1040                 .chip_id = 0xFA,
1041                 .channels = bmc150_accel_channels,
1042                 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1043                 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1044                                  {19122, BMC150_ACCEL_DEF_RANGE_4G},
1045                                  {38344, BMC150_ACCEL_DEF_RANGE_8G},
1046                                  {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1047         },
1048         [bma250e] = {
1049                 .name = "BMA250E",
1050                 .chip_id = 0xF9,
1051                 .channels = bma250e_accel_channels,
1052                 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1053                 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1054                                  {76590, BMC150_ACCEL_DEF_RANGE_4G},
1055                                  {153277, BMC150_ACCEL_DEF_RANGE_8G},
1056                                  {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1057         },
1058         [bma222e] = {
1059                 .name = "BMA222E",
1060                 .chip_id = 0xF8,
1061                 .channels = bma222e_accel_channels,
1062                 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1063                 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1064                                  {306457, BMC150_ACCEL_DEF_RANGE_4G},
1065                                  {612915, BMC150_ACCEL_DEF_RANGE_8G},
1066                                  {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1067         },
1068         [bma280] = {
1069                 .name = "BMA0280",
1070                 .chip_id = 0xFB,
1071                 .channels = bma280_accel_channels,
1072                 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1073                 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1074                                  {4785, BMC150_ACCEL_DEF_RANGE_4G},
1075                                  {9581, BMC150_ACCEL_DEF_RANGE_8G},
1076                                  {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1077         },
1078 };
1079
1080 static const struct iio_info bmc150_accel_info = {
1081         .attrs                  = &bmc150_accel_attrs_group,
1082         .read_raw               = bmc150_accel_read_raw,
1083         .write_raw              = bmc150_accel_write_raw,
1084         .read_event_value       = bmc150_accel_read_event,
1085         .write_event_value      = bmc150_accel_write_event,
1086         .write_event_config     = bmc150_accel_write_event_config,
1087         .read_event_config      = bmc150_accel_read_event_config,
1088 };
1089
1090 static const struct iio_info bmc150_accel_info_fifo = {
1091         .attrs                  = &bmc150_accel_attrs_group,
1092         .read_raw               = bmc150_accel_read_raw,
1093         .write_raw              = bmc150_accel_write_raw,
1094         .read_event_value       = bmc150_accel_read_event,
1095         .write_event_value      = bmc150_accel_write_event,
1096         .write_event_config     = bmc150_accel_write_event_config,
1097         .read_event_config      = bmc150_accel_read_event_config,
1098         .validate_trigger       = bmc150_accel_validate_trigger,
1099         .hwfifo_set_watermark   = bmc150_accel_set_watermark,
1100         .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1101 };
1102
1103 static const unsigned long bmc150_accel_scan_masks[] = {
1104                                         BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1105                                         0};
1106
1107 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1108 {
1109         struct iio_poll_func *pf = p;
1110         struct iio_dev *indio_dev = pf->indio_dev;
1111         struct bmc150_accel_data *data = iio_priv(indio_dev);
1112         int ret;
1113
1114         mutex_lock(&data->mutex);
1115         ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1116                                data->buffer, AXIS_MAX * 2);
1117         mutex_unlock(&data->mutex);
1118         if (ret < 0)
1119                 goto err_read;
1120
1121         iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1122                                            pf->timestamp);
1123 err_read:
1124         iio_trigger_notify_done(indio_dev->trig);
1125
1126         return IRQ_HANDLED;
1127 }
1128
1129 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1130 {
1131         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1132         struct bmc150_accel_data *data = t->data;
1133         struct device *dev = regmap_get_device(data->regmap);
1134         int ret;
1135
1136         /* new data interrupts don't need ack */
1137         if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1138                 return 0;
1139
1140         mutex_lock(&data->mutex);
1141         /* clear any latched interrupt */
1142         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1143                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1144                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1145         mutex_unlock(&data->mutex);
1146         if (ret < 0) {
1147                 dev_err(dev, "Error writing reg_int_rst_latch\n");
1148                 return ret;
1149         }
1150
1151         return 0;
1152 }
1153
1154 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1155                                           bool state)
1156 {
1157         struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1158         struct bmc150_accel_data *data = t->data;
1159         int ret;
1160
1161         mutex_lock(&data->mutex);
1162
1163         if (t->enabled == state) {
1164                 mutex_unlock(&data->mutex);
1165                 return 0;
1166         }
1167
1168         if (t->setup) {
1169                 ret = t->setup(t, state);
1170                 if (ret < 0) {
1171                         mutex_unlock(&data->mutex);
1172                         return ret;
1173                 }
1174         }
1175
1176         ret = bmc150_accel_set_interrupt(data, t->intr, state);
1177         if (ret < 0) {
1178                 mutex_unlock(&data->mutex);
1179                 return ret;
1180         }
1181
1182         t->enabled = state;
1183
1184         mutex_unlock(&data->mutex);
1185
1186         return ret;
1187 }
1188
1189 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1190         .set_trigger_state = bmc150_accel_trigger_set_state,
1191         .try_reenable = bmc150_accel_trig_try_reen,
1192 };
1193
1194 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1195 {
1196         struct bmc150_accel_data *data = iio_priv(indio_dev);
1197         struct device *dev = regmap_get_device(data->regmap);
1198         int dir;
1199         int ret;
1200         unsigned int val;
1201
1202         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1203         if (ret < 0) {
1204                 dev_err(dev, "Error reading reg_int_status_2\n");
1205                 return ret;
1206         }
1207
1208         if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1209                 dir = IIO_EV_DIR_FALLING;
1210         else
1211                 dir = IIO_EV_DIR_RISING;
1212
1213         if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1214                 iio_push_event(indio_dev,
1215                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1216                                                   0,
1217                                                   IIO_MOD_X,
1218                                                   IIO_EV_TYPE_ROC,
1219                                                   dir),
1220                                data->timestamp);
1221
1222         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1223                 iio_push_event(indio_dev,
1224                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1225                                                   0,
1226                                                   IIO_MOD_Y,
1227                                                   IIO_EV_TYPE_ROC,
1228                                                   dir),
1229                                data->timestamp);
1230
1231         if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1232                 iio_push_event(indio_dev,
1233                                IIO_MOD_EVENT_CODE(IIO_ACCEL,
1234                                                   0,
1235                                                   IIO_MOD_Z,
1236                                                   IIO_EV_TYPE_ROC,
1237                                                   dir),
1238                                data->timestamp);
1239
1240         return ret;
1241 }
1242
1243 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1244 {
1245         struct iio_dev *indio_dev = private;
1246         struct bmc150_accel_data *data = iio_priv(indio_dev);
1247         struct device *dev = regmap_get_device(data->regmap);
1248         bool ack = false;
1249         int ret;
1250
1251         mutex_lock(&data->mutex);
1252
1253         if (data->fifo_mode) {
1254                 ret = __bmc150_accel_fifo_flush(indio_dev,
1255                                                 BMC150_ACCEL_FIFO_LENGTH, true);
1256                 if (ret > 0)
1257                         ack = true;
1258         }
1259
1260         if (data->ev_enable_state) {
1261                 ret = bmc150_accel_handle_roc_event(indio_dev);
1262                 if (ret > 0)
1263                         ack = true;
1264         }
1265
1266         if (ack) {
1267                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1268                                    BMC150_ACCEL_INT_MODE_LATCH_INT |
1269                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1270                 if (ret)
1271                         dev_err(dev, "Error writing reg_int_rst_latch\n");
1272
1273                 ret = IRQ_HANDLED;
1274         } else {
1275                 ret = IRQ_NONE;
1276         }
1277
1278         mutex_unlock(&data->mutex);
1279
1280         return ret;
1281 }
1282
1283 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1284 {
1285         struct iio_dev *indio_dev = private;
1286         struct bmc150_accel_data *data = iio_priv(indio_dev);
1287         bool ack = false;
1288         int i;
1289
1290         data->old_timestamp = data->timestamp;
1291         data->timestamp = iio_get_time_ns(indio_dev);
1292
1293         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1294                 if (data->triggers[i].enabled) {
1295                         iio_trigger_poll(data->triggers[i].indio_trig);
1296                         ack = true;
1297                         break;
1298                 }
1299         }
1300
1301         if (data->ev_enable_state || data->fifo_mode)
1302                 return IRQ_WAKE_THREAD;
1303
1304         if (ack)
1305                 return IRQ_HANDLED;
1306
1307         return IRQ_NONE;
1308 }
1309
1310 static const struct {
1311         int intr;
1312         const char *name;
1313         int (*setup)(struct bmc150_accel_trigger *t, bool state);
1314 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1315         {
1316                 .intr = 0,
1317                 .name = "%s-dev%d",
1318         },
1319         {
1320                 .intr = 1,
1321                 .name = "%s-any-motion-dev%d",
1322                 .setup = bmc150_accel_any_motion_setup,
1323         },
1324 };
1325
1326 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1327                                              int from)
1328 {
1329         int i;
1330
1331         for (i = from; i >= 0; i--) {
1332                 if (data->triggers[i].indio_trig) {
1333                         iio_trigger_unregister(data->triggers[i].indio_trig);
1334                         data->triggers[i].indio_trig = NULL;
1335                 }
1336         }
1337 }
1338
1339 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1340                                        struct bmc150_accel_data *data)
1341 {
1342         struct device *dev = regmap_get_device(data->regmap);
1343         int i, ret;
1344
1345         for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1346                 struct bmc150_accel_trigger *t = &data->triggers[i];
1347
1348                 t->indio_trig = devm_iio_trigger_alloc(dev,
1349                                         bmc150_accel_triggers[i].name,
1350                                                        indio_dev->name,
1351                                                        indio_dev->id);
1352                 if (!t->indio_trig) {
1353                         ret = -ENOMEM;
1354                         break;
1355                 }
1356
1357                 t->indio_trig->dev.parent = dev;
1358                 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1359                 t->intr = bmc150_accel_triggers[i].intr;
1360                 t->data = data;
1361                 t->setup = bmc150_accel_triggers[i].setup;
1362                 iio_trigger_set_drvdata(t->indio_trig, t);
1363
1364                 ret = iio_trigger_register(t->indio_trig);
1365                 if (ret)
1366                         break;
1367         }
1368
1369         if (ret)
1370                 bmc150_accel_unregister_triggers(data, i - 1);
1371
1372         return ret;
1373 }
1374
1375 #define BMC150_ACCEL_FIFO_MODE_STREAM          0x80
1376 #define BMC150_ACCEL_FIFO_MODE_FIFO            0x40
1377 #define BMC150_ACCEL_FIFO_MODE_BYPASS          0x00
1378
1379 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1380 {
1381         struct device *dev = regmap_get_device(data->regmap);
1382         u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1383         int ret;
1384
1385         ret = regmap_write(data->regmap, reg, data->fifo_mode);
1386         if (ret < 0) {
1387                 dev_err(dev, "Error writing reg_fifo_config1\n");
1388                 return ret;
1389         }
1390
1391         if (!data->fifo_mode)
1392                 return 0;
1393
1394         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1395                            data->watermark);
1396         if (ret < 0)
1397                 dev_err(dev, "Error writing reg_fifo_config0\n");
1398
1399         return ret;
1400 }
1401
1402 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1403 {
1404         struct bmc150_accel_data *data = iio_priv(indio_dev);
1405
1406         return bmc150_accel_set_power_state(data, true);
1407 }
1408
1409 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1410 {
1411         struct bmc150_accel_data *data = iio_priv(indio_dev);
1412         int ret = 0;
1413
1414         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1415                 return iio_triggered_buffer_postenable(indio_dev);
1416
1417         mutex_lock(&data->mutex);
1418
1419         if (!data->watermark)
1420                 goto out;
1421
1422         ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1423                                          true);
1424         if (ret)
1425                 goto out;
1426
1427         data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1428
1429         ret = bmc150_accel_fifo_set_mode(data);
1430         if (ret) {
1431                 data->fifo_mode = 0;
1432                 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1433                                            false);
1434         }
1435
1436 out:
1437         mutex_unlock(&data->mutex);
1438
1439         return ret;
1440 }
1441
1442 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1443 {
1444         struct bmc150_accel_data *data = iio_priv(indio_dev);
1445
1446         if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1447                 return iio_triggered_buffer_predisable(indio_dev);
1448
1449         mutex_lock(&data->mutex);
1450
1451         if (!data->fifo_mode)
1452                 goto out;
1453
1454         bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1455         __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1456         data->fifo_mode = 0;
1457         bmc150_accel_fifo_set_mode(data);
1458
1459 out:
1460         mutex_unlock(&data->mutex);
1461
1462         return 0;
1463 }
1464
1465 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1466 {
1467         struct bmc150_accel_data *data = iio_priv(indio_dev);
1468
1469         return bmc150_accel_set_power_state(data, false);
1470 }
1471
1472 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1473         .preenable = bmc150_accel_buffer_preenable,
1474         .postenable = bmc150_accel_buffer_postenable,
1475         .predisable = bmc150_accel_buffer_predisable,
1476         .postdisable = bmc150_accel_buffer_postdisable,
1477 };
1478
1479 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1480 {
1481         struct device *dev = regmap_get_device(data->regmap);
1482         int ret, i;
1483         unsigned int val;
1484
1485         /*
1486          * Reset chip to get it in a known good state. A delay of 1.8ms after
1487          * reset is required according to the data sheets of supported chips.
1488          */
1489         regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1490                      BMC150_ACCEL_RESET_VAL);
1491         usleep_range(1800, 2500);
1492
1493         ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1494         if (ret < 0) {
1495                 dev_err(dev, "Error: Reading chip id\n");
1496                 return ret;
1497         }
1498
1499         dev_dbg(dev, "Chip Id %x\n", val);
1500         for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1501                 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1502                         data->chip_info = &bmc150_accel_chip_info_tbl[i];
1503                         break;
1504                 }
1505         }
1506
1507         if (!data->chip_info) {
1508                 dev_err(dev, "Invalid chip %x\n", val);
1509                 return -ENODEV;
1510         }
1511
1512         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1513         if (ret < 0)
1514                 return ret;
1515
1516         /* Set Bandwidth */
1517         ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1518         if (ret < 0)
1519                 return ret;
1520
1521         /* Set Default Range */
1522         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1523                            BMC150_ACCEL_DEF_RANGE_4G);
1524         if (ret < 0) {
1525                 dev_err(dev, "Error writing reg_pmu_range\n");
1526                 return ret;
1527         }
1528
1529         data->range = BMC150_ACCEL_DEF_RANGE_4G;
1530
1531         /* Set default slope duration and thresholds */
1532         data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1533         data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1534         ret = bmc150_accel_update_slope(data);
1535         if (ret < 0)
1536                 return ret;
1537
1538         /* Set default as latched interrupts */
1539         ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1540                            BMC150_ACCEL_INT_MODE_LATCH_INT |
1541                            BMC150_ACCEL_INT_MODE_LATCH_RESET);
1542         if (ret < 0) {
1543                 dev_err(dev, "Error writing reg_int_rst_latch\n");
1544                 return ret;
1545         }
1546
1547         return 0;
1548 }
1549
1550 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1551                             const char *name, bool block_supported)
1552 {
1553         struct bmc150_accel_data *data;
1554         struct iio_dev *indio_dev;
1555         int ret;
1556
1557         indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1558         if (!indio_dev)
1559                 return -ENOMEM;
1560
1561         data = iio_priv(indio_dev);
1562         dev_set_drvdata(dev, indio_dev);
1563         data->irq = irq;
1564
1565         data->regmap = regmap;
1566
1567         ret = bmc150_accel_chip_init(data);
1568         if (ret < 0)
1569                 return ret;
1570
1571         mutex_init(&data->mutex);
1572
1573         indio_dev->dev.parent = dev;
1574         indio_dev->channels = data->chip_info->channels;
1575         indio_dev->num_channels = data->chip_info->num_channels;
1576         indio_dev->name = name ? name : data->chip_info->name;
1577         indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1578         indio_dev->modes = INDIO_DIRECT_MODE;
1579         indio_dev->info = &bmc150_accel_info;
1580
1581         ret = iio_triggered_buffer_setup(indio_dev,
1582                                          &iio_pollfunc_store_time,
1583                                          bmc150_accel_trigger_handler,
1584                                          &bmc150_accel_buffer_ops);
1585         if (ret < 0) {
1586                 dev_err(dev, "Failed: iio triggered buffer setup\n");
1587                 return ret;
1588         }
1589
1590         if (data->irq > 0) {
1591                 ret = devm_request_threaded_irq(
1592                                                 dev, data->irq,
1593                                                 bmc150_accel_irq_handler,
1594                                                 bmc150_accel_irq_thread_handler,
1595                                                 IRQF_TRIGGER_RISING,
1596                                                 BMC150_ACCEL_IRQ_NAME,
1597                                                 indio_dev);
1598                 if (ret)
1599                         goto err_buffer_cleanup;
1600
1601                 /*
1602                  * Set latched mode interrupt. While certain interrupts are
1603                  * non-latched regardless of this settings (e.g. new data) we
1604                  * want to use latch mode when we can to prevent interrupt
1605                  * flooding.
1606                  */
1607                 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1608                                    BMC150_ACCEL_INT_MODE_LATCH_RESET);
1609                 if (ret < 0) {
1610                         dev_err(dev, "Error writing reg_int_rst_latch\n");
1611                         goto err_buffer_cleanup;
1612                 }
1613
1614                 bmc150_accel_interrupts_setup(indio_dev, data);
1615
1616                 ret = bmc150_accel_triggers_setup(indio_dev, data);
1617                 if (ret)
1618                         goto err_buffer_cleanup;
1619
1620                 if (block_supported) {
1621                         indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1622                         indio_dev->info = &bmc150_accel_info_fifo;
1623                         iio_buffer_set_attrs(indio_dev->buffer,
1624                                              bmc150_accel_fifo_attributes);
1625                 }
1626         }
1627
1628         ret = pm_runtime_set_active(dev);
1629         if (ret)
1630                 goto err_trigger_unregister;
1631
1632         pm_runtime_enable(dev);
1633         pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1634         pm_runtime_use_autosuspend(dev);
1635
1636         ret = iio_device_register(indio_dev);
1637         if (ret < 0) {
1638                 dev_err(dev, "Unable to register iio device\n");
1639                 goto err_trigger_unregister;
1640         }
1641
1642         return 0;
1643
1644 err_trigger_unregister:
1645         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1646 err_buffer_cleanup:
1647         iio_triggered_buffer_cleanup(indio_dev);
1648
1649         return ret;
1650 }
1651 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1652
1653 int bmc150_accel_core_remove(struct device *dev)
1654 {
1655         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1656         struct bmc150_accel_data *data = iio_priv(indio_dev);
1657
1658         iio_device_unregister(indio_dev);
1659
1660         pm_runtime_disable(dev);
1661         pm_runtime_set_suspended(dev);
1662         pm_runtime_put_noidle(dev);
1663
1664         bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1665
1666         iio_triggered_buffer_cleanup(indio_dev);
1667
1668         mutex_lock(&data->mutex);
1669         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1670         mutex_unlock(&data->mutex);
1671
1672         return 0;
1673 }
1674 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1675
1676 #ifdef CONFIG_PM_SLEEP
1677 static int bmc150_accel_suspend(struct device *dev)
1678 {
1679         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1680         struct bmc150_accel_data *data = iio_priv(indio_dev);
1681
1682         mutex_lock(&data->mutex);
1683         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1684         mutex_unlock(&data->mutex);
1685
1686         return 0;
1687 }
1688
1689 static int bmc150_accel_resume(struct device *dev)
1690 {
1691         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1692         struct bmc150_accel_data *data = iio_priv(indio_dev);
1693
1694         mutex_lock(&data->mutex);
1695         bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1696         bmc150_accel_fifo_set_mode(data);
1697         mutex_unlock(&data->mutex);
1698
1699         return 0;
1700 }
1701 #endif
1702
1703 #ifdef CONFIG_PM
1704 static int bmc150_accel_runtime_suspend(struct device *dev)
1705 {
1706         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1707         struct bmc150_accel_data *data = iio_priv(indio_dev);
1708         int ret;
1709
1710         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1711         if (ret < 0)
1712                 return -EAGAIN;
1713
1714         return 0;
1715 }
1716
1717 static int bmc150_accel_runtime_resume(struct device *dev)
1718 {
1719         struct iio_dev *indio_dev = dev_get_drvdata(dev);
1720         struct bmc150_accel_data *data = iio_priv(indio_dev);
1721         int ret;
1722         int sleep_val;
1723
1724         ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1725         if (ret < 0)
1726                 return ret;
1727         ret = bmc150_accel_fifo_set_mode(data);
1728         if (ret < 0)
1729                 return ret;
1730
1731         sleep_val = bmc150_accel_get_startup_times(data);
1732         if (sleep_val < 20)
1733                 usleep_range(sleep_val * 1000, 20000);
1734         else
1735                 msleep_interruptible(sleep_val);
1736
1737         return 0;
1738 }
1739 #endif
1740
1741 const struct dev_pm_ops bmc150_accel_pm_ops = {
1742         SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1743         SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1744                            bmc150_accel_runtime_resume, NULL)
1745 };
1746 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1747
1748 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1749 MODULE_LICENSE("GPL v2");
1750 MODULE_DESCRIPTION("BMC150 accelerometer driver");