2 * 3-axis accelerometer driver supporting following Bosch-Sensortec chips:
10 * Copyright (c) 2014, Intel Corporation.
12 * This program is free software; you can redistribute it and/or modify it
13 * under the terms and conditions of the GNU General Public License,
14 * version 2, as published by the Free Software Foundation.
16 * This program is distributed in the hope it will be useful, but WITHOUT
17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
22 #include <linux/module.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
25 #include <linux/delay.h>
26 #include <linux/slab.h>
27 #include <linux/acpi.h>
29 #include <linux/pm_runtime.h>
30 #include <linux/iio/iio.h>
31 #include <linux/iio/sysfs.h>
32 #include <linux/iio/buffer.h>
33 #include <linux/iio/events.h>
34 #include <linux/iio/trigger.h>
35 #include <linux/iio/trigger_consumer.h>
36 #include <linux/iio/triggered_buffer.h>
37 #include <linux/regmap.h>
39 #include "bmc150-accel.h"
41 #define BMC150_ACCEL_DRV_NAME "bmc150_accel"
42 #define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
44 #define BMC150_ACCEL_REG_CHIP_ID 0x00
46 #define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
47 #define BMC150_ACCEL_ANY_MOTION_MASK 0x07
48 #define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
49 #define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
50 #define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
51 #define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
53 #define BMC150_ACCEL_REG_PMU_LPW 0x11
54 #define BMC150_ACCEL_PMU_MODE_MASK 0xE0
55 #define BMC150_ACCEL_PMU_MODE_SHIFT 5
56 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
57 #define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
59 #define BMC150_ACCEL_REG_PMU_RANGE 0x0F
61 #define BMC150_ACCEL_DEF_RANGE_2G 0x03
62 #define BMC150_ACCEL_DEF_RANGE_4G 0x05
63 #define BMC150_ACCEL_DEF_RANGE_8G 0x08
64 #define BMC150_ACCEL_DEF_RANGE_16G 0x0C
66 /* Default BW: 125Hz */
67 #define BMC150_ACCEL_REG_PMU_BW 0x10
68 #define BMC150_ACCEL_DEF_BW 125
70 #define BMC150_ACCEL_REG_RESET 0x14
71 #define BMC150_ACCEL_RESET_VAL 0xB6
73 #define BMC150_ACCEL_REG_INT_MAP_0 0x19
74 #define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
76 #define BMC150_ACCEL_REG_INT_MAP_1 0x1A
77 #define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
78 #define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
79 #define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
81 #define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
82 #define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
83 #define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
84 #define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
86 #define BMC150_ACCEL_REG_INT_EN_0 0x16
87 #define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
88 #define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
89 #define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
91 #define BMC150_ACCEL_REG_INT_EN_1 0x17
92 #define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
93 #define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
94 #define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
96 #define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
97 #define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
99 #define BMC150_ACCEL_REG_INT_5 0x27
100 #define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
102 #define BMC150_ACCEL_REG_INT_6 0x28
103 #define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
105 /* Slope duration in terms of number of samples */
106 #define BMC150_ACCEL_DEF_SLOPE_DURATION 1
107 /* in terms of multiples of g's/LSB, based on range */
108 #define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
110 #define BMC150_ACCEL_REG_XOUT_L 0x02
112 #define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
114 /* Sleep Duration values */
115 #define BMC150_ACCEL_SLEEP_500_MICRO 0x05
116 #define BMC150_ACCEL_SLEEP_1_MS 0x06
117 #define BMC150_ACCEL_SLEEP_2_MS 0x07
118 #define BMC150_ACCEL_SLEEP_4_MS 0x08
119 #define BMC150_ACCEL_SLEEP_6_MS 0x09
120 #define BMC150_ACCEL_SLEEP_10_MS 0x0A
121 #define BMC150_ACCEL_SLEEP_25_MS 0x0B
122 #define BMC150_ACCEL_SLEEP_50_MS 0x0C
123 #define BMC150_ACCEL_SLEEP_100_MS 0x0D
124 #define BMC150_ACCEL_SLEEP_500_MS 0x0E
125 #define BMC150_ACCEL_SLEEP_1_SEC 0x0F
127 #define BMC150_ACCEL_REG_TEMP 0x08
128 #define BMC150_ACCEL_TEMP_CENTER_VAL 23
130 #define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
131 #define BMC150_AUTO_SUSPEND_DELAY_MS 2000
133 #define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
134 #define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
135 #define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
136 #define BMC150_ACCEL_REG_FIFO_DATA 0x3F
137 #define BMC150_ACCEL_FIFO_LENGTH 32
139 enum bmc150_accel_axis {
146 enum bmc150_power_modes {
147 BMC150_ACCEL_SLEEP_MODE_NORMAL,
148 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
149 BMC150_ACCEL_SLEEP_MODE_LPM,
150 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
153 struct bmc150_scale_info {
158 struct bmc150_accel_chip_info {
161 const struct iio_chan_spec *channels;
163 const struct bmc150_scale_info scale_table[4];
166 struct bmc150_accel_interrupt {
167 const struct bmc150_accel_interrupt_info *info;
171 struct bmc150_accel_trigger {
172 struct bmc150_accel_data *data;
173 struct iio_trigger *indio_trig;
174 int (*setup)(struct bmc150_accel_trigger *t, bool state);
179 enum bmc150_accel_interrupt_id {
180 BMC150_ACCEL_INT_DATA_READY,
181 BMC150_ACCEL_INT_ANY_MOTION,
182 BMC150_ACCEL_INT_WATERMARK,
183 BMC150_ACCEL_INTERRUPTS,
186 enum bmc150_accel_trigger_id {
187 BMC150_ACCEL_TRIGGER_DATA_READY,
188 BMC150_ACCEL_TRIGGER_ANY_MOTION,
189 BMC150_ACCEL_TRIGGERS,
192 struct bmc150_accel_data {
193 struct regmap *regmap;
195 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
196 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
198 u8 fifo_mode, watermark;
201 * Ensure there is sufficient space and correct alignment for
202 * the timestamp if enabled
213 int64_t timestamp, old_timestamp; /* Only used in hw fifo mode. */
214 const struct bmc150_accel_chip_info *chip_info;
217 static const struct {
221 } bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
230 static const struct {
233 } bmc150_accel_sample_upd_time[] = { {0x08, 64},
242 static const struct {
245 } bmc150_accel_sleep_value_table[] = { {0, 0},
246 {500, BMC150_ACCEL_SLEEP_500_MICRO},
247 {1000, BMC150_ACCEL_SLEEP_1_MS},
248 {2000, BMC150_ACCEL_SLEEP_2_MS},
249 {4000, BMC150_ACCEL_SLEEP_4_MS},
250 {6000, BMC150_ACCEL_SLEEP_6_MS},
251 {10000, BMC150_ACCEL_SLEEP_10_MS},
252 {25000, BMC150_ACCEL_SLEEP_25_MS},
253 {50000, BMC150_ACCEL_SLEEP_50_MS},
254 {100000, BMC150_ACCEL_SLEEP_100_MS},
255 {500000, BMC150_ACCEL_SLEEP_500_MS},
256 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
258 const struct regmap_config bmc150_regmap_conf = {
261 .max_register = 0x3f,
263 EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
265 static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
266 enum bmc150_power_modes mode,
269 struct device *dev = regmap_get_device(data->regmap);
276 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
278 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
281 bmc150_accel_sleep_value_table[i].reg_value;
290 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
291 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
293 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
295 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
297 dev_err(dev, "Error writing reg_pmu_lpw\n");
304 static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
310 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
311 if (bmc150_accel_samp_freq_table[i].val == val &&
312 bmc150_accel_samp_freq_table[i].val2 == val2) {
313 ret = regmap_write(data->regmap,
314 BMC150_ACCEL_REG_PMU_BW,
315 bmc150_accel_samp_freq_table[i].bw_bits);
320 bmc150_accel_samp_freq_table[i].bw_bits;
328 static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
330 struct device *dev = regmap_get_device(data->regmap);
333 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
336 dev_err(dev, "Error writing reg_int_6\n");
340 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
341 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
343 dev_err(dev, "Error updating reg_int_5\n");
347 dev_dbg(dev, "%s: %x %x\n", __func__, data->slope_thres,
353 static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
357 return bmc150_accel_update_slope(t->data);
362 static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
367 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
368 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
369 *val = bmc150_accel_samp_freq_table[i].val;
370 *val2 = bmc150_accel_samp_freq_table[i].val2;
371 return IIO_VAL_INT_PLUS_MICRO;
379 static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
383 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
384 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
385 return bmc150_accel_sample_upd_time[i].msec;
388 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
391 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
393 struct device *dev = regmap_get_device(data->regmap);
397 ret = pm_runtime_get_sync(dev);
399 pm_runtime_mark_last_busy(dev);
400 ret = pm_runtime_put_autosuspend(dev);
405 "Failed: bmc150_accel_set_power_state for %d\n", on);
407 pm_runtime_put_noidle(dev);
415 static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
421 static const struct bmc150_accel_interrupt_info {
426 } bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
427 { /* data ready interrupt */
428 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
429 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
430 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
431 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
433 { /* motion interrupt */
434 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
435 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
436 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
437 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
438 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
439 BMC150_ACCEL_INT_EN_BIT_SLP_Z
441 { /* fifo watermark interrupt */
442 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
443 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
444 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
445 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
449 static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
450 struct bmc150_accel_data *data)
454 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
455 data->interrupts[i].info = &bmc150_accel_interrupts[i];
458 static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
461 struct device *dev = regmap_get_device(data->regmap);
462 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
463 const struct bmc150_accel_interrupt_info *info = intr->info;
467 if (atomic_inc_return(&intr->users) > 1)
470 if (atomic_dec_return(&intr->users) > 0)
475 * We will expect the enable and disable to do operation in reverse
476 * order. This will happen here anyway, as our resume operation uses
477 * sync mode runtime pm calls. The suspend operation will be delayed
478 * by autosuspend delay.
479 * So the disable operation will still happen in reverse order of
480 * enable operation. When runtime pm is disabled the mode is always on,
481 * so sequence doesn't matter.
483 ret = bmc150_accel_set_power_state(data, state);
487 /* map the interrupt to the appropriate pins */
488 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
489 (state ? info->map_bitmask : 0));
491 dev_err(dev, "Error updating reg_int_map\n");
492 goto out_fix_power_state;
495 /* enable/disable the interrupt */
496 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
497 (state ? info->en_bitmask : 0));
499 dev_err(dev, "Error updating reg_int_en\n");
500 goto out_fix_power_state;
506 bmc150_accel_set_power_state(data, false);
510 static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
512 struct device *dev = regmap_get_device(data->regmap);
515 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
516 if (data->chip_info->scale_table[i].scale == val) {
517 ret = regmap_write(data->regmap,
518 BMC150_ACCEL_REG_PMU_RANGE,
519 data->chip_info->scale_table[i].reg_range);
521 dev_err(dev, "Error writing pmu_range\n");
525 data->range = data->chip_info->scale_table[i].reg_range;
533 static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
535 struct device *dev = regmap_get_device(data->regmap);
539 mutex_lock(&data->mutex);
541 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
543 dev_err(dev, "Error reading reg_temp\n");
544 mutex_unlock(&data->mutex);
547 *val = sign_extend32(value, 7);
549 mutex_unlock(&data->mutex);
554 static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
555 struct iio_chan_spec const *chan,
558 struct device *dev = regmap_get_device(data->regmap);
560 int axis = chan->scan_index;
563 mutex_lock(&data->mutex);
564 ret = bmc150_accel_set_power_state(data, true);
566 mutex_unlock(&data->mutex);
570 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
571 &raw_val, sizeof(raw_val));
573 dev_err(dev, "Error reading axis %d\n", axis);
574 bmc150_accel_set_power_state(data, false);
575 mutex_unlock(&data->mutex);
578 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
579 chan->scan_type.realbits - 1);
580 ret = bmc150_accel_set_power_state(data, false);
581 mutex_unlock(&data->mutex);
588 static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
589 struct iio_chan_spec const *chan,
590 int *val, int *val2, long mask)
592 struct bmc150_accel_data *data = iio_priv(indio_dev);
596 case IIO_CHAN_INFO_RAW:
597 switch (chan->type) {
599 return bmc150_accel_get_temp(data, val);
601 if (iio_buffer_enabled(indio_dev))
604 return bmc150_accel_get_axis(data, chan, val);
608 case IIO_CHAN_INFO_OFFSET:
609 if (chan->type == IIO_TEMP) {
610 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
615 case IIO_CHAN_INFO_SCALE:
617 switch (chan->type) {
620 return IIO_VAL_INT_PLUS_MICRO;
624 const struct bmc150_scale_info *si;
625 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
627 for (i = 0; i < st_size; ++i) {
628 si = &data->chip_info->scale_table[i];
629 if (si->reg_range == data->range) {
631 return IIO_VAL_INT_PLUS_MICRO;
639 case IIO_CHAN_INFO_SAMP_FREQ:
640 mutex_lock(&data->mutex);
641 ret = bmc150_accel_get_bw(data, val, val2);
642 mutex_unlock(&data->mutex);
649 static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
650 struct iio_chan_spec const *chan,
651 int val, int val2, long mask)
653 struct bmc150_accel_data *data = iio_priv(indio_dev);
657 case IIO_CHAN_INFO_SAMP_FREQ:
658 mutex_lock(&data->mutex);
659 ret = bmc150_accel_set_bw(data, val, val2);
660 mutex_unlock(&data->mutex);
662 case IIO_CHAN_INFO_SCALE:
666 mutex_lock(&data->mutex);
667 ret = bmc150_accel_set_scale(data, val2);
668 mutex_unlock(&data->mutex);
677 static int bmc150_accel_read_event(struct iio_dev *indio_dev,
678 const struct iio_chan_spec *chan,
679 enum iio_event_type type,
680 enum iio_event_direction dir,
681 enum iio_event_info info,
684 struct bmc150_accel_data *data = iio_priv(indio_dev);
688 case IIO_EV_INFO_VALUE:
689 *val = data->slope_thres;
691 case IIO_EV_INFO_PERIOD:
692 *val = data->slope_dur;
701 static int bmc150_accel_write_event(struct iio_dev *indio_dev,
702 const struct iio_chan_spec *chan,
703 enum iio_event_type type,
704 enum iio_event_direction dir,
705 enum iio_event_info info,
708 struct bmc150_accel_data *data = iio_priv(indio_dev);
710 if (data->ev_enable_state)
714 case IIO_EV_INFO_VALUE:
715 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
717 case IIO_EV_INFO_PERIOD:
718 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
727 static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
728 const struct iio_chan_spec *chan,
729 enum iio_event_type type,
730 enum iio_event_direction dir)
732 struct bmc150_accel_data *data = iio_priv(indio_dev);
734 return data->ev_enable_state;
737 static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
738 const struct iio_chan_spec *chan,
739 enum iio_event_type type,
740 enum iio_event_direction dir,
743 struct bmc150_accel_data *data = iio_priv(indio_dev);
746 if (state == data->ev_enable_state)
749 mutex_lock(&data->mutex);
751 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
754 mutex_unlock(&data->mutex);
758 data->ev_enable_state = state;
759 mutex_unlock(&data->mutex);
764 static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
765 struct iio_trigger *trig)
767 struct bmc150_accel_data *data = iio_priv(indio_dev);
770 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
771 if (data->triggers[i].indio_trig == trig)
778 static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
779 struct device_attribute *attr,
782 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
783 struct bmc150_accel_data *data = iio_priv(indio_dev);
786 mutex_lock(&data->mutex);
787 wm = data->watermark;
788 mutex_unlock(&data->mutex);
790 return sprintf(buf, "%d\n", wm);
793 static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
794 struct device_attribute *attr,
797 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
798 struct bmc150_accel_data *data = iio_priv(indio_dev);
801 mutex_lock(&data->mutex);
802 state = data->fifo_mode;
803 mutex_unlock(&data->mutex);
805 return sprintf(buf, "%d\n", state);
808 static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
809 static IIO_CONST_ATTR(hwfifo_watermark_max,
810 __stringify(BMC150_ACCEL_FIFO_LENGTH));
811 static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
812 bmc150_accel_get_fifo_state, NULL, 0);
813 static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
814 bmc150_accel_get_fifo_watermark, NULL, 0);
816 static const struct attribute *bmc150_accel_fifo_attributes[] = {
817 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
818 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
819 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
820 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
824 static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
826 struct bmc150_accel_data *data = iio_priv(indio_dev);
828 if (val > BMC150_ACCEL_FIFO_LENGTH)
829 val = BMC150_ACCEL_FIFO_LENGTH;
831 mutex_lock(&data->mutex);
832 data->watermark = val;
833 mutex_unlock(&data->mutex);
839 * We must read at least one full frame in one burst, otherwise the rest of the
840 * frame data is discarded.
842 static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
843 char *buffer, int samples)
845 struct device *dev = regmap_get_device(data->regmap);
846 int sample_length = 3 * 2;
848 int total_length = samples * sample_length;
850 size_t step = regmap_get_raw_read_max(data->regmap);
852 if (!step || step > total_length)
854 else if (step < total_length)
855 step = sample_length;
858 * Seems we have a bus with size limitation so we have to execute
861 for (i = 0; i < total_length; i += step) {
862 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
870 "Error transferring data from fifo in single steps of %zu\n",
876 static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
877 unsigned samples, bool irq)
879 struct bmc150_accel_data *data = iio_priv(indio_dev);
880 struct device *dev = regmap_get_device(data->regmap);
883 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
885 uint64_t sample_period;
888 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
890 dev_err(dev, "Error reading reg_fifo_status\n");
900 * If we getting called from IRQ handler we know the stored timestamp is
901 * fairly accurate for the last stored sample. Otherwise, if we are
902 * called as a result of a read operation from userspace and hence
903 * before the watermark interrupt was triggered, take a timestamp
904 * now. We can fall anywhere in between two samples so the error in this
905 * case is at most one sample period.
908 data->old_timestamp = data->timestamp;
909 data->timestamp = iio_get_time_ns(indio_dev);
913 * Approximate timestamps for each of the sample based on the sampling
914 * frequency, timestamp for last sample and number of samples.
916 * Note that we can't use the current bandwidth settings to compute the
917 * sample period because the sample rate varies with the device
918 * (e.g. between 31.70ms to 32.20ms for a bandwidth of 15.63HZ). That
919 * small variation adds when we store a large number of samples and
920 * creates significant jitter between the last and first samples in
921 * different batches (e.g. 32ms vs 21ms).
923 * To avoid this issue we compute the actual sample period ourselves
924 * based on the timestamp delta between the last two flush operations.
926 sample_period = (data->timestamp - data->old_timestamp);
927 do_div(sample_period, count);
928 tstamp = data->timestamp - (count - 1) * sample_period;
930 if (samples && count > samples)
933 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
938 * Ideally we want the IIO core to handle the demux when running in fifo
939 * mode but not when running in triggered buffer mode. Unfortunately
940 * this does not seem to be possible, so stick with driver demux for
943 for (i = 0; i < count; i++) {
947 for_each_set_bit(bit, indio_dev->active_scan_mask,
948 indio_dev->masklength)
949 memcpy(&data->scan.channels[j++], &buffer[i * 3 + bit],
950 sizeof(data->scan.channels[0]));
952 iio_push_to_buffers_with_timestamp(indio_dev, &data->scan,
955 tstamp += sample_period;
961 static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
963 struct bmc150_accel_data *data = iio_priv(indio_dev);
966 mutex_lock(&data->mutex);
967 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
968 mutex_unlock(&data->mutex);
973 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
974 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
976 static struct attribute *bmc150_accel_attributes[] = {
977 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
981 static const struct attribute_group bmc150_accel_attrs_group = {
982 .attrs = bmc150_accel_attributes,
985 static const struct iio_event_spec bmc150_accel_event = {
986 .type = IIO_EV_TYPE_ROC,
987 .dir = IIO_EV_DIR_EITHER,
988 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
989 BIT(IIO_EV_INFO_ENABLE) |
990 BIT(IIO_EV_INFO_PERIOD)
993 #define BMC150_ACCEL_CHANNEL(_axis, bits) { \
996 .channel2 = IIO_MOD_##_axis, \
997 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
998 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
999 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
1000 .scan_index = AXIS_##_axis, \
1003 .realbits = (bits), \
1004 .storagebits = 16, \
1005 .shift = 16 - (bits), \
1006 .endianness = IIO_LE, \
1008 .event_spec = &bmc150_accel_event, \
1009 .num_event_specs = 1 \
1012 #define BMC150_ACCEL_CHANNELS(bits) { \
1015 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1016 BIT(IIO_CHAN_INFO_SCALE) | \
1017 BIT(IIO_CHAN_INFO_OFFSET), \
1020 BMC150_ACCEL_CHANNEL(X, bits), \
1021 BMC150_ACCEL_CHANNEL(Y, bits), \
1022 BMC150_ACCEL_CHANNEL(Z, bits), \
1023 IIO_CHAN_SOFT_TIMESTAMP(3), \
1026 static const struct iio_chan_spec bma222e_accel_channels[] =
1027 BMC150_ACCEL_CHANNELS(8);
1028 static const struct iio_chan_spec bma250e_accel_channels[] =
1029 BMC150_ACCEL_CHANNELS(10);
1030 static const struct iio_chan_spec bmc150_accel_channels[] =
1031 BMC150_ACCEL_CHANNELS(12);
1032 static const struct iio_chan_spec bma280_accel_channels[] =
1033 BMC150_ACCEL_CHANNELS(14);
1035 static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1039 .channels = bmc150_accel_channels,
1040 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1041 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1042 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1043 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1044 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1049 .channels = bmc150_accel_channels,
1050 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1051 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1052 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1053 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1054 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1059 .channels = bmc150_accel_channels,
1060 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1061 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1062 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1063 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1064 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1069 .channels = bma250e_accel_channels,
1070 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1071 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1072 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1073 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1074 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1079 .channels = bma222e_accel_channels,
1080 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1081 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1082 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1083 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1084 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1089 .channels = bma280_accel_channels,
1090 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1091 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1092 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1093 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1094 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1098 static const struct iio_info bmc150_accel_info = {
1099 .attrs = &bmc150_accel_attrs_group,
1100 .read_raw = bmc150_accel_read_raw,
1101 .write_raw = bmc150_accel_write_raw,
1102 .read_event_value = bmc150_accel_read_event,
1103 .write_event_value = bmc150_accel_write_event,
1104 .write_event_config = bmc150_accel_write_event_config,
1105 .read_event_config = bmc150_accel_read_event_config,
1106 .driver_module = THIS_MODULE,
1109 static const struct iio_info bmc150_accel_info_fifo = {
1110 .attrs = &bmc150_accel_attrs_group,
1111 .read_raw = bmc150_accel_read_raw,
1112 .write_raw = bmc150_accel_write_raw,
1113 .read_event_value = bmc150_accel_read_event,
1114 .write_event_value = bmc150_accel_write_event,
1115 .write_event_config = bmc150_accel_write_event_config,
1116 .read_event_config = bmc150_accel_read_event_config,
1117 .validate_trigger = bmc150_accel_validate_trigger,
1118 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1119 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1120 .driver_module = THIS_MODULE,
1123 static const unsigned long bmc150_accel_scan_masks[] = {
1124 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1127 static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1129 struct iio_poll_func *pf = p;
1130 struct iio_dev *indio_dev = pf->indio_dev;
1131 struct bmc150_accel_data *data = iio_priv(indio_dev);
1134 mutex_lock(&data->mutex);
1135 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1136 data->buffer, AXIS_MAX * 2);
1137 mutex_unlock(&data->mutex);
1141 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1144 iio_trigger_notify_done(indio_dev->trig);
1149 static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1151 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1152 struct bmc150_accel_data *data = t->data;
1153 struct device *dev = regmap_get_device(data->regmap);
1156 /* new data interrupts don't need ack */
1157 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1160 mutex_lock(&data->mutex);
1161 /* clear any latched interrupt */
1162 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1163 BMC150_ACCEL_INT_MODE_LATCH_INT |
1164 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1165 mutex_unlock(&data->mutex);
1167 dev_err(dev, "Error writing reg_int_rst_latch\n");
1174 static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1177 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1178 struct bmc150_accel_data *data = t->data;
1181 mutex_lock(&data->mutex);
1183 if (t->enabled == state) {
1184 mutex_unlock(&data->mutex);
1189 ret = t->setup(t, state);
1191 mutex_unlock(&data->mutex);
1196 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1198 mutex_unlock(&data->mutex);
1204 mutex_unlock(&data->mutex);
1209 static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1210 .set_trigger_state = bmc150_accel_trigger_set_state,
1211 .try_reenable = bmc150_accel_trig_try_reen,
1212 .owner = THIS_MODULE,
1215 static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1217 struct bmc150_accel_data *data = iio_priv(indio_dev);
1218 struct device *dev = regmap_get_device(data->regmap);
1223 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1225 dev_err(dev, "Error reading reg_int_status_2\n");
1229 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1230 dir = IIO_EV_DIR_FALLING;
1232 dir = IIO_EV_DIR_RISING;
1234 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1235 iio_push_event(indio_dev,
1236 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1243 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1244 iio_push_event(indio_dev,
1245 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1252 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1253 iio_push_event(indio_dev,
1254 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1264 static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1266 struct iio_dev *indio_dev = private;
1267 struct bmc150_accel_data *data = iio_priv(indio_dev);
1268 struct device *dev = regmap_get_device(data->regmap);
1272 mutex_lock(&data->mutex);
1274 if (data->fifo_mode) {
1275 ret = __bmc150_accel_fifo_flush(indio_dev,
1276 BMC150_ACCEL_FIFO_LENGTH, true);
1281 if (data->ev_enable_state) {
1282 ret = bmc150_accel_handle_roc_event(indio_dev);
1288 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1289 BMC150_ACCEL_INT_MODE_LATCH_INT |
1290 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1292 dev_err(dev, "Error writing reg_int_rst_latch\n");
1299 mutex_unlock(&data->mutex);
1304 static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1306 struct iio_dev *indio_dev = private;
1307 struct bmc150_accel_data *data = iio_priv(indio_dev);
1311 data->old_timestamp = data->timestamp;
1312 data->timestamp = iio_get_time_ns(indio_dev);
1314 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1315 if (data->triggers[i].enabled) {
1316 iio_trigger_poll(data->triggers[i].indio_trig);
1322 if (data->ev_enable_state || data->fifo_mode)
1323 return IRQ_WAKE_THREAD;
1331 static const struct {
1334 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1335 } bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1342 .name = "%s-any-motion-dev%d",
1343 .setup = bmc150_accel_any_motion_setup,
1347 static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1352 for (i = from; i >= 0; i--) {
1353 if (data->triggers[i].indio_trig) {
1354 iio_trigger_unregister(data->triggers[i].indio_trig);
1355 data->triggers[i].indio_trig = NULL;
1360 static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1361 struct bmc150_accel_data *data)
1363 struct device *dev = regmap_get_device(data->regmap);
1366 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1367 struct bmc150_accel_trigger *t = &data->triggers[i];
1369 t->indio_trig = devm_iio_trigger_alloc(dev,
1370 bmc150_accel_triggers[i].name,
1373 if (!t->indio_trig) {
1378 t->indio_trig->dev.parent = dev;
1379 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1380 t->intr = bmc150_accel_triggers[i].intr;
1382 t->setup = bmc150_accel_triggers[i].setup;
1383 iio_trigger_set_drvdata(t->indio_trig, t);
1385 ret = iio_trigger_register(t->indio_trig);
1391 bmc150_accel_unregister_triggers(data, i - 1);
1396 #define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1397 #define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1398 #define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1400 static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1402 struct device *dev = regmap_get_device(data->regmap);
1403 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1406 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1408 dev_err(dev, "Error writing reg_fifo_config1\n");
1412 if (!data->fifo_mode)
1415 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1418 dev_err(dev, "Error writing reg_fifo_config0\n");
1423 static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1425 struct bmc150_accel_data *data = iio_priv(indio_dev);
1427 return bmc150_accel_set_power_state(data, true);
1430 static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1432 struct bmc150_accel_data *data = iio_priv(indio_dev);
1435 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1436 return iio_triggered_buffer_postenable(indio_dev);
1438 mutex_lock(&data->mutex);
1440 if (!data->watermark)
1443 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1448 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1450 ret = bmc150_accel_fifo_set_mode(data);
1452 data->fifo_mode = 0;
1453 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1458 mutex_unlock(&data->mutex);
1463 static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1465 struct bmc150_accel_data *data = iio_priv(indio_dev);
1467 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1468 return iio_triggered_buffer_predisable(indio_dev);
1470 mutex_lock(&data->mutex);
1472 if (!data->fifo_mode)
1475 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1476 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1477 data->fifo_mode = 0;
1478 bmc150_accel_fifo_set_mode(data);
1481 mutex_unlock(&data->mutex);
1486 static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1488 struct bmc150_accel_data *data = iio_priv(indio_dev);
1490 return bmc150_accel_set_power_state(data, false);
1493 static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1494 .preenable = bmc150_accel_buffer_preenable,
1495 .postenable = bmc150_accel_buffer_postenable,
1496 .predisable = bmc150_accel_buffer_predisable,
1497 .postdisable = bmc150_accel_buffer_postdisable,
1500 static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1502 struct device *dev = regmap_get_device(data->regmap);
1507 * Reset chip to get it in a known good state. A delay of 1.8ms after
1508 * reset is required according to the data sheets of supported chips.
1510 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1511 BMC150_ACCEL_RESET_VAL);
1512 usleep_range(1800, 2500);
1514 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1516 dev_err(dev, "Error: Reading chip id\n");
1520 dev_dbg(dev, "Chip Id %x\n", val);
1521 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1522 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1523 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1528 if (!data->chip_info) {
1529 dev_err(dev, "Invalid chip %x\n", val);
1533 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1538 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1542 /* Set Default Range */
1543 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1544 BMC150_ACCEL_DEF_RANGE_4G);
1546 dev_err(dev, "Error writing reg_pmu_range\n");
1550 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1552 /* Set default slope duration and thresholds */
1553 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1554 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1555 ret = bmc150_accel_update_slope(data);
1559 /* Set default as latched interrupts */
1560 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1561 BMC150_ACCEL_INT_MODE_LATCH_INT |
1562 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1564 dev_err(dev, "Error writing reg_int_rst_latch\n");
1571 int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1572 const char *name, bool block_supported)
1574 struct bmc150_accel_data *data;
1575 struct iio_dev *indio_dev;
1578 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1582 data = iio_priv(indio_dev);
1583 dev_set_drvdata(dev, indio_dev);
1586 data->regmap = regmap;
1588 ret = bmc150_accel_chip_init(data);
1592 mutex_init(&data->mutex);
1594 indio_dev->dev.parent = dev;
1595 indio_dev->channels = data->chip_info->channels;
1596 indio_dev->num_channels = data->chip_info->num_channels;
1597 indio_dev->name = name ? name : data->chip_info->name;
1598 indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1599 indio_dev->modes = INDIO_DIRECT_MODE;
1600 indio_dev->info = &bmc150_accel_info;
1602 ret = iio_triggered_buffer_setup(indio_dev,
1603 &iio_pollfunc_store_time,
1604 bmc150_accel_trigger_handler,
1605 &bmc150_accel_buffer_ops);
1607 dev_err(dev, "Failed: iio triggered buffer setup\n");
1611 if (data->irq > 0) {
1612 ret = devm_request_threaded_irq(
1614 bmc150_accel_irq_handler,
1615 bmc150_accel_irq_thread_handler,
1616 IRQF_TRIGGER_RISING,
1617 BMC150_ACCEL_IRQ_NAME,
1620 goto err_buffer_cleanup;
1623 * Set latched mode interrupt. While certain interrupts are
1624 * non-latched regardless of this settings (e.g. new data) we
1625 * want to use latch mode when we can to prevent interrupt
1628 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1629 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1631 dev_err(dev, "Error writing reg_int_rst_latch\n");
1632 goto err_buffer_cleanup;
1635 bmc150_accel_interrupts_setup(indio_dev, data);
1637 ret = bmc150_accel_triggers_setup(indio_dev, data);
1639 goto err_buffer_cleanup;
1641 if (block_supported) {
1642 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1643 indio_dev->info = &bmc150_accel_info_fifo;
1644 indio_dev->buffer->attrs = bmc150_accel_fifo_attributes;
1648 ret = pm_runtime_set_active(dev);
1650 goto err_trigger_unregister;
1652 pm_runtime_enable(dev);
1653 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1654 pm_runtime_use_autosuspend(dev);
1656 ret = iio_device_register(indio_dev);
1658 dev_err(dev, "Unable to register iio device\n");
1659 goto err_trigger_unregister;
1664 err_trigger_unregister:
1665 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1667 iio_triggered_buffer_cleanup(indio_dev);
1671 EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1673 int bmc150_accel_core_remove(struct device *dev)
1675 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1676 struct bmc150_accel_data *data = iio_priv(indio_dev);
1678 iio_device_unregister(indio_dev);
1680 pm_runtime_disable(dev);
1681 pm_runtime_set_suspended(dev);
1682 pm_runtime_put_noidle(dev);
1684 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1686 iio_triggered_buffer_cleanup(indio_dev);
1688 mutex_lock(&data->mutex);
1689 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1690 mutex_unlock(&data->mutex);
1694 EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1696 #ifdef CONFIG_PM_SLEEP
1697 static int bmc150_accel_suspend(struct device *dev)
1699 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1700 struct bmc150_accel_data *data = iio_priv(indio_dev);
1702 mutex_lock(&data->mutex);
1703 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1704 mutex_unlock(&data->mutex);
1709 static int bmc150_accel_resume(struct device *dev)
1711 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1712 struct bmc150_accel_data *data = iio_priv(indio_dev);
1714 mutex_lock(&data->mutex);
1715 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1716 bmc150_accel_fifo_set_mode(data);
1717 mutex_unlock(&data->mutex);
1724 static int bmc150_accel_runtime_suspend(struct device *dev)
1726 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1727 struct bmc150_accel_data *data = iio_priv(indio_dev);
1730 dev_dbg(dev, __func__);
1731 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1738 static int bmc150_accel_runtime_resume(struct device *dev)
1740 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1741 struct bmc150_accel_data *data = iio_priv(indio_dev);
1745 dev_dbg(dev, __func__);
1747 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1750 ret = bmc150_accel_fifo_set_mode(data);
1754 sleep_val = bmc150_accel_get_startup_times(data);
1756 usleep_range(sleep_val * 1000, 20000);
1758 msleep_interruptible(sleep_val);
1764 const struct dev_pm_ops bmc150_accel_pm_ops = {
1765 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1766 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1767 bmc150_accel_runtime_resume, NULL)
1769 EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1771 MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1772 MODULE_LICENSE("GPL v2");
1773 MODULE_DESCRIPTION("BMC150 accelerometer driver");