1 // SPDX-License-Identifier: GPL-2.0-only
3 * ADXL345 3-Axis Digital Accelerometer IIO core driver
5 * Copyright (c) 2017 Eva Rachel Retuya <eraretuya@gmail.com>
7 * Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADXL345.pdf
10 #include <linux/module.h>
11 #include <linux/property.h>
12 #include <linux/regmap.h>
13 #include <linux/units.h>
15 #include <linux/iio/iio.h>
16 #include <linux/iio/sysfs.h>
20 #define ADXL345_REG_DEVID 0x00
21 #define ADXL345_REG_OFSX 0x1e
22 #define ADXL345_REG_OFSY 0x1f
23 #define ADXL345_REG_OFSZ 0x20
24 #define ADXL345_REG_OFS_AXIS(index) (ADXL345_REG_OFSX + (index))
25 #define ADXL345_REG_BW_RATE 0x2C
26 #define ADXL345_REG_POWER_CTL 0x2D
27 #define ADXL345_REG_DATA_FORMAT 0x31
28 #define ADXL345_REG_DATAX0 0x32
29 #define ADXL345_REG_DATAY0 0x34
30 #define ADXL345_REG_DATAZ0 0x36
31 #define ADXL345_REG_DATA_AXIS(index) \
32 (ADXL345_REG_DATAX0 + (index) * sizeof(__le16))
34 #define ADXL345_BW_RATE GENMASK(3, 0)
35 #define ADXL345_BASE_RATE_NANO_HZ 97656250LL
37 #define ADXL345_POWER_CTL_MEASURE BIT(3)
38 #define ADXL345_POWER_CTL_STANDBY 0x00
40 #define ADXL345_DATA_FORMAT_FULL_RES BIT(3) /* Up to 13-bits resolution */
41 #define ADXL345_DATA_FORMAT_2G 0
42 #define ADXL345_DATA_FORMAT_4G 1
43 #define ADXL345_DATA_FORMAT_8G 2
44 #define ADXL345_DATA_FORMAT_16G 3
46 #define ADXL345_DEVID 0xE5
49 const struct adxl345_chip_info *info;
50 struct regmap *regmap;
54 #define ADXL345_CHANNEL(index, axis) { \
57 .channel2 = IIO_MOD_##axis, \
59 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
60 BIT(IIO_CHAN_INFO_CALIBBIAS), \
61 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
62 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
65 static const struct iio_chan_spec adxl345_channels[] = {
66 ADXL345_CHANNEL(0, X),
67 ADXL345_CHANNEL(1, Y),
68 ADXL345_CHANNEL(2, Z),
71 static int adxl345_read_raw(struct iio_dev *indio_dev,
72 struct iio_chan_spec const *chan,
73 int *val, int *val2, long mask)
75 struct adxl345_data *data = iio_priv(indio_dev);
77 long long samp_freq_nhz;
82 case IIO_CHAN_INFO_RAW:
84 * Data is stored in adjacent registers:
85 * ADXL345_REG_DATA(X0/Y0/Z0) contain the least significant byte
86 * and ADXL345_REG_DATA(X0/Y0/Z0) + 1 the most significant byte
88 ret = regmap_bulk_read(data->regmap,
89 ADXL345_REG_DATA_AXIS(chan->address),
90 &accel, sizeof(accel));
94 *val = sign_extend32(le16_to_cpu(accel), 12);
96 case IIO_CHAN_INFO_SCALE:
98 *val2 = data->info->uscale;
99 return IIO_VAL_INT_PLUS_MICRO;
100 case IIO_CHAN_INFO_CALIBBIAS:
101 ret = regmap_read(data->regmap,
102 ADXL345_REG_OFS_AXIS(chan->address), ®val);
106 * 8-bit resolution at +/- 2g, that is 4x accel data scale
109 *val = sign_extend32(regval, 7) * 4;
112 case IIO_CHAN_INFO_SAMP_FREQ:
113 ret = regmap_read(data->regmap, ADXL345_REG_BW_RATE, ®val);
117 samp_freq_nhz = ADXL345_BASE_RATE_NANO_HZ <<
118 (regval & ADXL345_BW_RATE);
119 *val = div_s64_rem(samp_freq_nhz, NANOHZ_PER_HZ, val2);
121 return IIO_VAL_INT_PLUS_NANO;
127 static int adxl345_write_raw(struct iio_dev *indio_dev,
128 struct iio_chan_spec const *chan,
129 int val, int val2, long mask)
131 struct adxl345_data *data = iio_priv(indio_dev);
135 case IIO_CHAN_INFO_CALIBBIAS:
137 * 8-bit resolution at +/- 2g, that is 4x accel data scale
140 return regmap_write(data->regmap,
141 ADXL345_REG_OFS_AXIS(chan->address),
143 case IIO_CHAN_INFO_SAMP_FREQ:
144 n = div_s64(val * NANOHZ_PER_HZ + val2,
145 ADXL345_BASE_RATE_NANO_HZ);
147 return regmap_update_bits(data->regmap, ADXL345_REG_BW_RATE,
149 clamp_val(ilog2(n), 0,
156 static int adxl345_write_raw_get_fmt(struct iio_dev *indio_dev,
157 struct iio_chan_spec const *chan,
161 case IIO_CHAN_INFO_CALIBBIAS:
163 case IIO_CHAN_INFO_SAMP_FREQ:
164 return IIO_VAL_INT_PLUS_NANO;
170 static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
171 "0.09765625 0.1953125 0.390625 0.78125 1.5625 3.125 6.25 12.5 25 50 100 200 400 800 1600 3200"
174 static struct attribute *adxl345_attrs[] = {
175 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
179 static const struct attribute_group adxl345_attrs_group = {
180 .attrs = adxl345_attrs,
183 static const struct iio_info adxl345_info = {
184 .attrs = &adxl345_attrs_group,
185 .read_raw = adxl345_read_raw,
186 .write_raw = adxl345_write_raw,
187 .write_raw_get_fmt = adxl345_write_raw_get_fmt,
190 static int adxl345_powerup(void *regmap)
192 return regmap_write(regmap, ADXL345_REG_POWER_CTL, ADXL345_POWER_CTL_MEASURE);
195 static void adxl345_powerdown(void *regmap)
197 regmap_write(regmap, ADXL345_REG_POWER_CTL, ADXL345_POWER_CTL_STANDBY);
200 int adxl345_core_probe(struct device *dev, struct regmap *regmap)
202 struct adxl345_data *data;
203 struct iio_dev *indio_dev;
207 ret = regmap_read(regmap, ADXL345_REG_DEVID, ®val);
209 return dev_err_probe(dev, ret, "Error reading device ID\n");
211 if (regval != ADXL345_DEVID)
212 return dev_err_probe(dev, -ENODEV, "Invalid device ID: %x, expected %x\n",
213 regval, ADXL345_DEVID);
215 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
219 data = iio_priv(indio_dev);
220 data->regmap = regmap;
221 /* Enable full-resolution mode */
222 data->data_range = ADXL345_DATA_FORMAT_FULL_RES;
223 data->info = device_get_match_data(dev);
227 ret = regmap_write(data->regmap, ADXL345_REG_DATA_FORMAT,
230 return dev_err_probe(dev, ret, "Failed to set data range\n");
232 indio_dev->name = data->info->name;
233 indio_dev->info = &adxl345_info;
234 indio_dev->modes = INDIO_DIRECT_MODE;
235 indio_dev->channels = adxl345_channels;
236 indio_dev->num_channels = ARRAY_SIZE(adxl345_channels);
238 /* Enable measurement mode */
239 ret = adxl345_powerup(data->regmap);
241 return dev_err_probe(dev, ret, "Failed to enable measurement mode\n");
243 ret = devm_add_action_or_reset(dev, adxl345_powerdown, data->regmap);
247 return devm_iio_device_register(dev, indio_dev);
249 EXPORT_SYMBOL_NS_GPL(adxl345_core_probe, IIO_ADXL345);
251 MODULE_AUTHOR("Eva Rachel Retuya <eraretuya@gmail.com>");
252 MODULE_DESCRIPTION("ADXL345 3-Axis Digital Accelerometer core driver");
253 MODULE_LICENSE("GPL v2");