1 // SPDX-License-Identifier: GPL-2.0-only
3 * intel_idle.c - native hardware idle loop for modern Intel processors
5 * Copyright (c) 2013 - 2020, Intel Corporation.
6 * Len Brown <len.brown@intel.com>
7 * Rafael J. Wysocki <rafael.j.wysocki@intel.com>
11 * intel_idle is a cpuidle driver that loads on all Intel CPUs with MWAIT
12 * in lieu of the legacy ACPI processor_idle driver. The intent is to
13 * make Linux more efficient on these processors, as intel_idle knows
14 * more than ACPI, as well as make Linux more immune to ACPI BIOS bugs.
20 * All CPUs have same idle states as boot CPU
22 * Chipset BM_STS (bus master status) bit is a NOP
23 * for preventing entry into deep C-states
25 * CPU will flush caches as needed when entering a C-state via MWAIT
26 * (in contrast to entering ACPI C3, in which case the WBINVD
27 * instruction needs to be executed to flush the caches)
33 * ACPI has a .suspend hack to turn off deep c-statees during suspend
34 * to avoid complications with the lapic timer workaround.
35 * Have not seen issues with suspend, but may need same workaround here.
39 /* un-comment DEBUG to enable pr_debug() statements */
42 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
44 #include <linux/acpi.h>
45 #include <linux/kernel.h>
46 #include <linux/cpuidle.h>
47 #include <linux/tick.h>
48 #include <trace/events/power.h>
49 #include <linux/sched.h>
50 #include <linux/notifier.h>
51 #include <linux/cpu.h>
52 #include <linux/moduleparam.h>
53 #include <asm/cpu_device_id.h>
54 #include <asm/intel-family.h>
55 #include <asm/mwait.h>
58 #define INTEL_IDLE_VERSION "0.5.1"
60 static struct cpuidle_driver intel_idle_driver = {
64 /* intel_idle.max_cstate=0 disables driver */
65 static int max_cstate = CPUIDLE_STATE_MAX - 1;
66 static unsigned int disabled_states_mask;
68 static struct cpuidle_device __percpu *intel_idle_cpuidle_devices;
70 static unsigned long auto_demotion_disable_flags;
71 static bool disable_promotion_to_c1e;
74 struct cpuidle_state *state_table;
77 * Hardware C-state auto-demotion may not always be optimal.
78 * Indicate which enable bits to clear here.
80 unsigned long auto_demotion_disable_flags;
81 bool byt_auto_demotion_disable_flag;
82 bool disable_promotion_to_c1e;
86 static const struct idle_cpu *icpu __initdata;
87 static struct cpuidle_state *cpuidle_state_table __initdata;
89 static unsigned int mwait_substates __initdata;
92 * Enable this state by default even if the ACPI _CST does not list it.
94 #define CPUIDLE_FLAG_ALWAYS_ENABLE BIT(15)
97 * MWAIT takes an 8-bit "hint" in EAX "suggesting"
98 * the C-state (top nibble) and sub-state (bottom nibble)
99 * 0x00 means "MWAIT(C1)", 0x10 means "MWAIT(C2)" etc.
101 * We store the hint at the top of our "flags" for each state.
103 #define flg2MWAIT(flags) (((flags) >> 24) & 0xFF)
104 #define MWAIT2flg(eax) ((eax & 0xFF) << 24)
107 * intel_idle - Ask the processor to enter the given idle state.
108 * @dev: cpuidle device of the target CPU.
109 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
110 * @index: Target idle state index.
112 * Use the MWAIT instruction to notify the processor that the CPU represented by
113 * @dev is idle and it can try to enter the idle state corresponding to @index.
115 * If the local APIC timer is not known to be reliable in the target idle state,
116 * enable one-shot tick broadcasting for the target CPU before executing MWAIT.
118 * Optionally call leave_mm() for the target CPU upfront to avoid wakeups due to
119 * flushing user TLBs.
121 * Must be called under local_irq_disable().
123 static __cpuidle int intel_idle(struct cpuidle_device *dev,
124 struct cpuidle_driver *drv, int index)
126 struct cpuidle_state *state = &drv->states[index];
127 unsigned long eax = flg2MWAIT(state->flags);
128 unsigned long ecx = 1; /* break on interrupt flag */
130 mwait_idle_with_hints(eax, ecx);
136 * intel_idle_s2idle - Ask the processor to enter the given idle state.
137 * @dev: cpuidle device of the target CPU.
138 * @drv: cpuidle driver (assumed to point to intel_idle_driver).
139 * @index: Target idle state index.
141 * Use the MWAIT instruction to notify the processor that the CPU represented by
142 * @dev is idle and it can try to enter the idle state corresponding to @index.
144 * Invoked as a suspend-to-idle callback routine with frozen user space, frozen
145 * scheduler tick and suspended scheduler clock on the target CPU.
147 static __cpuidle int intel_idle_s2idle(struct cpuidle_device *dev,
148 struct cpuidle_driver *drv, int index)
150 unsigned long eax = flg2MWAIT(drv->states[index].flags);
151 unsigned long ecx = 1; /* break on interrupt flag */
153 mwait_idle_with_hints(eax, ecx);
159 * States are indexed by the cstate number,
160 * which is also the index into the MWAIT hint array.
161 * Thus C0 is a dummy.
163 static struct cpuidle_state nehalem_cstates[] __initdata = {
166 .desc = "MWAIT 0x00",
167 .flags = MWAIT2flg(0x00),
169 .target_residency = 6,
170 .enter = &intel_idle,
171 .enter_s2idle = intel_idle_s2idle, },
174 .desc = "MWAIT 0x01",
175 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
177 .target_residency = 20,
178 .enter = &intel_idle,
179 .enter_s2idle = intel_idle_s2idle, },
182 .desc = "MWAIT 0x10",
183 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
185 .target_residency = 80,
186 .enter = &intel_idle,
187 .enter_s2idle = intel_idle_s2idle, },
190 .desc = "MWAIT 0x20",
191 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
193 .target_residency = 800,
194 .enter = &intel_idle,
195 .enter_s2idle = intel_idle_s2idle, },
200 static struct cpuidle_state snb_cstates[] __initdata = {
203 .desc = "MWAIT 0x00",
204 .flags = MWAIT2flg(0x00),
206 .target_residency = 2,
207 .enter = &intel_idle,
208 .enter_s2idle = intel_idle_s2idle, },
211 .desc = "MWAIT 0x01",
212 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
214 .target_residency = 20,
215 .enter = &intel_idle,
216 .enter_s2idle = intel_idle_s2idle, },
219 .desc = "MWAIT 0x10",
220 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
222 .target_residency = 211,
223 .enter = &intel_idle,
224 .enter_s2idle = intel_idle_s2idle, },
227 .desc = "MWAIT 0x20",
228 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
230 .target_residency = 345,
231 .enter = &intel_idle,
232 .enter_s2idle = intel_idle_s2idle, },
235 .desc = "MWAIT 0x30",
236 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
238 .target_residency = 345,
239 .enter = &intel_idle,
240 .enter_s2idle = intel_idle_s2idle, },
245 static struct cpuidle_state byt_cstates[] __initdata = {
248 .desc = "MWAIT 0x00",
249 .flags = MWAIT2flg(0x00),
251 .target_residency = 1,
252 .enter = &intel_idle,
253 .enter_s2idle = intel_idle_s2idle, },
256 .desc = "MWAIT 0x58",
257 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
259 .target_residency = 275,
260 .enter = &intel_idle,
261 .enter_s2idle = intel_idle_s2idle, },
264 .desc = "MWAIT 0x52",
265 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
267 .target_residency = 560,
268 .enter = &intel_idle,
269 .enter_s2idle = intel_idle_s2idle, },
272 .desc = "MWAIT 0x60",
273 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
274 .exit_latency = 1200,
275 .target_residency = 4000,
276 .enter = &intel_idle,
277 .enter_s2idle = intel_idle_s2idle, },
280 .desc = "MWAIT 0x64",
281 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
282 .exit_latency = 10000,
283 .target_residency = 20000,
284 .enter = &intel_idle,
285 .enter_s2idle = intel_idle_s2idle, },
290 static struct cpuidle_state cht_cstates[] __initdata = {
293 .desc = "MWAIT 0x00",
294 .flags = MWAIT2flg(0x00),
296 .target_residency = 1,
297 .enter = &intel_idle,
298 .enter_s2idle = intel_idle_s2idle, },
301 .desc = "MWAIT 0x58",
302 .flags = MWAIT2flg(0x58) | CPUIDLE_FLAG_TLB_FLUSHED,
304 .target_residency = 275,
305 .enter = &intel_idle,
306 .enter_s2idle = intel_idle_s2idle, },
309 .desc = "MWAIT 0x52",
310 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
312 .target_residency = 560,
313 .enter = &intel_idle,
314 .enter_s2idle = intel_idle_s2idle, },
317 .desc = "MWAIT 0x60",
318 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
319 .exit_latency = 1200,
320 .target_residency = 4000,
321 .enter = &intel_idle,
322 .enter_s2idle = intel_idle_s2idle, },
325 .desc = "MWAIT 0x64",
326 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
327 .exit_latency = 10000,
328 .target_residency = 20000,
329 .enter = &intel_idle,
330 .enter_s2idle = intel_idle_s2idle, },
335 static struct cpuidle_state ivb_cstates[] __initdata = {
338 .desc = "MWAIT 0x00",
339 .flags = MWAIT2flg(0x00),
341 .target_residency = 1,
342 .enter = &intel_idle,
343 .enter_s2idle = intel_idle_s2idle, },
346 .desc = "MWAIT 0x01",
347 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
349 .target_residency = 20,
350 .enter = &intel_idle,
351 .enter_s2idle = intel_idle_s2idle, },
354 .desc = "MWAIT 0x10",
355 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
357 .target_residency = 156,
358 .enter = &intel_idle,
359 .enter_s2idle = intel_idle_s2idle, },
362 .desc = "MWAIT 0x20",
363 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
365 .target_residency = 300,
366 .enter = &intel_idle,
367 .enter_s2idle = intel_idle_s2idle, },
370 .desc = "MWAIT 0x30",
371 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
373 .target_residency = 300,
374 .enter = &intel_idle,
375 .enter_s2idle = intel_idle_s2idle, },
380 static struct cpuidle_state ivt_cstates[] __initdata = {
383 .desc = "MWAIT 0x00",
384 .flags = MWAIT2flg(0x00),
386 .target_residency = 1,
387 .enter = &intel_idle,
388 .enter_s2idle = intel_idle_s2idle, },
391 .desc = "MWAIT 0x01",
392 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
394 .target_residency = 80,
395 .enter = &intel_idle,
396 .enter_s2idle = intel_idle_s2idle, },
399 .desc = "MWAIT 0x10",
400 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
402 .target_residency = 156,
403 .enter = &intel_idle,
404 .enter_s2idle = intel_idle_s2idle, },
407 .desc = "MWAIT 0x20",
408 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
410 .target_residency = 300,
411 .enter = &intel_idle,
412 .enter_s2idle = intel_idle_s2idle, },
417 static struct cpuidle_state ivt_cstates_4s[] __initdata = {
420 .desc = "MWAIT 0x00",
421 .flags = MWAIT2flg(0x00),
423 .target_residency = 1,
424 .enter = &intel_idle,
425 .enter_s2idle = intel_idle_s2idle, },
428 .desc = "MWAIT 0x01",
429 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
431 .target_residency = 250,
432 .enter = &intel_idle,
433 .enter_s2idle = intel_idle_s2idle, },
436 .desc = "MWAIT 0x10",
437 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
439 .target_residency = 300,
440 .enter = &intel_idle,
441 .enter_s2idle = intel_idle_s2idle, },
444 .desc = "MWAIT 0x20",
445 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
447 .target_residency = 400,
448 .enter = &intel_idle,
449 .enter_s2idle = intel_idle_s2idle, },
454 static struct cpuidle_state ivt_cstates_8s[] __initdata = {
457 .desc = "MWAIT 0x00",
458 .flags = MWAIT2flg(0x00),
460 .target_residency = 1,
461 .enter = &intel_idle,
462 .enter_s2idle = intel_idle_s2idle, },
465 .desc = "MWAIT 0x01",
466 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
468 .target_residency = 500,
469 .enter = &intel_idle,
470 .enter_s2idle = intel_idle_s2idle, },
473 .desc = "MWAIT 0x10",
474 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
476 .target_residency = 600,
477 .enter = &intel_idle,
478 .enter_s2idle = intel_idle_s2idle, },
481 .desc = "MWAIT 0x20",
482 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
484 .target_residency = 700,
485 .enter = &intel_idle,
486 .enter_s2idle = intel_idle_s2idle, },
491 static struct cpuidle_state hsw_cstates[] __initdata = {
494 .desc = "MWAIT 0x00",
495 .flags = MWAIT2flg(0x00),
497 .target_residency = 2,
498 .enter = &intel_idle,
499 .enter_s2idle = intel_idle_s2idle, },
502 .desc = "MWAIT 0x01",
503 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
505 .target_residency = 20,
506 .enter = &intel_idle,
507 .enter_s2idle = intel_idle_s2idle, },
510 .desc = "MWAIT 0x10",
511 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
513 .target_residency = 100,
514 .enter = &intel_idle,
515 .enter_s2idle = intel_idle_s2idle, },
518 .desc = "MWAIT 0x20",
519 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
521 .target_residency = 400,
522 .enter = &intel_idle,
523 .enter_s2idle = intel_idle_s2idle, },
526 .desc = "MWAIT 0x32",
527 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
529 .target_residency = 500,
530 .enter = &intel_idle,
531 .enter_s2idle = intel_idle_s2idle, },
534 .desc = "MWAIT 0x40",
535 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
537 .target_residency = 900,
538 .enter = &intel_idle,
539 .enter_s2idle = intel_idle_s2idle, },
542 .desc = "MWAIT 0x50",
543 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
545 .target_residency = 1800,
546 .enter = &intel_idle,
547 .enter_s2idle = intel_idle_s2idle, },
550 .desc = "MWAIT 0x60",
551 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
552 .exit_latency = 2600,
553 .target_residency = 7700,
554 .enter = &intel_idle,
555 .enter_s2idle = intel_idle_s2idle, },
559 static struct cpuidle_state bdw_cstates[] __initdata = {
562 .desc = "MWAIT 0x00",
563 .flags = MWAIT2flg(0x00),
565 .target_residency = 2,
566 .enter = &intel_idle,
567 .enter_s2idle = intel_idle_s2idle, },
570 .desc = "MWAIT 0x01",
571 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
573 .target_residency = 20,
574 .enter = &intel_idle,
575 .enter_s2idle = intel_idle_s2idle, },
578 .desc = "MWAIT 0x10",
579 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
581 .target_residency = 100,
582 .enter = &intel_idle,
583 .enter_s2idle = intel_idle_s2idle, },
586 .desc = "MWAIT 0x20",
587 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
589 .target_residency = 400,
590 .enter = &intel_idle,
591 .enter_s2idle = intel_idle_s2idle, },
594 .desc = "MWAIT 0x32",
595 .flags = MWAIT2flg(0x32) | CPUIDLE_FLAG_TLB_FLUSHED,
597 .target_residency = 500,
598 .enter = &intel_idle,
599 .enter_s2idle = intel_idle_s2idle, },
602 .desc = "MWAIT 0x40",
603 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
605 .target_residency = 900,
606 .enter = &intel_idle,
607 .enter_s2idle = intel_idle_s2idle, },
610 .desc = "MWAIT 0x50",
611 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
613 .target_residency = 1800,
614 .enter = &intel_idle,
615 .enter_s2idle = intel_idle_s2idle, },
618 .desc = "MWAIT 0x60",
619 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
620 .exit_latency = 2600,
621 .target_residency = 7700,
622 .enter = &intel_idle,
623 .enter_s2idle = intel_idle_s2idle, },
628 static struct cpuidle_state skl_cstates[] __initdata = {
631 .desc = "MWAIT 0x00",
632 .flags = MWAIT2flg(0x00),
634 .target_residency = 2,
635 .enter = &intel_idle,
636 .enter_s2idle = intel_idle_s2idle, },
639 .desc = "MWAIT 0x01",
640 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
642 .target_residency = 20,
643 .enter = &intel_idle,
644 .enter_s2idle = intel_idle_s2idle, },
647 .desc = "MWAIT 0x10",
648 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
650 .target_residency = 100,
651 .enter = &intel_idle,
652 .enter_s2idle = intel_idle_s2idle, },
655 .desc = "MWAIT 0x20",
656 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
658 .target_residency = 200,
659 .enter = &intel_idle,
660 .enter_s2idle = intel_idle_s2idle, },
663 .desc = "MWAIT 0x33",
664 .flags = MWAIT2flg(0x33) | CPUIDLE_FLAG_TLB_FLUSHED,
666 .target_residency = 800,
667 .enter = &intel_idle,
668 .enter_s2idle = intel_idle_s2idle, },
671 .desc = "MWAIT 0x40",
672 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
674 .target_residency = 800,
675 .enter = &intel_idle,
676 .enter_s2idle = intel_idle_s2idle, },
679 .desc = "MWAIT 0x50",
680 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
682 .target_residency = 5000,
683 .enter = &intel_idle,
684 .enter_s2idle = intel_idle_s2idle, },
687 .desc = "MWAIT 0x60",
688 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
690 .target_residency = 5000,
691 .enter = &intel_idle,
692 .enter_s2idle = intel_idle_s2idle, },
697 static struct cpuidle_state skx_cstates[] __initdata = {
700 .desc = "MWAIT 0x00",
701 .flags = MWAIT2flg(0x00),
703 .target_residency = 2,
704 .enter = &intel_idle,
705 .enter_s2idle = intel_idle_s2idle, },
708 .desc = "MWAIT 0x01",
709 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
711 .target_residency = 20,
712 .enter = &intel_idle,
713 .enter_s2idle = intel_idle_s2idle, },
716 .desc = "MWAIT 0x20",
717 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
719 .target_residency = 600,
720 .enter = &intel_idle,
721 .enter_s2idle = intel_idle_s2idle, },
726 static struct cpuidle_state icx_cstates[] __initdata = {
729 .desc = "MWAIT 0x00",
730 .flags = MWAIT2flg(0x00),
732 .target_residency = 1,
733 .enter = &intel_idle,
734 .enter_s2idle = intel_idle_s2idle, },
737 .desc = "MWAIT 0x01",
738 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
740 .target_residency = 4,
741 .enter = &intel_idle,
742 .enter_s2idle = intel_idle_s2idle, },
745 .desc = "MWAIT 0x20",
746 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
748 .target_residency = 600,
749 .enter = &intel_idle,
750 .enter_s2idle = intel_idle_s2idle, },
755 static struct cpuidle_state atom_cstates[] __initdata = {
758 .desc = "MWAIT 0x00",
759 .flags = MWAIT2flg(0x00),
761 .target_residency = 20,
762 .enter = &intel_idle,
763 .enter_s2idle = intel_idle_s2idle, },
766 .desc = "MWAIT 0x10",
767 .flags = MWAIT2flg(0x10),
769 .target_residency = 80,
770 .enter = &intel_idle,
771 .enter_s2idle = intel_idle_s2idle, },
774 .desc = "MWAIT 0x30",
775 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
777 .target_residency = 400,
778 .enter = &intel_idle,
779 .enter_s2idle = intel_idle_s2idle, },
782 .desc = "MWAIT 0x52",
783 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
785 .target_residency = 560,
786 .enter = &intel_idle,
787 .enter_s2idle = intel_idle_s2idle, },
791 static struct cpuidle_state tangier_cstates[] __initdata = {
794 .desc = "MWAIT 0x00",
795 .flags = MWAIT2flg(0x00),
797 .target_residency = 4,
798 .enter = &intel_idle,
799 .enter_s2idle = intel_idle_s2idle, },
802 .desc = "MWAIT 0x30",
803 .flags = MWAIT2flg(0x30) | CPUIDLE_FLAG_TLB_FLUSHED,
805 .target_residency = 400,
806 .enter = &intel_idle,
807 .enter_s2idle = intel_idle_s2idle, },
810 .desc = "MWAIT 0x52",
811 .flags = MWAIT2flg(0x52) | CPUIDLE_FLAG_TLB_FLUSHED,
813 .target_residency = 560,
814 .enter = &intel_idle,
815 .enter_s2idle = intel_idle_s2idle, },
818 .desc = "MWAIT 0x60",
819 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
820 .exit_latency = 1200,
821 .target_residency = 4000,
822 .enter = &intel_idle,
823 .enter_s2idle = intel_idle_s2idle, },
826 .desc = "MWAIT 0x64",
827 .flags = MWAIT2flg(0x64) | CPUIDLE_FLAG_TLB_FLUSHED,
828 .exit_latency = 10000,
829 .target_residency = 20000,
830 .enter = &intel_idle,
831 .enter_s2idle = intel_idle_s2idle, },
835 static struct cpuidle_state avn_cstates[] __initdata = {
838 .desc = "MWAIT 0x00",
839 .flags = MWAIT2flg(0x00),
841 .target_residency = 2,
842 .enter = &intel_idle,
843 .enter_s2idle = intel_idle_s2idle, },
846 .desc = "MWAIT 0x51",
847 .flags = MWAIT2flg(0x51) | CPUIDLE_FLAG_TLB_FLUSHED,
849 .target_residency = 45,
850 .enter = &intel_idle,
851 .enter_s2idle = intel_idle_s2idle, },
855 static struct cpuidle_state knl_cstates[] __initdata = {
858 .desc = "MWAIT 0x00",
859 .flags = MWAIT2flg(0x00),
861 .target_residency = 2,
862 .enter = &intel_idle,
863 .enter_s2idle = intel_idle_s2idle },
866 .desc = "MWAIT 0x10",
867 .flags = MWAIT2flg(0x10) | CPUIDLE_FLAG_TLB_FLUSHED,
869 .target_residency = 500,
870 .enter = &intel_idle,
871 .enter_s2idle = intel_idle_s2idle },
876 static struct cpuidle_state bxt_cstates[] __initdata = {
879 .desc = "MWAIT 0x00",
880 .flags = MWAIT2flg(0x00),
882 .target_residency = 2,
883 .enter = &intel_idle,
884 .enter_s2idle = intel_idle_s2idle, },
887 .desc = "MWAIT 0x01",
888 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
890 .target_residency = 20,
891 .enter = &intel_idle,
892 .enter_s2idle = intel_idle_s2idle, },
895 .desc = "MWAIT 0x20",
896 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
898 .target_residency = 133,
899 .enter = &intel_idle,
900 .enter_s2idle = intel_idle_s2idle, },
903 .desc = "MWAIT 0x31",
904 .flags = MWAIT2flg(0x31) | CPUIDLE_FLAG_TLB_FLUSHED,
906 .target_residency = 155,
907 .enter = &intel_idle,
908 .enter_s2idle = intel_idle_s2idle, },
911 .desc = "MWAIT 0x40",
912 .flags = MWAIT2flg(0x40) | CPUIDLE_FLAG_TLB_FLUSHED,
913 .exit_latency = 1000,
914 .target_residency = 1000,
915 .enter = &intel_idle,
916 .enter_s2idle = intel_idle_s2idle, },
919 .desc = "MWAIT 0x50",
920 .flags = MWAIT2flg(0x50) | CPUIDLE_FLAG_TLB_FLUSHED,
921 .exit_latency = 2000,
922 .target_residency = 2000,
923 .enter = &intel_idle,
924 .enter_s2idle = intel_idle_s2idle, },
927 .desc = "MWAIT 0x60",
928 .flags = MWAIT2flg(0x60) | CPUIDLE_FLAG_TLB_FLUSHED,
929 .exit_latency = 10000,
930 .target_residency = 10000,
931 .enter = &intel_idle,
932 .enter_s2idle = intel_idle_s2idle, },
937 static struct cpuidle_state dnv_cstates[] __initdata = {
940 .desc = "MWAIT 0x00",
941 .flags = MWAIT2flg(0x00),
943 .target_residency = 2,
944 .enter = &intel_idle,
945 .enter_s2idle = intel_idle_s2idle, },
948 .desc = "MWAIT 0x01",
949 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
951 .target_residency = 20,
952 .enter = &intel_idle,
953 .enter_s2idle = intel_idle_s2idle, },
956 .desc = "MWAIT 0x20",
957 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
959 .target_residency = 500,
960 .enter = &intel_idle,
961 .enter_s2idle = intel_idle_s2idle, },
967 * Note, depending on HW and FW revision, SnowRidge SoC may or may not support
968 * C6, and this is indicated in the CPUID mwait leaf.
970 static struct cpuidle_state snr_cstates[] __initdata = {
973 .desc = "MWAIT 0x00",
974 .flags = MWAIT2flg(0x00),
976 .target_residency = 2,
977 .enter = &intel_idle,
978 .enter_s2idle = intel_idle_s2idle, },
981 .desc = "MWAIT 0x01",
982 .flags = MWAIT2flg(0x01) | CPUIDLE_FLAG_ALWAYS_ENABLE,
984 .target_residency = 25,
985 .enter = &intel_idle,
986 .enter_s2idle = intel_idle_s2idle, },
989 .desc = "MWAIT 0x20",
990 .flags = MWAIT2flg(0x20) | CPUIDLE_FLAG_TLB_FLUSHED,
992 .target_residency = 500,
993 .enter = &intel_idle,
994 .enter_s2idle = intel_idle_s2idle, },
999 static const struct idle_cpu idle_cpu_nehalem __initconst = {
1000 .state_table = nehalem_cstates,
1001 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1002 .disable_promotion_to_c1e = true,
1005 static const struct idle_cpu idle_cpu_nhx __initconst = {
1006 .state_table = nehalem_cstates,
1007 .auto_demotion_disable_flags = NHM_C1_AUTO_DEMOTE | NHM_C3_AUTO_DEMOTE,
1008 .disable_promotion_to_c1e = true,
1012 static const struct idle_cpu idle_cpu_atom __initconst = {
1013 .state_table = atom_cstates,
1016 static const struct idle_cpu idle_cpu_tangier __initconst = {
1017 .state_table = tangier_cstates,
1020 static const struct idle_cpu idle_cpu_lincroft __initconst = {
1021 .state_table = atom_cstates,
1022 .auto_demotion_disable_flags = ATM_LNC_C6_AUTO_DEMOTE,
1025 static const struct idle_cpu idle_cpu_snb __initconst = {
1026 .state_table = snb_cstates,
1027 .disable_promotion_to_c1e = true,
1030 static const struct idle_cpu idle_cpu_snx __initconst = {
1031 .state_table = snb_cstates,
1032 .disable_promotion_to_c1e = true,
1036 static const struct idle_cpu idle_cpu_byt __initconst = {
1037 .state_table = byt_cstates,
1038 .disable_promotion_to_c1e = true,
1039 .byt_auto_demotion_disable_flag = true,
1042 static const struct idle_cpu idle_cpu_cht __initconst = {
1043 .state_table = cht_cstates,
1044 .disable_promotion_to_c1e = true,
1045 .byt_auto_demotion_disable_flag = true,
1048 static const struct idle_cpu idle_cpu_ivb __initconst = {
1049 .state_table = ivb_cstates,
1050 .disable_promotion_to_c1e = true,
1053 static const struct idle_cpu idle_cpu_ivt __initconst = {
1054 .state_table = ivt_cstates,
1055 .disable_promotion_to_c1e = true,
1059 static const struct idle_cpu idle_cpu_hsw __initconst = {
1060 .state_table = hsw_cstates,
1061 .disable_promotion_to_c1e = true,
1064 static const struct idle_cpu idle_cpu_hsx __initconst = {
1065 .state_table = hsw_cstates,
1066 .disable_promotion_to_c1e = true,
1070 static const struct idle_cpu idle_cpu_bdw __initconst = {
1071 .state_table = bdw_cstates,
1072 .disable_promotion_to_c1e = true,
1075 static const struct idle_cpu idle_cpu_bdx __initconst = {
1076 .state_table = bdw_cstates,
1077 .disable_promotion_to_c1e = true,
1081 static const struct idle_cpu idle_cpu_skl __initconst = {
1082 .state_table = skl_cstates,
1083 .disable_promotion_to_c1e = true,
1086 static const struct idle_cpu idle_cpu_skx __initconst = {
1087 .state_table = skx_cstates,
1088 .disable_promotion_to_c1e = true,
1092 static const struct idle_cpu idle_cpu_icx __initconst = {
1093 .state_table = icx_cstates,
1094 .disable_promotion_to_c1e = true,
1098 static const struct idle_cpu idle_cpu_avn __initconst = {
1099 .state_table = avn_cstates,
1100 .disable_promotion_to_c1e = true,
1104 static const struct idle_cpu idle_cpu_knl __initconst = {
1105 .state_table = knl_cstates,
1109 static const struct idle_cpu idle_cpu_bxt __initconst = {
1110 .state_table = bxt_cstates,
1111 .disable_promotion_to_c1e = true,
1114 static const struct idle_cpu idle_cpu_dnv __initconst = {
1115 .state_table = dnv_cstates,
1116 .disable_promotion_to_c1e = true,
1120 static const struct idle_cpu idle_cpu_snr __initconst = {
1121 .state_table = snr_cstates,
1122 .disable_promotion_to_c1e = true,
1126 static const struct x86_cpu_id intel_idle_ids[] __initconst = {
1127 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EP, &idle_cpu_nhx),
1128 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM, &idle_cpu_nehalem),
1129 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_G, &idle_cpu_nehalem),
1130 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE, &idle_cpu_nehalem),
1131 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EP, &idle_cpu_nhx),
1132 X86_MATCH_INTEL_FAM6_MODEL(NEHALEM_EX, &idle_cpu_nhx),
1133 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL, &idle_cpu_atom),
1134 X86_MATCH_INTEL_FAM6_MODEL(ATOM_BONNELL_MID, &idle_cpu_lincroft),
1135 X86_MATCH_INTEL_FAM6_MODEL(WESTMERE_EX, &idle_cpu_nhx),
1136 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE, &idle_cpu_snb),
1137 X86_MATCH_INTEL_FAM6_MODEL(SANDYBRIDGE_X, &idle_cpu_snx),
1138 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SALTWELL, &idle_cpu_atom),
1139 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT, &idle_cpu_byt),
1140 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, &idle_cpu_tangier),
1141 X86_MATCH_INTEL_FAM6_MODEL(ATOM_AIRMONT, &idle_cpu_cht),
1142 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE, &idle_cpu_ivb),
1143 X86_MATCH_INTEL_FAM6_MODEL(IVYBRIDGE_X, &idle_cpu_ivt),
1144 X86_MATCH_INTEL_FAM6_MODEL(HASWELL, &idle_cpu_hsw),
1145 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_X, &idle_cpu_hsx),
1146 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_L, &idle_cpu_hsw),
1147 X86_MATCH_INTEL_FAM6_MODEL(HASWELL_G, &idle_cpu_hsw),
1148 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_D, &idle_cpu_avn),
1149 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL, &idle_cpu_bdw),
1150 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_G, &idle_cpu_bdw),
1151 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_X, &idle_cpu_bdx),
1152 X86_MATCH_INTEL_FAM6_MODEL(BROADWELL_D, &idle_cpu_bdx),
1153 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_L, &idle_cpu_skl),
1154 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE, &idle_cpu_skl),
1155 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE_L, &idle_cpu_skl),
1156 X86_MATCH_INTEL_FAM6_MODEL(KABYLAKE, &idle_cpu_skl),
1157 X86_MATCH_INTEL_FAM6_MODEL(SKYLAKE_X, &idle_cpu_skx),
1158 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_X, &idle_cpu_icx),
1159 X86_MATCH_INTEL_FAM6_MODEL(ICELAKE_D, &idle_cpu_icx),
1160 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNL, &idle_cpu_knl),
1161 X86_MATCH_INTEL_FAM6_MODEL(XEON_PHI_KNM, &idle_cpu_knl),
1162 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, &idle_cpu_bxt),
1163 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_PLUS, &idle_cpu_bxt),
1164 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT_D, &idle_cpu_dnv),
1165 X86_MATCH_INTEL_FAM6_MODEL(ATOM_TREMONT_D, &idle_cpu_snr),
1169 static const struct x86_cpu_id intel_mwait_ids[] __initconst = {
1170 X86_MATCH_VENDOR_FAM_FEATURE(INTEL, 6, X86_FEATURE_MWAIT, NULL),
1174 static bool __init intel_idle_max_cstate_reached(int cstate)
1176 if (cstate + 1 > max_cstate) {
1177 pr_info("max_cstate %d reached\n", max_cstate);
1183 static bool __init intel_idle_state_needs_timer_stop(struct cpuidle_state *state)
1185 unsigned long eax = flg2MWAIT(state->flags);
1187 if (boot_cpu_has(X86_FEATURE_ARAT))
1191 * Switch over to one-shot tick broadcast if the target C-state
1192 * is deeper than C1.
1194 return !!((eax >> MWAIT_SUBSTATE_SIZE) & MWAIT_CSTATE_MASK);
1197 #ifdef CONFIG_ACPI_PROCESSOR_CSTATE
1198 #include <acpi/processor.h>
1200 static bool no_acpi __read_mostly;
1201 module_param(no_acpi, bool, 0444);
1202 MODULE_PARM_DESC(no_acpi, "Do not use ACPI _CST for building the idle states list");
1204 static bool force_use_acpi __read_mostly; /* No effect if no_acpi is set. */
1205 module_param_named(use_acpi, force_use_acpi, bool, 0444);
1206 MODULE_PARM_DESC(use_acpi, "Use ACPI _CST for building the idle states list");
1208 static struct acpi_processor_power acpi_state_table __initdata;
1211 * intel_idle_cst_usable - Check if the _CST information can be used.
1213 * Check if all of the C-states listed by _CST in the max_cstate range are
1214 * ACPI_CSTATE_FFH, which means that they should be entered via MWAIT.
1216 static bool __init intel_idle_cst_usable(void)
1220 limit = min_t(int, min_t(int, CPUIDLE_STATE_MAX, max_cstate + 1),
1221 acpi_state_table.count);
1223 for (cstate = 1; cstate < limit; cstate++) {
1224 struct acpi_processor_cx *cx = &acpi_state_table.states[cstate];
1226 if (cx->entry_method != ACPI_CSTATE_FFH)
1233 static bool __init intel_idle_acpi_cst_extract(void)
1238 pr_debug("Not allowed to use ACPI _CST\n");
1242 for_each_possible_cpu(cpu) {
1243 struct acpi_processor *pr = per_cpu(processors, cpu);
1248 if (acpi_processor_evaluate_cst(pr->handle, cpu, &acpi_state_table))
1251 acpi_state_table.count++;
1253 if (!intel_idle_cst_usable())
1256 if (!acpi_processor_claim_cst_control())
1262 acpi_state_table.count = 0;
1263 pr_debug("ACPI _CST not found or not usable\n");
1267 static void __init intel_idle_init_cstates_acpi(struct cpuidle_driver *drv)
1269 int cstate, limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1272 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1273 * the interesting states are ACPI_CSTATE_FFH.
1275 for (cstate = 1; cstate < limit; cstate++) {
1276 struct acpi_processor_cx *cx;
1277 struct cpuidle_state *state;
1279 if (intel_idle_max_cstate_reached(cstate - 1))
1282 cx = &acpi_state_table.states[cstate];
1284 state = &drv->states[drv->state_count++];
1286 snprintf(state->name, CPUIDLE_NAME_LEN, "C%d_ACPI", cstate);
1287 strlcpy(state->desc, cx->desc, CPUIDLE_DESC_LEN);
1288 state->exit_latency = cx->latency;
1290 * For C1-type C-states use the same number for both the exit
1291 * latency and target residency, because that is the case for
1292 * C1 in the majority of the static C-states tables above.
1293 * For the other types of C-states, however, set the target
1294 * residency to 3 times the exit latency which should lead to
1295 * a reasonable balance between energy-efficiency and
1296 * performance in the majority of interesting cases.
1298 state->target_residency = cx->latency;
1299 if (cx->type > ACPI_STATE_C1)
1300 state->target_residency *= 3;
1302 state->flags = MWAIT2flg(cx->address);
1303 if (cx->type > ACPI_STATE_C2)
1304 state->flags |= CPUIDLE_FLAG_TLB_FLUSHED;
1306 if (disabled_states_mask & BIT(cstate))
1307 state->flags |= CPUIDLE_FLAG_OFF;
1309 if (intel_idle_state_needs_timer_stop(state))
1310 state->flags |= CPUIDLE_FLAG_TIMER_STOP;
1312 state->enter = intel_idle;
1313 state->enter_s2idle = intel_idle_s2idle;
1317 static bool __init intel_idle_off_by_default(u32 mwait_hint)
1322 * If there are no _CST C-states, do not disable any C-states by
1325 if (!acpi_state_table.count)
1328 limit = min_t(int, CPUIDLE_STATE_MAX, acpi_state_table.count);
1330 * If limit > 0, intel_idle_cst_usable() has returned 'true', so all of
1331 * the interesting states are ACPI_CSTATE_FFH.
1333 for (cstate = 1; cstate < limit; cstate++) {
1334 if (acpi_state_table.states[cstate].address == mwait_hint)
1339 #else /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1340 #define force_use_acpi (false)
1342 static inline bool intel_idle_acpi_cst_extract(void) { return false; }
1343 static inline void intel_idle_init_cstates_acpi(struct cpuidle_driver *drv) { }
1344 static inline bool intel_idle_off_by_default(u32 mwait_hint) { return false; }
1345 #endif /* !CONFIG_ACPI_PROCESSOR_CSTATE */
1348 * ivt_idle_state_table_update - Tune the idle states table for Ivy Town.
1350 * Tune IVT multi-socket targets.
1351 * Assumption: num_sockets == (max_package_num + 1).
1353 static void __init ivt_idle_state_table_update(void)
1355 /* IVT uses a different table for 1-2, 3-4, and > 4 sockets */
1356 int cpu, package_num, num_sockets = 1;
1358 for_each_online_cpu(cpu) {
1359 package_num = topology_physical_package_id(cpu);
1360 if (package_num + 1 > num_sockets) {
1361 num_sockets = package_num + 1;
1363 if (num_sockets > 4) {
1364 cpuidle_state_table = ivt_cstates_8s;
1370 if (num_sockets > 2)
1371 cpuidle_state_table = ivt_cstates_4s;
1373 /* else, 1 and 2 socket systems use default ivt_cstates */
1377 * irtl_2_usec - IRTL to microseconds conversion.
1378 * @irtl: IRTL MSR value.
1380 * Translate the IRTL (Interrupt Response Time Limit) MSR value to microseconds.
1382 static unsigned long long __init irtl_2_usec(unsigned long long irtl)
1384 static const unsigned int irtl_ns_units[] __initconst = {
1385 1, 32, 1024, 32768, 1048576, 33554432, 0, 0
1387 unsigned long long ns;
1392 ns = irtl_ns_units[(irtl >> 10) & 0x7];
1394 return div_u64((irtl & 0x3FF) * ns, NSEC_PER_USEC);
1398 * bxt_idle_state_table_update - Fix up the Broxton idle states table.
1400 * On BXT, trust the IRTL (Interrupt Response Time Limit) MSR to show the
1401 * definitive maximum latency and use the same value for target_residency.
1403 static void __init bxt_idle_state_table_update(void)
1405 unsigned long long msr;
1408 rdmsrl(MSR_PKGC6_IRTL, msr);
1409 usec = irtl_2_usec(msr);
1411 bxt_cstates[2].exit_latency = usec;
1412 bxt_cstates[2].target_residency = usec;
1415 rdmsrl(MSR_PKGC7_IRTL, msr);
1416 usec = irtl_2_usec(msr);
1418 bxt_cstates[3].exit_latency = usec;
1419 bxt_cstates[3].target_residency = usec;
1422 rdmsrl(MSR_PKGC8_IRTL, msr);
1423 usec = irtl_2_usec(msr);
1425 bxt_cstates[4].exit_latency = usec;
1426 bxt_cstates[4].target_residency = usec;
1429 rdmsrl(MSR_PKGC9_IRTL, msr);
1430 usec = irtl_2_usec(msr);
1432 bxt_cstates[5].exit_latency = usec;
1433 bxt_cstates[5].target_residency = usec;
1436 rdmsrl(MSR_PKGC10_IRTL, msr);
1437 usec = irtl_2_usec(msr);
1439 bxt_cstates[6].exit_latency = usec;
1440 bxt_cstates[6].target_residency = usec;
1446 * sklh_idle_state_table_update - Fix up the Sky Lake idle states table.
1448 * On SKL-H (model 0x5e) skip C8 and C9 if C10 is enabled and SGX disabled.
1450 static void __init sklh_idle_state_table_update(void)
1452 unsigned long long msr;
1453 unsigned int eax, ebx, ecx, edx;
1456 /* if PC10 disabled via cmdline intel_idle.max_cstate=7 or shallower */
1457 if (max_cstate <= 7)
1460 /* if PC10 not present in CPUID.MWAIT.EDX */
1461 if ((mwait_substates & (0xF << 28)) == 0)
1464 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1466 /* PC10 is not enabled in PKG C-state limit */
1467 if ((msr & 0xF) != 8)
1471 cpuid(7, &eax, &ebx, &ecx, &edx);
1473 /* if SGX is present */
1474 if (ebx & (1 << 2)) {
1476 rdmsrl(MSR_IA32_FEAT_CTL, msr);
1478 /* if SGX is enabled */
1479 if (msr & (1 << 18))
1483 skl_cstates[5].flags |= CPUIDLE_FLAG_UNUSABLE; /* C8-SKL */
1484 skl_cstates[6].flags |= CPUIDLE_FLAG_UNUSABLE; /* C9-SKL */
1488 * skx_idle_state_table_update - Adjust the Sky Lake/Cascade Lake
1489 * idle states table.
1491 static void __init skx_idle_state_table_update(void)
1493 unsigned long long msr;
1495 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr);
1498 * 000b: C0/C1 (no package C-state support)
1500 * 010b: C6 (non-retention)
1501 * 011b: C6 (retention)
1502 * 111b: No Package C state limits.
1504 if ((msr & 0x7) < 2) {
1506 * Uses the CC6 + PC0 latency and 3 times of
1507 * latency for target_residency if the PC6
1508 * is disabled in BIOS. This is consistent
1509 * with how intel_idle driver uses _CST
1510 * to set the target_residency.
1512 skx_cstates[2].exit_latency = 92;
1513 skx_cstates[2].target_residency = 276;
1517 static bool __init intel_idle_verify_cstate(unsigned int mwait_hint)
1519 unsigned int mwait_cstate = MWAIT_HINT2CSTATE(mwait_hint) + 1;
1520 unsigned int num_substates = (mwait_substates >> mwait_cstate * 4) &
1521 MWAIT_SUBSTATE_MASK;
1523 /* Ignore the C-state if there are NO sub-states in CPUID for it. */
1524 if (num_substates == 0)
1527 if (mwait_cstate > 2 && !boot_cpu_has(X86_FEATURE_NONSTOP_TSC))
1528 mark_tsc_unstable("TSC halts in idle states deeper than C2");
1533 static void __init intel_idle_init_cstates_icpu(struct cpuidle_driver *drv)
1537 switch (boot_cpu_data.x86_model) {
1538 case INTEL_FAM6_IVYBRIDGE_X:
1539 ivt_idle_state_table_update();
1541 case INTEL_FAM6_ATOM_GOLDMONT:
1542 case INTEL_FAM6_ATOM_GOLDMONT_PLUS:
1543 bxt_idle_state_table_update();
1545 case INTEL_FAM6_SKYLAKE:
1546 sklh_idle_state_table_update();
1548 case INTEL_FAM6_SKYLAKE_X:
1549 skx_idle_state_table_update();
1553 for (cstate = 0; cstate < CPUIDLE_STATE_MAX; ++cstate) {
1554 unsigned int mwait_hint;
1556 if (intel_idle_max_cstate_reached(cstate))
1559 if (!cpuidle_state_table[cstate].enter &&
1560 !cpuidle_state_table[cstate].enter_s2idle)
1563 /* If marked as unusable, skip this state. */
1564 if (cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_UNUSABLE) {
1565 pr_debug("state %s is disabled\n",
1566 cpuidle_state_table[cstate].name);
1570 mwait_hint = flg2MWAIT(cpuidle_state_table[cstate].flags);
1571 if (!intel_idle_verify_cstate(mwait_hint))
1574 /* Structure copy. */
1575 drv->states[drv->state_count] = cpuidle_state_table[cstate];
1577 if ((disabled_states_mask & BIT(drv->state_count)) ||
1578 ((icpu->use_acpi || force_use_acpi) &&
1579 intel_idle_off_by_default(mwait_hint) &&
1580 !(cpuidle_state_table[cstate].flags & CPUIDLE_FLAG_ALWAYS_ENABLE)))
1581 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_OFF;
1583 if (intel_idle_state_needs_timer_stop(&drv->states[drv->state_count]))
1584 drv->states[drv->state_count].flags |= CPUIDLE_FLAG_TIMER_STOP;
1589 if (icpu->byt_auto_demotion_disable_flag) {
1590 wrmsrl(MSR_CC6_DEMOTION_POLICY_CONFIG, 0);
1591 wrmsrl(MSR_MC6_DEMOTION_POLICY_CONFIG, 0);
1596 * intel_idle_cpuidle_driver_init - Create the list of available idle states.
1597 * @drv: cpuidle driver structure to initialize.
1599 static void __init intel_idle_cpuidle_driver_init(struct cpuidle_driver *drv)
1601 cpuidle_poll_state_init(drv);
1603 if (disabled_states_mask & BIT(0))
1604 drv->states[0].flags |= CPUIDLE_FLAG_OFF;
1606 drv->state_count = 1;
1609 intel_idle_init_cstates_icpu(drv);
1611 intel_idle_init_cstates_acpi(drv);
1614 static void auto_demotion_disable(void)
1616 unsigned long long msr_bits;
1618 rdmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1619 msr_bits &= ~auto_demotion_disable_flags;
1620 wrmsrl(MSR_PKG_CST_CONFIG_CONTROL, msr_bits);
1623 static void c1e_promotion_disable(void)
1625 unsigned long long msr_bits;
1627 rdmsrl(MSR_IA32_POWER_CTL, msr_bits);
1629 wrmsrl(MSR_IA32_POWER_CTL, msr_bits);
1633 * intel_idle_cpu_init - Register the target CPU with the cpuidle core.
1634 * @cpu: CPU to initialize.
1636 * Register a cpuidle device object for @cpu and update its MSRs in accordance
1637 * with the processor model flags.
1639 static int intel_idle_cpu_init(unsigned int cpu)
1641 struct cpuidle_device *dev;
1643 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1646 if (cpuidle_register_device(dev)) {
1647 pr_debug("cpuidle_register_device %d failed!\n", cpu);
1651 if (auto_demotion_disable_flags)
1652 auto_demotion_disable();
1654 if (disable_promotion_to_c1e)
1655 c1e_promotion_disable();
1660 static int intel_idle_cpu_online(unsigned int cpu)
1662 struct cpuidle_device *dev;
1664 if (!boot_cpu_has(X86_FEATURE_ARAT))
1665 tick_broadcast_enable();
1668 * Some systems can hotplug a cpu at runtime after
1669 * the kernel has booted, we have to initialize the
1670 * driver in this case
1672 dev = per_cpu_ptr(intel_idle_cpuidle_devices, cpu);
1673 if (!dev->registered)
1674 return intel_idle_cpu_init(cpu);
1680 * intel_idle_cpuidle_devices_uninit - Unregister all cpuidle devices.
1682 static void __init intel_idle_cpuidle_devices_uninit(void)
1686 for_each_online_cpu(i)
1687 cpuidle_unregister_device(per_cpu_ptr(intel_idle_cpuidle_devices, i));
1690 static int __init intel_idle_init(void)
1692 const struct x86_cpu_id *id;
1693 unsigned int eax, ebx, ecx;
1696 /* Do not load intel_idle at all for now if idle= is passed */
1697 if (boot_option_idle_override != IDLE_NO_OVERRIDE)
1700 if (max_cstate == 0) {
1701 pr_debug("disabled\n");
1705 id = x86_match_cpu(intel_idle_ids);
1707 if (!boot_cpu_has(X86_FEATURE_MWAIT)) {
1708 pr_debug("Please enable MWAIT in BIOS SETUP\n");
1712 id = x86_match_cpu(intel_mwait_ids);
1717 if (boot_cpu_data.cpuid_level < CPUID_MWAIT_LEAF)
1720 cpuid(CPUID_MWAIT_LEAF, &eax, &ebx, &ecx, &mwait_substates);
1722 if (!(ecx & CPUID5_ECX_EXTENSIONS_SUPPORTED) ||
1723 !(ecx & CPUID5_ECX_INTERRUPT_BREAK) ||
1727 pr_debug("MWAIT substates: 0x%x\n", mwait_substates);
1729 icpu = (const struct idle_cpu *)id->driver_data;
1731 cpuidle_state_table = icpu->state_table;
1732 auto_demotion_disable_flags = icpu->auto_demotion_disable_flags;
1733 disable_promotion_to_c1e = icpu->disable_promotion_to_c1e;
1734 if (icpu->use_acpi || force_use_acpi)
1735 intel_idle_acpi_cst_extract();
1736 } else if (!intel_idle_acpi_cst_extract()) {
1740 pr_debug("v" INTEL_IDLE_VERSION " model 0x%X\n",
1741 boot_cpu_data.x86_model);
1743 intel_idle_cpuidle_devices = alloc_percpu(struct cpuidle_device);
1744 if (!intel_idle_cpuidle_devices)
1747 intel_idle_cpuidle_driver_init(&intel_idle_driver);
1749 retval = cpuidle_register_driver(&intel_idle_driver);
1751 struct cpuidle_driver *drv = cpuidle_get_driver();
1752 printk(KERN_DEBUG pr_fmt("intel_idle yielding to %s\n"),
1753 drv ? drv->name : "none");
1754 goto init_driver_fail;
1757 retval = cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "idle/intel:online",
1758 intel_idle_cpu_online, NULL);
1762 pr_debug("Local APIC timer is reliable in %s\n",
1763 boot_cpu_has(X86_FEATURE_ARAT) ? "all C-states" : "C1");
1768 intel_idle_cpuidle_devices_uninit();
1769 cpuidle_unregister_driver(&intel_idle_driver);
1771 free_percpu(intel_idle_cpuidle_devices);
1775 device_initcall(intel_idle_init);
1778 * We are not really modular, but we used to support that. Meaning we also
1779 * support "intel_idle.max_cstate=..." at boot and also a read-only export of
1780 * it at /sys/module/intel_idle/parameters/max_cstate -- so using module_param
1781 * is the easiest way (currently) to continue doing that.
1783 module_param(max_cstate, int, 0444);
1785 * The positions of the bits that are set in this number are the indices of the
1786 * idle states to be disabled by default (as reflected by the names of the
1787 * corresponding idle state directories in sysfs, "state0", "state1" ...
1788 * "state<i>" ..., where <i> is the index of the given state).
1790 module_param_named(states_off, disabled_states_mask, uint, 0444);
1791 MODULE_PARM_DESC(states_off, "Mask of disabled idle states");