drivers/i2c/busses/i2c-tegra.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * drivers/i2c/busses/i2c-tegra.c
   4  *
   5  * Copyright (C) 2010 Google, Inc.
   6  * Author: Colin Cross <ccross@android.com>
   7  */
   8
   9 #include <linux/bitfield.h>
  10 #include <linux/clk.h>
  11 #include <linux/delay.h>
  12 #include <linux/dmaengine.h>
  13 #include <linux/dma-mapping.h>
  14 #include <linux/err.h>
  15 #include <linux/i2c.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/io.h>
  19 #include <linux/iopoll.h>
  20 #include <linux/irq.h>
  21 #include <linux/kernel.h>
  22 #include <linux/ktime.h>
  23 #include <linux/module.h>
  24 #include <linux/of_device.h>
  25 #include <linux/pinctrl/consumer.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/reset.h>
  29
  30 #define BYTES_PER_FIFO_WORD 4
  31
  32 #define I2C_CNFG                                0x000
  33 #define I2C_CNFG_DEBOUNCE_CNT                   GENMASK(14, 12)
  34 #define I2C_CNFG_PACKET_MODE_EN                 BIT(10)
  35 #define I2C_CNFG_NEW_MASTER_FSM                 BIT(11)
  36 #define I2C_CNFG_MULTI_MASTER_MODE              BIT(17)
  37 #define I2C_STATUS                              0x01c
  38 #define I2C_SL_CNFG                             0x020
  39 #define I2C_SL_CNFG_NACK                        BIT(1)
  40 #define I2C_SL_CNFG_NEWSL                       BIT(2)
  41 #define I2C_SL_ADDR1                            0x02c
  42 #define I2C_SL_ADDR2                            0x030
  43 #define I2C_TLOW_SEXT                           0x034
  44 #define I2C_TX_FIFO                             0x050
  45 #define I2C_RX_FIFO                             0x054
  46 #define I2C_PACKET_TRANSFER_STATUS              0x058
  47 #define I2C_FIFO_CONTROL                        0x05c
  48 #define I2C_FIFO_CONTROL_TX_FLUSH               BIT(1)
  49 #define I2C_FIFO_CONTROL_RX_FLUSH               BIT(0)
  50 #define I2C_FIFO_CONTROL_TX_TRIG(x)             (((x) - 1) << 5)
  51 #define I2C_FIFO_CONTROL_RX_TRIG(x)             (((x) - 1) << 2)
  52 #define I2C_FIFO_STATUS                         0x060
  53 #define I2C_FIFO_STATUS_TX                      GENMASK(7, 4)
  54 #define I2C_FIFO_STATUS_RX                      GENMASK(3, 0)
  55 #define I2C_INT_MASK                            0x064
  56 #define I2C_INT_STATUS                          0x068
  57 #define I2C_INT_BUS_CLR_DONE                    BIT(11)
  58 #define I2C_INT_PACKET_XFER_COMPLETE            BIT(7)
  59 #define I2C_INT_NO_ACK                          BIT(3)
  60 #define I2C_INT_ARBITRATION_LOST                BIT(2)
  61 #define I2C_INT_TX_FIFO_DATA_REQ                BIT(1)
  62 #define I2C_INT_RX_FIFO_DATA_REQ                BIT(0)
  63 #define I2C_CLK_DIVISOR                         0x06c
  64 #define I2C_CLK_DIVISOR_STD_FAST_MODE           GENMASK(31, 16)
  65 #define I2C_CLK_DIVISOR_HSMODE                  GENMASK(15, 0)
  66
  67 #define DVC_CTRL_REG1                           0x000
  68 #define DVC_CTRL_REG1_INTR_EN                   BIT(10)
  69 #define DVC_CTRL_REG3                           0x008
  70 #define DVC_CTRL_REG3_SW_PROG                   BIT(26)
  71 #define DVC_CTRL_REG3_I2C_DONE_INTR_EN          BIT(30)
  72 #define DVC_STATUS                              0x00c
  73 #define DVC_STATUS_I2C_DONE_INTR                BIT(30)
  74
  75 #define I2C_ERR_NONE                            0x00
  76 #define I2C_ERR_NO_ACK                          BIT(0)
  77 #define I2C_ERR_ARBITRATION_LOST                BIT(1)
  78 #define I2C_ERR_UNKNOWN_INTERRUPT               BIT(2)
  79 #define I2C_ERR_RX_BUFFER_OVERFLOW              BIT(3)
  80
  81 #define PACKET_HEADER0_HEADER_SIZE              GENMASK(29, 28)
  82 #define PACKET_HEADER0_PACKET_ID                GENMASK(23, 16)
  83 #define PACKET_HEADER0_CONT_ID                  GENMASK(15, 12)
  84 #define PACKET_HEADER0_PROTOCOL                 GENMASK(7, 4)
  85 #define PACKET_HEADER0_PROTOCOL_I2C             1
  86
  87 #define I2C_HEADER_CONT_ON_NAK                  BIT(21)
  88 #define I2C_HEADER_READ                         BIT(19)
  89 #define I2C_HEADER_10BIT_ADDR                   BIT(18)
  90 #define I2C_HEADER_IE_ENABLE                    BIT(17)
  91 #define I2C_HEADER_REPEAT_START                 BIT(16)
  92 #define I2C_HEADER_CONTINUE_XFER                BIT(15)
  93 #define I2C_HEADER_SLAVE_ADDR_SHIFT             1
  94
  95 #define I2C_BUS_CLEAR_CNFG                      0x084
  96 #define I2C_BC_SCLK_THRESHOLD                   GENMASK(23, 16)
  97 #define I2C_BC_STOP_COND                        BIT(2)
  98 #define I2C_BC_TERMINATE                        BIT(1)
  99 #define I2C_BC_ENABLE                           BIT(0)
 100 #define I2C_BUS_CLEAR_STATUS                    0x088
 101 #define I2C_BC_STATUS                           BIT(0)
 102
 103 #define I2C_CONFIG_LOAD                         0x08c
 104 #define I2C_MSTR_CONFIG_LOAD                    BIT(0)
 105
 106 #define I2C_CLKEN_OVERRIDE                      0x090
 107 #define I2C_MST_CORE_CLKEN_OVR                  BIT(0)
 108
 109 #define I2C_INTERFACE_TIMING_0                  0x094
 110 #define  I2C_INTERFACE_TIMING_THIGH             GENMASK(13, 8)
 111 #define  I2C_INTERFACE_TIMING_TLOW              GENMASK(5, 0)
 112 #define I2C_INTERFACE_TIMING_1                  0x098
 113 #define  I2C_INTERFACE_TIMING_TBUF              GENMASK(29, 24)
 114 #define  I2C_INTERFACE_TIMING_TSU_STO           GENMASK(21, 16)
 115 #define  I2C_INTERFACE_TIMING_THD_STA           GENMASK(13, 8)
 116 #define  I2C_INTERFACE_TIMING_TSU_STA           GENMASK(5, 0)
 117
 118 #define I2C_HS_INTERFACE_TIMING_0               0x09c
 119 #define  I2C_HS_INTERFACE_TIMING_THIGH          GENMASK(13, 8)
 120 #define  I2C_HS_INTERFACE_TIMING_TLOW           GENMASK(5, 0)
 121 #define I2C_HS_INTERFACE_TIMING_1               0x0a0
 122 #define  I2C_HS_INTERFACE_TIMING_TSU_STO        GENMASK(21, 16)
 123 #define  I2C_HS_INTERFACE_TIMING_THD_STA        GENMASK(13, 8)
 124 #define  I2C_HS_INTERFACE_TIMING_TSU_STA        GENMASK(5, 0)
 125
 126 #define I2C_MST_FIFO_CONTROL                    0x0b4
 127 #define I2C_MST_FIFO_CONTROL_RX_FLUSH           BIT(0)
 128 #define I2C_MST_FIFO_CONTROL_TX_FLUSH           BIT(1)
 129 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x)         (((x) - 1) <<  4)
 130 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x)         (((x) - 1) << 16)
 131
 132 #define I2C_MST_FIFO_STATUS                     0x0b8
 133 #define I2C_MST_FIFO_STATUS_TX                  GENMASK(23, 16)
 134 #define I2C_MST_FIFO_STATUS_RX                  GENMASK(7, 0)
 135
 136 /* configuration load timeout in microseconds */
 137 #define I2C_CONFIG_LOAD_TIMEOUT                 1000000
 138
 139 /* packet header size in bytes */
 140 #define I2C_PACKET_HEADER_SIZE                  12
 141
 142 /*
 143  * I2C Controller will use PIO mode for transfers up to 32 bytes in order to
 144  * avoid DMA overhead, otherwise external APB DMA controller will be used.
 145  * Note that the actual MAX PIO length is 20 bytes because 32 bytes include
 146  * I2C_PACKET_HEADER_SIZE.
 147  */
 148 #define I2C_PIO_MODE_PREFERRED_LEN              32
 149
 150 /*
 151  * msg_end_type: The bus control which needs to be sent at end of transfer.
 152  * @MSG_END_STOP: Send stop pulse.
 153  * @MSG_END_REPEAT_START: Send repeat-start.
 154  * @MSG_END_CONTINUE: Don't send stop or repeat-start.
 155  */
 156 enum msg_end_type {
 157         MSG_END_STOP,
 158         MSG_END_REPEAT_START,
 159         MSG_END_CONTINUE,
 160 };
 161
 162 /**
 163  * struct tegra_i2c_hw_feature : per hardware generation features
 164  * @has_continue_xfer_support: continue-transfer supported
 165  * @has_per_pkt_xfer_complete_irq: Has enable/disable capability for transfer
 166  *              completion interrupt on per packet basis.
 167  * @has_config_load_reg: Has the config load register to load the new
 168  *              configuration.
 169  * @clk_divisor_hs_mode: Clock divisor in HS mode.
 170  * @clk_divisor_std_mode: Clock divisor in standard mode. It is
 171  *              applicable if there is no fast clock source i.e. single clock
 172  *              source.
 173  * @clk_divisor_fast_mode: Clock divisor in fast mode. It is
 174  *              applicable if there is no fast clock source i.e. single clock
 175  *              source.
 176  * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
 177  *              applicable if there is no fast clock source (i.e. single
 178  *              clock source).
 179  * @has_multi_master_mode: The I2C controller supports running in single-master
 180  *              or multi-master mode.
 181  * @has_slcg_override_reg: The I2C controller supports a register that
 182  *              overrides the second level clock gating.
 183  * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
 184  *              provides additional features and allows for longer messages to
 185  *              be transferred in one go.
 186  * @quirks: I2C adapter quirks for limiting write/read transfer size and not
 187  *              allowing 0 length transfers.
 188  * @supports_bus_clear: Bus Clear support to recover from bus hang during
 189  *              SDA stuck low from device for some unknown reasons.
 190  * @has_apb_dma: Support of APBDMA on corresponding Tegra chip.
 191  * @tlow_std_mode: Low period of the clock in standard mode.
 192  * @thigh_std_mode: High period of the clock in standard mode.
 193  * @tlow_fast_fastplus_mode: Low period of the clock in fast/fast-plus modes.
 194  * @thigh_fast_fastplus_mode: High period of the clock in fast/fast-plus modes.
 195  * @setup_hold_time_std_mode: Setup and hold time for start and stop conditions
 196  *              in standard mode.
 197  * @setup_hold_time_fast_fast_plus_mode: Setup and hold time for start and stop
 198  *              conditions in fast/fast-plus modes.
 199  * @setup_hold_time_hs_mode: Setup and hold time for start and stop conditions
 200  *              in HS mode.
 201  * @has_interface_timing_reg: Has interface timing register to program the tuned
 202  *              timing settings.
 203  */
 204 struct tegra_i2c_hw_feature {
 205         bool has_continue_xfer_support;
 206         bool has_per_pkt_xfer_complete_irq;
 207         bool has_config_load_reg;
 208         u32 clk_divisor_hs_mode;
 209         u32 clk_divisor_std_mode;
 210         u32 clk_divisor_fast_mode;
 211         u32 clk_divisor_fast_plus_mode;
 212         bool has_multi_master_mode;
 213         bool has_slcg_override_reg;
 214         bool has_mst_fifo;
 215         const struct i2c_adapter_quirks *quirks;
 216         bool supports_bus_clear;
 217         bool has_apb_dma;
 218         u32 tlow_std_mode;
 219         u32 thigh_std_mode;
 220         u32 tlow_fast_fastplus_mode;
 221         u32 thigh_fast_fastplus_mode;
 222         u32 setup_hold_time_std_mode;
 223         u32 setup_hold_time_fast_fast_plus_mode;
 224         u32 setup_hold_time_hs_mode;
 225         bool has_interface_timing_reg;
 226 };
 227
 228 /**
 229  * struct tegra_i2c_dev - per device I2C context
 230  * @dev: device reference for power management
 231  * @hw: Tegra I2C HW feature
 232  * @adapter: core I2C layer adapter information
 233  * @div_clk: clock reference for div clock of I2C controller
 234  * @clocks: array of I2C controller clocks
 235  * @nclocks: number of clocks in the array
 236  * @rst: reset control for the I2C controller
 237  * @base: ioremapped registers cookie
 238  * @base_phys: physical base address of the I2C controller
 239  * @cont_id: I2C controller ID, used for packet header
 240  * @irq: IRQ number of transfer complete interrupt
 241  * @is_dvc: identifies the DVC I2C controller, has a different register layout
 242  * @is_vi: identifies the VI I2C controller, has a different register layout
 243  * @msg_complete: transfer completion notifier
 244  * @msg_err: error code for completed message
 245  * @msg_buf: pointer to current message data
 246  * @msg_buf_remaining: size of unsent data in the message buffer
 247  * @msg_read: indicates that the transfer is a read access
 248  * @bus_clk_rate: current I2C bus clock rate
 249  * @multimaster_mode: indicates that I2C controller is in multi-master mode
 250  * @tx_dma_chan: DMA transmit channel
 251  * @rx_dma_chan: DMA receive channel
 252  * @dma_phys: handle to DMA resources
 253  * @dma_buf: pointer to allocated DMA buffer
 254  * @dma_buf_size: DMA buffer size
 255  * @dma_mode: indicates active DMA transfer
 256  * @dma_complete: DMA completion notifier
 257  * @atomic_mode: indicates active atomic transfer
 258  */
 259 struct tegra_i2c_dev {
 260         struct device *dev;
 261         struct i2c_adapter adapter;
 262
 263         const struct tegra_i2c_hw_feature *hw;
 264         struct reset_control *rst;
 265         unsigned int cont_id;
 266         unsigned int irq;
 267
 268         phys_addr_t base_phys;
 269         void __iomem *base;
 270
 271         struct clk_bulk_data clocks[2];
 272         unsigned int nclocks;
 273
 274         struct clk *div_clk;
 275         u32 bus_clk_rate;
 276
 277         struct completion msg_complete;
 278         size_t msg_buf_remaining;
 279         int msg_err;
 280         u8 *msg_buf;
 281
 282         struct completion dma_complete;
 283         struct dma_chan *tx_dma_chan;
 284         struct dma_chan *rx_dma_chan;
 285         unsigned int dma_buf_size;
 286         struct device *dma_dev;
 287         dma_addr_t dma_phys;
 288         void *dma_buf;
 289
 290         bool multimaster_mode;
 291         bool atomic_mode;
 292         bool dma_mode;
 293         bool msg_read;
 294         bool is_dvc;
 295         bool is_vi;
 296 };
 297
 298 static void dvc_writel(struct tegra_i2c_dev *i2c_dev, u32 val,
 299                        unsigned int reg)
 300 {
 301         writel_relaxed(val, i2c_dev->base + reg);
 302 }
 303
 304 static u32 dvc_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 305 {
 306         return readl_relaxed(i2c_dev->base + reg);
 307 }
 308
 309 /*
 310  * If necessary, i2c_writel() and i2c_readl() will offset the register
 311  * in order to talk to the I2C block inside the DVC block.
 312  */
 313 static u32 tegra_i2c_reg_addr(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 314 {
 315         if (i2c_dev->is_dvc)
 316                 reg += (reg >= I2C_TX_FIFO) ? 0x10 : 0x40;
 317         else if (i2c_dev->is_vi)
 318                 reg = 0xc00 + (reg << 2);
 319
 320         return reg;
 321 }
 322
 323 static void i2c_writel(struct tegra_i2c_dev *i2c_dev, u32 val, unsigned int reg)
 324 {
 325         writel_relaxed(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 326
 327         /* read back register to make sure that register writes completed */
 328         if (reg != I2C_TX_FIFO)
 329                 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 330         else if (i2c_dev->is_vi)
 331                 readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, I2C_INT_STATUS));
 332 }
 333
 334 static u32 i2c_readl(struct tegra_i2c_dev *i2c_dev, unsigned int reg)
 335 {
 336         return readl_relaxed(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg));
 337 }
 338
 339 static void i2c_writesl(struct tegra_i2c_dev *i2c_dev, void *data,
 340                         unsigned int reg, unsigned int len)
 341 {
 342         writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 343 }
 344
 345 static void i2c_writesl_vi(struct tegra_i2c_dev *i2c_dev, void *data,
 346                            unsigned int reg, unsigned int len)
 347 {
 348         u32 *data32 = data;
 349
 350         /*
 351          * VI I2C controller has known hardware bug where writes get stuck
 352          * when immediate multiple writes happen to TX_FIFO register.
 353          * Recommended software work around is to read I2C register after
 354          * each write to TX_FIFO register to flush out the data.
 355          */
 356         while (len--)
 357                 i2c_writel(i2c_dev, *data32++, reg);
 358 }
 359
 360 static void i2c_readsl(struct tegra_i2c_dev *i2c_dev, void *data,
 361                        unsigned int reg, unsigned int len)
 362 {
 363         readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len);
 364 }
 365
 366 static void tegra_i2c_mask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 367 {
 368         u32 int_mask;
 369
 370         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) & ~mask;
 371         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 372 }
 373
 374 static void tegra_i2c_unmask_irq(struct tegra_i2c_dev *i2c_dev, u32 mask)
 375 {
 376         u32 int_mask;
 377
 378         int_mask = i2c_readl(i2c_dev, I2C_INT_MASK) | mask;
 379         i2c_writel(i2c_dev, int_mask, I2C_INT_MASK);
 380 }
 381
 382 static void tegra_i2c_dma_complete(void *args)
 383 {
 384         struct tegra_i2c_dev *i2c_dev = args;
 385
 386         complete(&i2c_dev->dma_complete);
 387 }
 388
 389 static int tegra_i2c_dma_submit(struct tegra_i2c_dev *i2c_dev, size_t len)
 390 {
 391         struct dma_async_tx_descriptor *dma_desc;
 392         enum dma_transfer_direction dir;
 393         struct dma_chan *chan;
 394
 395         dev_dbg(i2c_dev->dev, "starting DMA for length: %zu\n", len);
 396
 397         reinit_completion(&i2c_dev->dma_complete);
 398
 399         dir = i2c_dev->msg_read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
 400         chan = i2c_dev->msg_read ? i2c_dev->rx_dma_chan : i2c_dev->tx_dma_chan;
 401
 402         dma_desc = dmaengine_prep_slave_single(chan, i2c_dev->dma_phys,
 403                                                len, dir, DMA_PREP_INTERRUPT |
 404                                                DMA_CTRL_ACK);
 405         if (!dma_desc) {
 406                 dev_err(i2c_dev->dev, "failed to get %s DMA descriptor\n",
 407                         i2c_dev->msg_read ? "RX" : "TX");
 408                 return -EINVAL;
 409         }
 410
 411         dma_desc->callback = tegra_i2c_dma_complete;
 412         dma_desc->callback_param = i2c_dev;
 413
 414         dmaengine_submit(dma_desc);
 415         dma_async_issue_pending(chan);
 416
 417         return 0;
 418 }
 419
 420 static void tegra_i2c_release_dma(struct tegra_i2c_dev *i2c_dev)
 421 {
 422         if (i2c_dev->dma_buf) {
 423                 dma_free_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
 424                                   i2c_dev->dma_buf, i2c_dev->dma_phys);
 425                 i2c_dev->dma_buf = NULL;
 426         }
 427
 428         if (i2c_dev->tx_dma_chan) {
 429                 dma_release_channel(i2c_dev->tx_dma_chan);
 430                 i2c_dev->tx_dma_chan = NULL;
 431         }
 432
 433         if (i2c_dev->rx_dma_chan) {
 434                 dma_release_channel(i2c_dev->rx_dma_chan);
 435                 i2c_dev->rx_dma_chan = NULL;
 436         }
 437 }
 438
 439 static int tegra_i2c_init_dma(struct tegra_i2c_dev *i2c_dev)
 440 {
 441         struct dma_chan *chan;
 442         dma_addr_t dma_phys;
 443         u32 *dma_buf;
 444         int err;
 445
 446         if (!i2c_dev->hw->has_apb_dma || i2c_dev->is_vi)
 447                 return 0;
 448
 449         if (!IS_ENABLED(CONFIG_TEGRA20_APB_DMA)) {
 450                 dev_dbg(i2c_dev->dev, "DMA support not enabled\n");
 451                 return 0;
 452         }
 453
 454         chan = dma_request_chan(i2c_dev->dev, "rx");
 455         if (IS_ERR(chan)) {
 456                 err = PTR_ERR(chan);
 457                 goto err_out;
 458         }
 459
 460         i2c_dev->rx_dma_chan = chan;
 461
 462         chan = dma_request_chan(i2c_dev->dev, "tx");
 463         if (IS_ERR(chan)) {
 464                 err = PTR_ERR(chan);
 465                 goto err_out;
 466         }
 467
 468         i2c_dev->tx_dma_chan = chan;
 469
 470         WARN_ON(i2c_dev->tx_dma_chan->device != i2c_dev->rx_dma_chan->device);
 471         i2c_dev->dma_dev = chan->device->dev;
 472
 473         i2c_dev->dma_buf_size = i2c_dev->hw->quirks->max_write_len +
 474                                 I2C_PACKET_HEADER_SIZE;
 475
 476         dma_buf = dma_alloc_coherent(i2c_dev->dma_dev, i2c_dev->dma_buf_size,
 477                                      &dma_phys, GFP_KERNEL | __GFP_NOWARN);
 478         if (!dma_buf) {
 479                 dev_err(i2c_dev->dev, "failed to allocate DMA buffer\n");
 480                 err = -ENOMEM;
 481                 goto err_out;
 482         }
 483
 484         i2c_dev->dma_buf = dma_buf;
 485         i2c_dev->dma_phys = dma_phys;
 486
 487         return 0;
 488
 489 err_out:
 490         tegra_i2c_release_dma(i2c_dev);
 491         if (err != -EPROBE_DEFER) {
 492                 dev_err(i2c_dev->dev, "cannot use DMA: %d\n", err);
 493                 dev_err(i2c_dev->dev, "falling back to PIO\n");
 494                 return 0;
 495         }
 496
 497         return err;
 498 }
 499
 500 /*
 501  * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
 502  * block.  This block is identical to the rest of the I2C blocks, except that
 503  * it only supports master mode, it has registers moved around, and it needs
 504  * some extra init to get it into I2C mode.  The register moves are handled
 505  * by i2c_readl() and i2c_writel().
 506  */
 507 static void tegra_dvc_init(struct tegra_i2c_dev *i2c_dev)
 508 {
 509         u32 val;
 510
 511         val = dvc_readl(i2c_dev, DVC_CTRL_REG3);
 512         val |= DVC_CTRL_REG3_SW_PROG;
 513         val |= DVC_CTRL_REG3_I2C_DONE_INTR_EN;
 514         dvc_writel(i2c_dev, val, DVC_CTRL_REG3);
 515
 516         val = dvc_readl(i2c_dev, DVC_CTRL_REG1);
 517         val |= DVC_CTRL_REG1_INTR_EN;
 518         dvc_writel(i2c_dev, val, DVC_CTRL_REG1);
 519 }
 520
 521 static void tegra_i2c_vi_init(struct tegra_i2c_dev *i2c_dev)
 522 {
 523         u32 value;
 524
 525         value = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, 2) |
 526                 FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, 4);
 527         i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_0);
 528
 529         value = FIELD_PREP(I2C_INTERFACE_TIMING_TBUF, 4) |
 530                 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STO, 7) |
 531                 FIELD_PREP(I2C_INTERFACE_TIMING_THD_STA, 4) |
 532                 FIELD_PREP(I2C_INTERFACE_TIMING_TSU_STA, 4);
 533         i2c_writel(i2c_dev, value, I2C_INTERFACE_TIMING_1);
 534
 535         value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_THIGH, 3) |
 536                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TLOW, 8);
 537         i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_0);
 538
 539         value = FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STO, 11) |
 540                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_THD_STA, 11) |
 541                 FIELD_PREP(I2C_HS_INTERFACE_TIMING_TSU_STA, 11);
 542         i2c_writel(i2c_dev, value, I2C_HS_INTERFACE_TIMING_1);
 543
 544         value = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND;
 545         i2c_writel(i2c_dev, value, I2C_BUS_CLEAR_CNFG);
 546
 547         i2c_writel(i2c_dev, 0x0, I2C_TLOW_SEXT);
 548 }
 549
 550 static int tegra_i2c_poll_register(struct tegra_i2c_dev *i2c_dev,
 551                                    u32 reg, u32 mask, u32 delay_us,
 552                                    u32 timeout_us)
 553 {
 554         void __iomem *addr = i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg);
 555         u32 val;
 556
 557         if (!i2c_dev->atomic_mode && !in_irq())
 558                 return readl_relaxed_poll_timeout(addr, val, !(val & mask),
 559                                                   delay_us, timeout_us);
 560
 561         return readl_relaxed_poll_timeout_atomic(addr, val, !(val & mask),
 562                                                  delay_us, timeout_us);
 563 }
 564
 565 static int tegra_i2c_flush_fifos(struct tegra_i2c_dev *i2c_dev)
 566 {
 567         u32 mask, val, offset;
 568         int err;
 569
 570         if (i2c_dev->hw->has_mst_fifo) {
 571                 mask = I2C_MST_FIFO_CONTROL_TX_FLUSH |
 572                        I2C_MST_FIFO_CONTROL_RX_FLUSH;
 573                 offset = I2C_MST_FIFO_CONTROL;
 574         } else {
 575                 mask = I2C_FIFO_CONTROL_TX_FLUSH |
 576                        I2C_FIFO_CONTROL_RX_FLUSH;
 577                 offset = I2C_FIFO_CONTROL;
 578         }
 579
 580         val = i2c_readl(i2c_dev, offset);
 581         val |= mask;
 582         i2c_writel(i2c_dev, val, offset);
 583
 584         err = tegra_i2c_poll_register(i2c_dev, offset, mask, 1000, 1000000);
 585         if (err) {
 586                 dev_err(i2c_dev->dev, "failed to flush FIFO\n");
 587                 return err;
 588         }
 589
 590         return 0;
 591 }
 592
 593 static int tegra_i2c_wait_for_config_load(struct tegra_i2c_dev *i2c_dev)
 594 {
 595         int err;
 596
 597         if (!i2c_dev->hw->has_config_load_reg)
 598                 return 0;
 599
 600         i2c_writel(i2c_dev, I2C_MSTR_CONFIG_LOAD, I2C_CONFIG_LOAD);
 601
 602         err = tegra_i2c_poll_register(i2c_dev, I2C_CONFIG_LOAD, 0xffffffff,
 603                                       1000, I2C_CONFIG_LOAD_TIMEOUT);
 604         if (err) {
 605                 dev_err(i2c_dev->dev, "failed to load config\n");
 606                 return err;
 607         }
 608
 609         return 0;
 610 }
 611
 612 static int tegra_i2c_init(struct tegra_i2c_dev *i2c_dev)
 613 {
 614         u32 val, clk_divisor, clk_multiplier, tsu_thd, tlow, thigh, non_hs_mode;
 615         int err;
 616
 617         /*
 618          * The reset shouldn't ever fail in practice. The failure will be a
 619          * sign of a severe problem that needs to be resolved. Still we don't
 620          * want to fail the initialization completely because this may break
 621          * kernel boot up since voltage regulators use I2C. Hence, we will
 622          * emit a noisy warning on error, which won't stay unnoticed and
 623          * won't hose machine entirely.
 624          */
 625         err = reset_control_reset(i2c_dev->rst);
 626         WARN_ON_ONCE(err);
 627
 628         if (i2c_dev->is_dvc)
 629                 tegra_dvc_init(i2c_dev);
 630
 631         val = I2C_CNFG_NEW_MASTER_FSM | I2C_CNFG_PACKET_MODE_EN |
 632               FIELD_PREP(I2C_CNFG_DEBOUNCE_CNT, 2);
 633
 634         if (i2c_dev->hw->has_multi_master_mode)
 635                 val |= I2C_CNFG_MULTI_MASTER_MODE;
 636
 637         i2c_writel(i2c_dev, val, I2C_CNFG);
 638         i2c_writel(i2c_dev, 0, I2C_INT_MASK);
 639
 640         if (i2c_dev->is_vi)
 641                 tegra_i2c_vi_init(i2c_dev);
 642
 643         switch (i2c_dev->bus_clk_rate) {
 644         case I2C_MAX_STANDARD_MODE_FREQ + 1 ... I2C_MAX_FAST_MODE_PLUS_FREQ:
 645         default:
 646                 tlow = i2c_dev->hw->tlow_fast_fastplus_mode;
 647                 thigh = i2c_dev->hw->thigh_fast_fastplus_mode;
 648                 tsu_thd = i2c_dev->hw->setup_hold_time_fast_fast_plus_mode;
 649
 650                 if (i2c_dev->bus_clk_rate > I2C_MAX_FAST_MODE_FREQ)
 651                         non_hs_mode = i2c_dev->hw->clk_divisor_fast_plus_mode;
 652                 else
 653                         non_hs_mode = i2c_dev->hw->clk_divisor_fast_mode;
 654                 break;
 655
 656         case 0 ... I2C_MAX_STANDARD_MODE_FREQ:
 657                 tlow = i2c_dev->hw->tlow_std_mode;
 658                 thigh = i2c_dev->hw->thigh_std_mode;
 659                 tsu_thd = i2c_dev->hw->setup_hold_time_std_mode;
 660                 non_hs_mode = i2c_dev->hw->clk_divisor_std_mode;
 661                 break;
 662         }
 663
 664         /* make sure clock divisor programmed correctly */
 665         clk_divisor = FIELD_PREP(I2C_CLK_DIVISOR_HSMODE,
 666                                  i2c_dev->hw->clk_divisor_hs_mode) |
 667                       FIELD_PREP(I2C_CLK_DIVISOR_STD_FAST_MODE, non_hs_mode);
 668         i2c_writel(i2c_dev, clk_divisor, I2C_CLK_DIVISOR);
 669
 670         if (i2c_dev->hw->has_interface_timing_reg) {
 671                 val = FIELD_PREP(I2C_INTERFACE_TIMING_THIGH, thigh) |
 672                       FIELD_PREP(I2C_INTERFACE_TIMING_TLOW, tlow);
 673                 i2c_writel(i2c_dev, val, I2C_INTERFACE_TIMING_0);
 674         }
 675
 676         /*
 677          * Configure setup and hold times only when tsu_thd is non-zero.
 678          * Otherwise, preserve the chip default values.
 679          */
 680         if (i2c_dev->hw->has_interface_timing_reg && tsu_thd)
 681                 i2c_writel(i2c_dev, tsu_thd, I2C_INTERFACE_TIMING_1);
 682
 683         clk_multiplier = (tlow + thigh + 2) * (non_hs_mode + 1);
 684
 685         err = clk_set_rate(i2c_dev->div_clk,
 686                            i2c_dev->bus_clk_rate * clk_multiplier);
 687         if (err) {
 688                 dev_err(i2c_dev->dev, "failed to set div-clk rate: %d\n", err);
 689                 return err;
 690         }
 691
 692         if (!i2c_dev->is_dvc && !i2c_dev->is_vi) {
 693                 u32 sl_cfg = i2c_readl(i2c_dev, I2C_SL_CNFG);
 694
 695                 sl_cfg |= I2C_SL_CNFG_NACK | I2C_SL_CNFG_NEWSL;
 696                 i2c_writel(i2c_dev, sl_cfg, I2C_SL_CNFG);
 697                 i2c_writel(i2c_dev, 0xfc, I2C_SL_ADDR1);
 698                 i2c_writel(i2c_dev, 0x00, I2C_SL_ADDR2);
 699         }
 700
 701         err = tegra_i2c_flush_fifos(i2c_dev);
 702         if (err)
 703                 return err;
 704
 705         if (i2c_dev->multimaster_mode && i2c_dev->hw->has_slcg_override_reg)
 706                 i2c_writel(i2c_dev, I2C_MST_CORE_CLKEN_OVR, I2C_CLKEN_OVERRIDE);
 707
 708         err = tegra_i2c_wait_for_config_load(i2c_dev);
 709         if (err)
 710                 return err;
 711
 712         return 0;
 713 }
 714
 715 static int tegra_i2c_disable_packet_mode(struct tegra_i2c_dev *i2c_dev)
 716 {
 717         u32 cnfg;
 718
 719         /*
 720          * NACK interrupt is generated before the I2C controller generates
 721          * the STOP condition on the bus.  So, wait for 2 clock periods
 722          * before disabling the controller so that the STOP condition has
 723          * been delivered properly.
 724          */
 725         udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate));
 726
 727         cnfg = i2c_readl(i2c_dev, I2C_CNFG);
 728         if (cnfg & I2C_CNFG_PACKET_MODE_EN)
 729                 i2c_writel(i2c_dev, cnfg & ~I2C_CNFG_PACKET_MODE_EN, I2C_CNFG);
 730
 731         return tegra_i2c_wait_for_config_load(i2c_dev);
 732 }
 733
 734 static int tegra_i2c_empty_rx_fifo(struct tegra_i2c_dev *i2c_dev)
 735 {
 736         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 737         unsigned int words_to_transfer, rx_fifo_avail;
 738         u8 *buf = i2c_dev->msg_buf;
 739         u32 val;
 740
 741         /*
 742          * Catch overflow due to message fully sent before the check for
 743          * RX FIFO availability.
 744          */
 745         if (WARN_ON_ONCE(!(i2c_dev->msg_buf_remaining)))
 746                 return -EINVAL;
 747
 748         if (i2c_dev->hw->has_mst_fifo) {
 749                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 750                 rx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_RX, val);
 751         } else {
 752                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 753                 rx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_RX, val);
 754         }
 755
 756         /* round down to exclude partial word at the end of buffer */
 757         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 758         if (words_to_transfer > rx_fifo_avail)
 759                 words_to_transfer = rx_fifo_avail;
 760
 761         i2c_readsl(i2c_dev, buf, I2C_RX_FIFO, words_to_transfer);
 762
 763         buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 764         buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 765         rx_fifo_avail -= words_to_transfer;
 766
 767         /*
 768          * If there is a partial word at the end of buffer, handle it
 769          * manually to prevent overwriting past the end of buffer.
 770          */
 771         if (rx_fifo_avail > 0 && buf_remaining > 0) {
 772                 /*
 773                  * buf_remaining > 3 check not needed as rx_fifo_avail == 0
 774                  * when (words_to_transfer was > rx_fifo_avail) earlier
 775                  * in this function.
 776                  */
 777                 val = i2c_readl(i2c_dev, I2C_RX_FIFO);
 778                 val = cpu_to_le32(val);
 779                 memcpy(buf, &val, buf_remaining);
 780                 buf_remaining = 0;
 781                 rx_fifo_avail--;
 782         }
 783
 784         /* RX FIFO must be drained, otherwise it's an Overflow case. */
 785         if (WARN_ON_ONCE(rx_fifo_avail))
 786                 return -EINVAL;
 787
 788         i2c_dev->msg_buf_remaining = buf_remaining;
 789         i2c_dev->msg_buf = buf;
 790
 791         return 0;
 792 }
 793
 794 static int tegra_i2c_fill_tx_fifo(struct tegra_i2c_dev *i2c_dev)
 795 {
 796         size_t buf_remaining = i2c_dev->msg_buf_remaining;
 797         unsigned int words_to_transfer, tx_fifo_avail;
 798         u8 *buf = i2c_dev->msg_buf;
 799         u32 val;
 800
 801         if (i2c_dev->hw->has_mst_fifo) {
 802                 val = i2c_readl(i2c_dev, I2C_MST_FIFO_STATUS);
 803                 tx_fifo_avail = FIELD_GET(I2C_MST_FIFO_STATUS_TX, val);
 804         } else {
 805                 val = i2c_readl(i2c_dev, I2C_FIFO_STATUS);
 806                 tx_fifo_avail = FIELD_GET(I2C_FIFO_STATUS_TX, val);
 807         }
 808
 809         /* round down to exclude partial word at the end of buffer */
 810         words_to_transfer = buf_remaining / BYTES_PER_FIFO_WORD;
 811
 812         /*
 813          * This hunk pushes 4 bytes at a time into the TX FIFO.
 814          *
 815          * It's very common to have < 4 bytes, hence there is no word
 816          * to push if we have less than 4 bytes to transfer.
 817          */
 818         if (words_to_transfer) {
 819                 if (words_to_transfer > tx_fifo_avail)
 820                         words_to_transfer = tx_fifo_avail;
 821
 822                 /*
 823                  * Update state before writing to FIFO.  Note that this may
 824                  * cause us to finish writing all bytes (AKA buf_remaining
 825                  * goes to 0), hence we have a potential for an interrupt
 826                  * (PACKET_XFER_COMPLETE is not maskable), but GIC interrupt
 827                  * is disabled at this point.
 828                  */
 829                 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD;
 830                 tx_fifo_avail -= words_to_transfer;
 831
 832                 i2c_dev->msg_buf_remaining = buf_remaining;
 833                 i2c_dev->msg_buf = buf + words_to_transfer * BYTES_PER_FIFO_WORD;
 834
 835                 if (i2c_dev->is_vi)
 836                         i2c_writesl_vi(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 837                 else
 838                         i2c_writesl(i2c_dev, buf, I2C_TX_FIFO, words_to_transfer);
 839
 840                 buf += words_to_transfer * BYTES_PER_FIFO_WORD;
 841         }
 842
 843         /*
 844          * If there is a partial word at the end of buffer, handle it manually
 845          * to prevent reading past the end of buffer, which could cross a page
 846          * boundary and fault.
 847          */
 848         if (tx_fifo_avail > 0 && buf_remaining > 0) {
 849                 /*
 850                  * buf_remaining > 3 check not needed as tx_fifo_avail == 0
 851                  * when (words_to_transfer was > tx_fifo_avail) earlier
 852                  * in this function for non-zero words_to_transfer.
 853                  */
 854                 memcpy(&val, buf, buf_remaining);
 855                 val = le32_to_cpu(val);
 856
 857                 i2c_dev->msg_buf_remaining = 0;
 858                 i2c_dev->msg_buf = NULL;
 859
 860                 i2c_writel(i2c_dev, val, I2C_TX_FIFO);
 861         }
 862
 863         return 0;
 864 }
 865
 866 static irqreturn_t tegra_i2c_isr(int irq, void *dev_id)
 867 {
 868         const u32 status_err = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
 869         struct tegra_i2c_dev *i2c_dev = dev_id;
 870         u32 status;
 871
 872         status = i2c_readl(i2c_dev, I2C_INT_STATUS);
 873
 874         if (status == 0) {
 875                 dev_warn(i2c_dev->dev, "IRQ status 0 %08x %08x %08x\n",
 876                          i2c_readl(i2c_dev, I2C_PACKET_TRANSFER_STATUS),
 877                          i2c_readl(i2c_dev, I2C_STATUS),
 878                          i2c_readl(i2c_dev, I2C_CNFG));
 879                 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 880                 goto err;
 881         }
 882
 883         if (status & status_err) {
 884                 tegra_i2c_disable_packet_mode(i2c_dev);
 885                 if (status & I2C_INT_NO_ACK)
 886                         i2c_dev->msg_err |= I2C_ERR_NO_ACK;
 887                 if (status & I2C_INT_ARBITRATION_LOST)
 888                         i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST;
 889                 goto err;
 890         }
 891
 892         /*
 893          * I2C transfer is terminated during the bus clear, so skip
 894          * processing the other interrupts.
 895          */
 896         if (i2c_dev->hw->supports_bus_clear && (status & I2C_INT_BUS_CLR_DONE))
 897                 goto err;
 898
 899         if (!i2c_dev->dma_mode) {
 900                 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) {
 901                         if (tegra_i2c_empty_rx_fifo(i2c_dev)) {
 902                                 /*
 903                                  * Overflow error condition: message fully sent,
 904                                  * with no XFER_COMPLETE interrupt but hardware
 905                                  * asks to transfer more.
 906                                  */
 907                                 i2c_dev->msg_err |= I2C_ERR_RX_BUFFER_OVERFLOW;
 908                                 goto err;
 909                         }
 910                 }
 911
 912                 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) {
 913                         if (i2c_dev->msg_buf_remaining)
 914                                 tegra_i2c_fill_tx_fifo(i2c_dev);
 915                         else
 916                                 tegra_i2c_mask_irq(i2c_dev,
 917                                                    I2C_INT_TX_FIFO_DATA_REQ);
 918                 }
 919         }
 920
 921         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 922         if (i2c_dev->is_dvc)
 923                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 924
 925         /*
 926          * During message read XFER_COMPLETE interrupt is triggered prior to
 927          * DMA completion and during message write XFER_COMPLETE interrupt is
 928          * triggered after DMA completion.
 929          *
 930          * PACKETS_XFER_COMPLETE indicates completion of all bytes of transfer,
 931          * so forcing msg_buf_remaining to 0 in DMA mode.
 932          */
 933         if (status & I2C_INT_PACKET_XFER_COMPLETE) {
 934                 if (i2c_dev->dma_mode)
 935                         i2c_dev->msg_buf_remaining = 0;
 936                 /*
 937                  * Underflow error condition: XFER_COMPLETE before message
 938                  * fully sent.
 939                  */
 940                 if (WARN_ON_ONCE(i2c_dev->msg_buf_remaining)) {
 941                         i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT;
 942                         goto err;
 943                 }
 944                 complete(&i2c_dev->msg_complete);
 945         }
 946         goto done;
 947 err:
 948         /* mask all interrupts on error */
 949         tegra_i2c_mask_irq(i2c_dev,
 950                            I2C_INT_NO_ACK |
 951                            I2C_INT_ARBITRATION_LOST |
 952                            I2C_INT_PACKET_XFER_COMPLETE |
 953                            I2C_INT_TX_FIFO_DATA_REQ |
 954                            I2C_INT_RX_FIFO_DATA_REQ);
 955
 956         if (i2c_dev->hw->supports_bus_clear)
 957                 tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
 958
 959         i2c_writel(i2c_dev, status, I2C_INT_STATUS);
 960
 961         if (i2c_dev->is_dvc)
 962                 dvc_writel(i2c_dev, DVC_STATUS_I2C_DONE_INTR, DVC_STATUS);
 963
 964         if (i2c_dev->dma_mode) {
 965                 if (i2c_dev->msg_read)
 966                         dmaengine_terminate_async(i2c_dev->rx_dma_chan);
 967                 else
 968                         dmaengine_terminate_async(i2c_dev->tx_dma_chan);
 969
 970                 complete(&i2c_dev->dma_complete);
 971         }
 972
 973         complete(&i2c_dev->msg_complete);
 974 done:
 975         return IRQ_HANDLED;
 976 }
 977
 978 static void tegra_i2c_config_fifo_trig(struct tegra_i2c_dev *i2c_dev,
 979                                        size_t len)
 980 {
 981         struct dma_slave_config slv_config = {0};
 982         u32 val, reg, dma_burst, reg_offset;
 983         struct dma_chan *chan;
 984         int err;
 985
 986         if (i2c_dev->hw->has_mst_fifo)
 987                 reg = I2C_MST_FIFO_CONTROL;
 988         else
 989                 reg = I2C_FIFO_CONTROL;
 990
 991         if (i2c_dev->dma_mode) {
 992                 if (len & 0xF)
 993                         dma_burst = 1;
 994                 else if (len & 0x10)
 995                         dma_burst = 4;
 996                 else
 997                         dma_burst = 8;
 998
 999                 if (i2c_dev->msg_read) {
1000                         chan = i2c_dev->rx_dma_chan;
1001                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_RX_FIFO);
1002
1003                         slv_config.src_addr = i2c_dev->base_phys + reg_offset;
1004                         slv_config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1005                         slv_config.src_maxburst = dma_burst;
1006
1007                         if (i2c_dev->hw->has_mst_fifo)
1008                                 val = I2C_MST_FIFO_CONTROL_RX_TRIG(dma_burst);
1009                         else
1010                                 val = I2C_FIFO_CONTROL_RX_TRIG(dma_burst);
1011                 } else {
1012                         chan = i2c_dev->tx_dma_chan;
1013                         reg_offset = tegra_i2c_reg_addr(i2c_dev, I2C_TX_FIFO);
1014
1015                         slv_config.dst_addr = i2c_dev->base_phys + reg_offset;
1016                         slv_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
1017                         slv_config.dst_maxburst = dma_burst;
1018
1019                         if (i2c_dev->hw->has_mst_fifo)
1020                                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(dma_burst);
1021                         else
1022                                 val = I2C_FIFO_CONTROL_TX_TRIG(dma_burst);
1023                 }
1024
1025                 slv_config.device_fc = true;
1026                 err = dmaengine_slave_config(chan, &slv_config);
1027                 if (err) {
1028                         dev_err(i2c_dev->dev, "DMA config failed: %d\n", err);
1029                         dev_err(i2c_dev->dev, "falling back to PIO\n");
1030
1031                         tegra_i2c_release_dma(i2c_dev);
1032                         i2c_dev->dma_mode = false;
1033                 } else {
1034                         goto out;
1035                 }
1036         }
1037
1038         if (i2c_dev->hw->has_mst_fifo)
1039                 val = I2C_MST_FIFO_CONTROL_TX_TRIG(8) |
1040                       I2C_MST_FIFO_CONTROL_RX_TRIG(1);
1041         else
1042                 val = I2C_FIFO_CONTROL_TX_TRIG(8) |
1043                       I2C_FIFO_CONTROL_RX_TRIG(1);
1044 out:
1045         i2c_writel(i2c_dev, val, reg);
1046 }
1047
1048 static unsigned long tegra_i2c_poll_completion(struct tegra_i2c_dev *i2c_dev,
1049                                                struct completion *complete,
1050                                                unsigned int timeout_ms)
1051 {
1052         ktime_t ktime = ktime_get();
1053         ktime_t ktimeout = ktime_add_ms(ktime, timeout_ms);
1054
1055         do {
1056                 u32 status = i2c_readl(i2c_dev, I2C_INT_STATUS);
1057
1058                 if (status)
1059                         tegra_i2c_isr(i2c_dev->irq, i2c_dev);
1060
1061                 if (completion_done(complete)) {
1062                         s64 delta = ktime_ms_delta(ktimeout, ktime);
1063
1064                         return msecs_to_jiffies(delta) ?: 1;
1065                 }
1066
1067                 ktime = ktime_get();
1068
1069         } while (ktime_before(ktime, ktimeout));
1070
1071         return 0;
1072 }
1073
1074 static unsigned long tegra_i2c_wait_completion(struct tegra_i2c_dev *i2c_dev,
1075                                                struct completion *complete,
1076                                                unsigned int timeout_ms)
1077 {
1078         unsigned long ret;
1079
1080         if (i2c_dev->atomic_mode) {
1081                 ret = tegra_i2c_poll_completion(i2c_dev, complete, timeout_ms);
1082         } else {
1083                 enable_irq(i2c_dev->irq);
1084                 ret = wait_for_completion_timeout(complete,
1085                                                   msecs_to_jiffies(timeout_ms));
1086                 disable_irq(i2c_dev->irq);
1087
1088                 /*
1089                  * Under some rare circumstances (like running KASAN +
1090                  * NFS root) CPU, which handles interrupt, may stuck in
1091                  * uninterruptible state for a significant time.  In this
1092                  * case we will get timeout if I2C transfer is running on
1093                  * a sibling CPU, despite of IRQ being raised.
1094                  *
1095                  * In order to handle this rare condition, the IRQ status
1096                  * needs to be checked after timeout.
1097                  */
1098                 if (ret == 0)
1099                         ret = tegra_i2c_poll_completion(i2c_dev, complete, 0);
1100         }
1101
1102         return ret;
1103 }
1104
1105 static int tegra_i2c_issue_bus_clear(struct i2c_adapter *adap)
1106 {
1107         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1108         u32 val, time_left;
1109         int err;
1110
1111         reinit_completion(&i2c_dev->msg_complete);
1112
1113         val = FIELD_PREP(I2C_BC_SCLK_THRESHOLD, 9) | I2C_BC_STOP_COND |
1114               I2C_BC_TERMINATE;
1115         i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1116
1117         err = tegra_i2c_wait_for_config_load(i2c_dev);
1118         if (err)
1119                 return err;
1120
1121         val |= I2C_BC_ENABLE;
1122         i2c_writel(i2c_dev, val, I2C_BUS_CLEAR_CNFG);
1123         tegra_i2c_unmask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1124
1125         time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete, 50);
1126         tegra_i2c_mask_irq(i2c_dev, I2C_INT_BUS_CLR_DONE);
1127
1128         if (time_left == 0) {
1129                 dev_err(i2c_dev->dev, "failed to clear bus\n");
1130                 return -ETIMEDOUT;
1131         }
1132
1133         val = i2c_readl(i2c_dev, I2C_BUS_CLEAR_STATUS);
1134         if (!(val & I2C_BC_STATUS)) {
1135                 dev_err(i2c_dev->dev, "un-recovered arbitration lost\n");
1136                 return -EIO;
1137         }
1138
1139         return -EAGAIN;
1140 }
1141
1142 static void tegra_i2c_push_packet_header(struct tegra_i2c_dev *i2c_dev,
1143                                          struct i2c_msg *msg,
1144                                          enum msg_end_type end_state)
1145 {
1146         u32 *dma_buf = i2c_dev->dma_buf;
1147         u32 packet_header;
1148
1149         packet_header = FIELD_PREP(PACKET_HEADER0_HEADER_SIZE, 0) |
1150                         FIELD_PREP(PACKET_HEADER0_PROTOCOL,
1151                                    PACKET_HEADER0_PROTOCOL_I2C) |
1152                         FIELD_PREP(PACKET_HEADER0_CONT_ID, i2c_dev->cont_id) |
1153                         FIELD_PREP(PACKET_HEADER0_PACKET_ID, 1);
1154
1155         if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1156                 *dma_buf++ = packet_header;
1157         else
1158                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1159
1160         packet_header = msg->len - 1;
1161
1162         if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1163                 *dma_buf++ = packet_header;
1164         else
1165                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1166
1167         packet_header = I2C_HEADER_IE_ENABLE;
1168
1169         if (end_state == MSG_END_CONTINUE)
1170                 packet_header |= I2C_HEADER_CONTINUE_XFER;
1171         else if (end_state == MSG_END_REPEAT_START)
1172                 packet_header |= I2C_HEADER_REPEAT_START;
1173
1174         if (msg->flags & I2C_M_TEN) {
1175                 packet_header |= msg->addr;
1176                 packet_header |= I2C_HEADER_10BIT_ADDR;
1177         } else {
1178                 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT;
1179         }
1180
1181         if (msg->flags & I2C_M_IGNORE_NAK)
1182                 packet_header |= I2C_HEADER_CONT_ON_NAK;
1183
1184         if (msg->flags & I2C_M_RD)
1185                 packet_header |= I2C_HEADER_READ;
1186
1187         if (i2c_dev->dma_mode && !i2c_dev->msg_read)
1188                 *dma_buf++ = packet_header;
1189         else
1190                 i2c_writel(i2c_dev, packet_header, I2C_TX_FIFO);
1191 }
1192
1193 static int tegra_i2c_error_recover(struct tegra_i2c_dev *i2c_dev,
1194                                    struct i2c_msg *msg)
1195 {
1196         if (i2c_dev->msg_err == I2C_ERR_NONE)
1197                 return 0;
1198
1199         tegra_i2c_init(i2c_dev);
1200
1201         /* start recovery upon arbitration loss in single master mode */
1202         if (i2c_dev->msg_err == I2C_ERR_ARBITRATION_LOST) {
1203                 if (!i2c_dev->multimaster_mode)
1204                         return i2c_recover_bus(&i2c_dev->adapter);
1205
1206                 return -EAGAIN;
1207         }
1208
1209         if (i2c_dev->msg_err == I2C_ERR_NO_ACK) {
1210                 if (msg->flags & I2C_M_IGNORE_NAK)
1211                         return 0;
1212
1213                 return -EREMOTEIO;
1214         }
1215
1216         return -EIO;
1217 }
1218
1219 static int tegra_i2c_xfer_msg(struct tegra_i2c_dev *i2c_dev,
1220                               struct i2c_msg *msg,
1221                               enum msg_end_type end_state)
1222 {
1223         unsigned long time_left, xfer_time = 100;
1224         size_t xfer_size;
1225         u32 int_mask;
1226         int err;
1227
1228         err = tegra_i2c_flush_fifos(i2c_dev);
1229         if (err)
1230                 return err;
1231
1232         i2c_dev->msg_buf = msg->buf;
1233         i2c_dev->msg_buf_remaining = msg->len;
1234         i2c_dev->msg_err = I2C_ERR_NONE;
1235         i2c_dev->msg_read = !!(msg->flags & I2C_M_RD);
1236         reinit_completion(&i2c_dev->msg_complete);
1237
1238         if (i2c_dev->msg_read)
1239                 xfer_size = msg->len;
1240         else
1241                 xfer_size = msg->len + I2C_PACKET_HEADER_SIZE;
1242
1243         xfer_size = ALIGN(xfer_size, BYTES_PER_FIFO_WORD);
1244
1245         i2c_dev->dma_mode = xfer_size > I2C_PIO_MODE_PREFERRED_LEN &&
1246                             i2c_dev->dma_buf && !i2c_dev->atomic_mode;
1247
1248         tegra_i2c_config_fifo_trig(i2c_dev, xfer_size);
1249
1250         /*
1251          * Transfer time in mSec = Total bits / transfer rate
1252          * Total bits = 9 bits per byte (including ACK bit) + Start & stop bits
1253          */
1254         xfer_time += DIV_ROUND_CLOSEST(((xfer_size * 9) + 2) * MSEC_PER_SEC,
1255                                        i2c_dev->bus_clk_rate);
1256
1257         int_mask = I2C_INT_NO_ACK | I2C_INT_ARBITRATION_LOST;
1258         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1259
1260         if (i2c_dev->dma_mode) {
1261                 if (i2c_dev->msg_read) {
1262                         dma_sync_single_for_device(i2c_dev->dma_dev,
1263                                                    i2c_dev->dma_phys,
1264                                                    xfer_size, DMA_FROM_DEVICE);
1265
1266                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1267                         if (err)
1268                                 return err;
1269                 } else {
1270                         dma_sync_single_for_cpu(i2c_dev->dma_dev,
1271                                                 i2c_dev->dma_phys,
1272                                                 xfer_size, DMA_TO_DEVICE);
1273                 }
1274         }
1275
1276         tegra_i2c_push_packet_header(i2c_dev, msg, end_state);
1277
1278         if (!i2c_dev->msg_read) {
1279                 if (i2c_dev->dma_mode) {
1280                         memcpy(i2c_dev->dma_buf + I2C_PACKET_HEADER_SIZE,
1281                                msg->buf, msg->len);
1282
1283                         dma_sync_single_for_device(i2c_dev->dma_dev,
1284                                                    i2c_dev->dma_phys,
1285                                                    xfer_size, DMA_TO_DEVICE);
1286
1287                         err = tegra_i2c_dma_submit(i2c_dev, xfer_size);
1288                         if (err)
1289                                 return err;
1290                 } else {
1291                         tegra_i2c_fill_tx_fifo(i2c_dev);
1292                 }
1293         }
1294
1295         if (i2c_dev->hw->has_per_pkt_xfer_complete_irq)
1296                 int_mask |= I2C_INT_PACKET_XFER_COMPLETE;
1297
1298         if (!i2c_dev->dma_mode) {
1299                 if (msg->flags & I2C_M_RD)
1300                         int_mask |= I2C_INT_RX_FIFO_DATA_REQ;
1301                 else if (i2c_dev->msg_buf_remaining)
1302                         int_mask |= I2C_INT_TX_FIFO_DATA_REQ;
1303         }
1304
1305         tegra_i2c_unmask_irq(i2c_dev, int_mask);
1306         dev_dbg(i2c_dev->dev, "unmasked IRQ: %02x\n",
1307                 i2c_readl(i2c_dev, I2C_INT_MASK));
1308
1309         if (i2c_dev->dma_mode) {
1310                 time_left = tegra_i2c_wait_completion(i2c_dev,
1311                                                       &i2c_dev->dma_complete,
1312                                                       xfer_time);
1313
1314                 /*
1315                  * Synchronize DMA first, since dmaengine_terminate_sync()
1316                  * performs synchronization after the transfer's termination
1317                  * and we want to get a completion if transfer succeeded.
1318                  */
1319                 dmaengine_synchronize(i2c_dev->msg_read ?
1320                                       i2c_dev->rx_dma_chan :
1321                                       i2c_dev->tx_dma_chan);
1322
1323                 dmaengine_terminate_sync(i2c_dev->msg_read ?
1324                                          i2c_dev->rx_dma_chan :
1325                                          i2c_dev->tx_dma_chan);
1326
1327                 if (!time_left && !completion_done(&i2c_dev->dma_complete)) {
1328                         dev_err(i2c_dev->dev, "DMA transfer timed out\n");
1329                         tegra_i2c_init(i2c_dev);
1330                         return -ETIMEDOUT;
1331                 }
1332
1333                 if (i2c_dev->msg_read && i2c_dev->msg_err == I2C_ERR_NONE) {
1334                         dma_sync_single_for_cpu(i2c_dev->dma_dev,
1335                                                 i2c_dev->dma_phys,
1336                                                 xfer_size, DMA_FROM_DEVICE);
1337
1338                         memcpy(i2c_dev->msg_buf, i2c_dev->dma_buf, msg->len);
1339                 }
1340         }
1341
1342         time_left = tegra_i2c_wait_completion(i2c_dev, &i2c_dev->msg_complete,
1343                                               xfer_time);
1344
1345         tegra_i2c_mask_irq(i2c_dev, int_mask);
1346
1347         if (time_left == 0) {
1348                 dev_err(i2c_dev->dev, "I2C transfer timed out\n");
1349                 tegra_i2c_init(i2c_dev);
1350                 return -ETIMEDOUT;
1351         }
1352
1353         dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n",
1354                 time_left, completion_done(&i2c_dev->msg_complete),
1355                 i2c_dev->msg_err);
1356
1357         i2c_dev->dma_mode = false;
1358
1359         err = tegra_i2c_error_recover(i2c_dev, msg);
1360         if (err)
1361                 return err;
1362
1363         return 0;
1364 }
1365
1366 static int tegra_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
1367                           int num)
1368 {
1369         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1370         int i, ret;
1371
1372         ret = pm_runtime_get_sync(i2c_dev->dev);
1373         if (ret < 0) {
1374                 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret);
1375                 pm_runtime_put_noidle(i2c_dev->dev);
1376                 return ret;
1377         }
1378
1379         for (i = 0; i < num; i++) {
1380                 enum msg_end_type end_type = MSG_END_STOP;
1381
1382                 if (i < (num - 1)) {
1383                         /* check whether follow up message is coming */
1384                         if (msgs[i + 1].flags & I2C_M_NOSTART)
1385                                 end_type = MSG_END_CONTINUE;
1386                         else
1387                                 end_type = MSG_END_REPEAT_START;
1388                 }
1389                 ret = tegra_i2c_xfer_msg(i2c_dev, &msgs[i], end_type);
1390                 if (ret)
1391                         break;
1392         }
1393
1394         pm_runtime_put(i2c_dev->dev);
1395
1396         return ret ?: i;
1397 }
1398
1399 static int tegra_i2c_xfer_atomic(struct i2c_adapter *adap,
1400                                  struct i2c_msg msgs[], int num)
1401 {
1402         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1403         int ret;
1404
1405         i2c_dev->atomic_mode = true;
1406         ret = tegra_i2c_xfer(adap, msgs, num);
1407         i2c_dev->atomic_mode = false;
1408
1409         return ret;
1410 }
1411
1412 static u32 tegra_i2c_func(struct i2c_adapter *adap)
1413 {
1414         struct tegra_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
1415         u32 ret = I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK) |
1416                   I2C_FUNC_10BIT_ADDR | I2C_FUNC_PROTOCOL_MANGLING;
1417
1418         if (i2c_dev->hw->has_continue_xfer_support)
1419                 ret |= I2C_FUNC_NOSTART;
1420
1421         return ret;
1422 }
1423
1424 static const struct i2c_algorithm tegra_i2c_algo = {
1425         .master_xfer            = tegra_i2c_xfer,
1426         .master_xfer_atomic     = tegra_i2c_xfer_atomic,
1427         .functionality          = tegra_i2c_func,
1428 };
1429
1430 /* payload size is only 12 bit */
1431 static const struct i2c_adapter_quirks tegra_i2c_quirks = {
1432         .flags = I2C_AQ_NO_ZERO_LEN,
1433         .max_read_len = SZ_4K,
1434         .max_write_len = SZ_4K - I2C_PACKET_HEADER_SIZE,
1435 };
1436
1437 static const struct i2c_adapter_quirks tegra194_i2c_quirks = {
1438         .flags = I2C_AQ_NO_ZERO_LEN,
1439         .max_write_len = SZ_64K - I2C_PACKET_HEADER_SIZE,
1440 };
1441
1442 static struct i2c_bus_recovery_info tegra_i2c_recovery_info = {
1443         .recover_bus = tegra_i2c_issue_bus_clear,
1444 };
1445
1446 static const struct tegra_i2c_hw_feature tegra20_i2c_hw = {
1447         .has_continue_xfer_support = false,
1448         .has_per_pkt_xfer_complete_irq = false,
1449         .clk_divisor_hs_mode = 3,
1450         .clk_divisor_std_mode = 0,
1451         .clk_divisor_fast_mode = 0,
1452         .clk_divisor_fast_plus_mode = 0,
1453         .has_config_load_reg = false,
1454         .has_multi_master_mode = false,
1455         .has_slcg_override_reg = false,
1456         .has_mst_fifo = false,
1457         .quirks = &tegra_i2c_quirks,
1458         .supports_bus_clear = false,
1459         .has_apb_dma = true,
1460         .tlow_std_mode = 0x4,
1461         .thigh_std_mode = 0x2,
1462         .tlow_fast_fastplus_mode = 0x4,
1463         .thigh_fast_fastplus_mode = 0x2,
1464         .setup_hold_time_std_mode = 0x0,
1465         .setup_hold_time_fast_fast_plus_mode = 0x0,
1466         .setup_hold_time_hs_mode = 0x0,
1467         .has_interface_timing_reg = false,
1468 };
1469
1470 static const struct tegra_i2c_hw_feature tegra30_i2c_hw = {
1471         .has_continue_xfer_support = true,
1472         .has_per_pkt_xfer_complete_irq = false,
1473         .clk_divisor_hs_mode = 3,
1474         .clk_divisor_std_mode = 0,
1475         .clk_divisor_fast_mode = 0,
1476         .clk_divisor_fast_plus_mode = 0,
1477         .has_config_load_reg = false,
1478         .has_multi_master_mode = false,
1479         .has_slcg_override_reg = false,
1480         .has_mst_fifo = false,
1481         .quirks = &tegra_i2c_quirks,
1482         .supports_bus_clear = false,
1483         .has_apb_dma = true,
1484         .tlow_std_mode = 0x4,
1485         .thigh_std_mode = 0x2,
1486         .tlow_fast_fastplus_mode = 0x4,
1487         .thigh_fast_fastplus_mode = 0x2,
1488         .setup_hold_time_std_mode = 0x0,
1489         .setup_hold_time_fast_fast_plus_mode = 0x0,
1490         .setup_hold_time_hs_mode = 0x0,
1491         .has_interface_timing_reg = false,
1492 };
1493
1494 static const struct tegra_i2c_hw_feature tegra114_i2c_hw = {
1495         .has_continue_xfer_support = true,
1496         .has_per_pkt_xfer_complete_irq = true,
1497         .clk_divisor_hs_mode = 1,
1498         .clk_divisor_std_mode = 0x19,
1499         .clk_divisor_fast_mode = 0x19,
1500         .clk_divisor_fast_plus_mode = 0x10,
1501         .has_config_load_reg = false,
1502         .has_multi_master_mode = false,
1503         .has_slcg_override_reg = false,
1504         .has_mst_fifo = false,
1505         .quirks = &tegra_i2c_quirks,
1506         .supports_bus_clear = true,
1507         .has_apb_dma = true,
1508         .tlow_std_mode = 0x4,
1509         .thigh_std_mode = 0x2,
1510         .tlow_fast_fastplus_mode = 0x4,
1511         .thigh_fast_fastplus_mode = 0x2,
1512         .setup_hold_time_std_mode = 0x0,
1513         .setup_hold_time_fast_fast_plus_mode = 0x0,
1514         .setup_hold_time_hs_mode = 0x0,
1515         .has_interface_timing_reg = false,
1516 };
1517
1518 static const struct tegra_i2c_hw_feature tegra124_i2c_hw = {
1519         .has_continue_xfer_support = true,
1520         .has_per_pkt_xfer_complete_irq = true,
1521         .clk_divisor_hs_mode = 1,
1522         .clk_divisor_std_mode = 0x19,
1523         .clk_divisor_fast_mode = 0x19,
1524         .clk_divisor_fast_plus_mode = 0x10,
1525         .has_config_load_reg = true,
1526         .has_multi_master_mode = false,
1527         .has_slcg_override_reg = true,
1528         .has_mst_fifo = false,
1529         .quirks = &tegra_i2c_quirks,
1530         .supports_bus_clear = true,
1531         .has_apb_dma = true,
1532         .tlow_std_mode = 0x4,
1533         .thigh_std_mode = 0x2,
1534         .tlow_fast_fastplus_mode = 0x4,
1535         .thigh_fast_fastplus_mode = 0x2,
1536         .setup_hold_time_std_mode = 0x0,
1537         .setup_hold_time_fast_fast_plus_mode = 0x0,
1538         .setup_hold_time_hs_mode = 0x0,
1539         .has_interface_timing_reg = true,
1540 };
1541
1542 static const struct tegra_i2c_hw_feature tegra210_i2c_hw = {
1543         .has_continue_xfer_support = true,
1544         .has_per_pkt_xfer_complete_irq = true,
1545         .clk_divisor_hs_mode = 1,
1546         .clk_divisor_std_mode = 0x19,
1547         .clk_divisor_fast_mode = 0x19,
1548         .clk_divisor_fast_plus_mode = 0x10,
1549         .has_config_load_reg = true,
1550         .has_multi_master_mode = false,
1551         .has_slcg_override_reg = true,
1552         .has_mst_fifo = false,
1553         .quirks = &tegra_i2c_quirks,
1554         .supports_bus_clear = true,
1555         .has_apb_dma = true,
1556         .tlow_std_mode = 0x4,
1557         .thigh_std_mode = 0x2,
1558         .tlow_fast_fastplus_mode = 0x4,
1559         .thigh_fast_fastplus_mode = 0x2,
1560         .setup_hold_time_std_mode = 0,
1561         .setup_hold_time_fast_fast_plus_mode = 0,
1562         .setup_hold_time_hs_mode = 0,
1563         .has_interface_timing_reg = true,
1564 };
1565
1566 static const struct tegra_i2c_hw_feature tegra186_i2c_hw = {
1567         .has_continue_xfer_support = true,
1568         .has_per_pkt_xfer_complete_irq = true,
1569         .clk_divisor_hs_mode = 1,
1570         .clk_divisor_std_mode = 0x16,
1571         .clk_divisor_fast_mode = 0x19,
1572         .clk_divisor_fast_plus_mode = 0x10,
1573         .has_config_load_reg = true,
1574         .has_multi_master_mode = false,
1575         .has_slcg_override_reg = true,
1576         .has_mst_fifo = false,
1577         .quirks = &tegra_i2c_quirks,
1578         .supports_bus_clear = true,
1579         .has_apb_dma = false,
1580         .tlow_std_mode = 0x4,
1581         .thigh_std_mode = 0x3,
1582         .tlow_fast_fastplus_mode = 0x4,
1583         .thigh_fast_fastplus_mode = 0x2,
1584         .setup_hold_time_std_mode = 0,
1585         .setup_hold_time_fast_fast_plus_mode = 0,
1586         .setup_hold_time_hs_mode = 0,
1587         .has_interface_timing_reg = true,
1588 };
1589
1590 static const struct tegra_i2c_hw_feature tegra194_i2c_hw = {
1591         .has_continue_xfer_support = true,
1592         .has_per_pkt_xfer_complete_irq = true,
1593         .clk_divisor_hs_mode = 1,
1594         .clk_divisor_std_mode = 0x4f,
1595         .clk_divisor_fast_mode = 0x3c,
1596         .clk_divisor_fast_plus_mode = 0x16,
1597         .has_config_load_reg = true,
1598         .has_multi_master_mode = true,
1599         .has_slcg_override_reg = true,
1600         .has_mst_fifo = true,
1601         .quirks = &tegra194_i2c_quirks,
1602         .supports_bus_clear = true,
1603         .has_apb_dma = false,
1604         .tlow_std_mode = 0x8,
1605         .thigh_std_mode = 0x7,
1606         .tlow_fast_fastplus_mode = 0x2,
1607         .thigh_fast_fastplus_mode = 0x2,
1608         .setup_hold_time_std_mode = 0x08080808,
1609         .setup_hold_time_fast_fast_plus_mode = 0x02020202,
1610         .setup_hold_time_hs_mode = 0x090909,
1611         .has_interface_timing_reg = true,
1612 };
1613
1614 static const struct of_device_id tegra_i2c_of_match[] = {
1615         { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
1616         { .compatible = "nvidia,tegra186-i2c", .data = &tegra186_i2c_hw, },
1617         { .compatible = "nvidia,tegra210-i2c-vi", .data = &tegra210_i2c_hw, },
1618         { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
1619         { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
1620         { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
1621         { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
1622         { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
1623         { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
1624         {},
1625 };
1626 MODULE_DEVICE_TABLE(of, tegra_i2c_of_match);
1627
1628 static void tegra_i2c_parse_dt(struct tegra_i2c_dev *i2c_dev)
1629 {
1630         struct device_node *np = i2c_dev->dev->of_node;
1631         bool multi_mode;
1632         int err;
1633
1634         err = of_property_read_u32(np, "clock-frequency",
1635                                    &i2c_dev->bus_clk_rate);
1636         if (err)
1637                 i2c_dev->bus_clk_rate = I2C_MAX_STANDARD_MODE_FREQ;
1638
1639         multi_mode = of_property_read_bool(np, "multi-master");
1640         i2c_dev->multimaster_mode = multi_mode;
1641
1642         if (of_device_is_compatible(np, "nvidia,tegra20-i2c-dvc"))
1643                 i2c_dev->is_dvc = true;
1644
1645         if (of_device_is_compatible(np, "nvidia,tegra210-i2c-vi"))
1646                 i2c_dev->is_vi = true;
1647 }
1648
1649 static int tegra_i2c_init_clocks(struct tegra_i2c_dev *i2c_dev)
1650 {
1651         int err;
1652
1653         i2c_dev->clocks[i2c_dev->nclocks++].id = "div-clk";
1654
1655         if (i2c_dev->hw == &tegra20_i2c_hw || i2c_dev->hw == &tegra30_i2c_hw)
1656                 i2c_dev->clocks[i2c_dev->nclocks++].id = "fast-clk";
1657
1658         if (i2c_dev->is_vi)
1659                 i2c_dev->clocks[i2c_dev->nclocks++].id = "slow";
1660
1661         err = devm_clk_bulk_get(i2c_dev->dev, i2c_dev->nclocks,
1662                                 i2c_dev->clocks);
1663         if (err)
1664                 return err;
1665
1666         err = clk_bulk_prepare(i2c_dev->nclocks, i2c_dev->clocks);
1667         if (err)
1668                 return err;
1669
1670         i2c_dev->div_clk = i2c_dev->clocks[0].clk;
1671
1672         if (!i2c_dev->multimaster_mode)
1673                 return 0;
1674
1675         err = clk_enable(i2c_dev->div_clk);
1676         if (err) {
1677                 dev_err(i2c_dev->dev, "failed to enable div-clk: %d\n", err);
1678                 goto unprepare_clocks;
1679         }
1680
1681         return 0;
1682
1683 unprepare_clocks:
1684         clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1685
1686         return err;
1687 }
1688
1689 static void tegra_i2c_release_clocks(struct tegra_i2c_dev *i2c_dev)
1690 {
1691         if (i2c_dev->multimaster_mode)
1692                 clk_disable(i2c_dev->div_clk);
1693
1694         clk_bulk_unprepare(i2c_dev->nclocks, i2c_dev->clocks);
1695 }
1696
1697 static int tegra_i2c_init_hardware(struct tegra_i2c_dev *i2c_dev)
1698 {
1699         int ret;
1700
1701         ret = pm_runtime_get_sync(i2c_dev->dev);
1702         if (ret < 0)
1703                 dev_err(i2c_dev->dev, "runtime resume failed: %d\n", ret);
1704         else
1705                 ret = tegra_i2c_init(i2c_dev);
1706
1707         pm_runtime_put(i2c_dev->dev);
1708
1709         return ret;
1710 }
1711
1712 static int tegra_i2c_probe(struct platform_device *pdev)
1713 {
1714         struct tegra_i2c_dev *i2c_dev;
1715         struct resource *res;
1716         int err;
1717
1718         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1719         if (!i2c_dev)
1720                 return -ENOMEM;
1721
1722         platform_set_drvdata(pdev, i2c_dev);
1723
1724         init_completion(&i2c_dev->msg_complete);
1725         init_completion(&i2c_dev->dma_complete);
1726
1727         i2c_dev->hw = of_device_get_match_data(&pdev->dev);
1728         i2c_dev->cont_id = pdev->id;
1729         i2c_dev->dev = &pdev->dev;
1730
1731         i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1732         if (IS_ERR(i2c_dev->base))
1733                 return PTR_ERR(i2c_dev->base);
1734
1735         i2c_dev->base_phys = res->start;
1736
1737         err = platform_get_irq(pdev, 0);
1738         if (err < 0)
1739                 return err;
1740
1741         i2c_dev->irq = err;
1742
1743         /* interrupt will be enabled during of transfer time */
1744         irq_set_status_flags(i2c_dev->irq, IRQ_NOAUTOEN);
1745
1746         err = devm_request_irq(i2c_dev->dev, i2c_dev->irq, tegra_i2c_isr,
1747                                IRQF_NO_SUSPEND, dev_name(i2c_dev->dev),
1748                                i2c_dev);
1749         if (err)
1750                 return err;
1751
1752         i2c_dev->rst = devm_reset_control_get_exclusive(i2c_dev->dev, "i2c");
1753         if (IS_ERR(i2c_dev->rst)) {
1754                 dev_err_probe(i2c_dev->dev, PTR_ERR(i2c_dev->rst),
1755                               "failed to get reset control\n");
1756                 return PTR_ERR(i2c_dev->rst);
1757         }
1758
1759         tegra_i2c_parse_dt(i2c_dev);
1760
1761         err = tegra_i2c_init_clocks(i2c_dev);
1762         if (err)
1763                 return err;
1764
1765         err = tegra_i2c_init_dma(i2c_dev);
1766         if (err)
1767                 goto release_clocks;
1768
1769         /*
1770          * VI I2C is in VE power domain which is not always ON and not
1771          * IRQ-safe.  Thus, IRQ-safe device shouldn't be attached to a
1772          * non IRQ-safe domain because this prevents powering off the power
1773          * domain.
1774          *
1775          * VI I2C device shouldn't be marked as IRQ-safe because VI I2C won't
1776          * be used for atomic transfers.
1777          */
1778         if (!i2c_dev->is_vi)
1779                 pm_runtime_irq_safe(i2c_dev->dev);
1780
1781         pm_runtime_enable(i2c_dev->dev);
1782
1783         err = tegra_i2c_init_hardware(i2c_dev);
1784         if (err)
1785                 goto release_rpm;
1786
1787         i2c_set_adapdata(&i2c_dev->adapter, i2c_dev);
1788         i2c_dev->adapter.dev.of_node = i2c_dev->dev->of_node;
1789         i2c_dev->adapter.dev.parent = i2c_dev->dev;
1790         i2c_dev->adapter.retries = 1;
1791         i2c_dev->adapter.timeout = 6 * HZ;
1792         i2c_dev->adapter.quirks = i2c_dev->hw->quirks;
1793         i2c_dev->adapter.owner = THIS_MODULE;
1794         i2c_dev->adapter.class = I2C_CLASS_DEPRECATED;
1795         i2c_dev->adapter.algo = &tegra_i2c_algo;
1796         i2c_dev->adapter.nr = pdev->id;
1797
1798         if (i2c_dev->hw->supports_bus_clear)
1799                 i2c_dev->adapter.bus_recovery_info = &tegra_i2c_recovery_info;
1800
1801         strlcpy(i2c_dev->adapter.name, dev_name(i2c_dev->dev),
1802                 sizeof(i2c_dev->adapter.name));
1803
1804         err = i2c_add_numbered_adapter(&i2c_dev->adapter);
1805         if (err)
1806                 goto release_rpm;
1807
1808         return 0;
1809
1810 release_rpm:
1811         pm_runtime_disable(i2c_dev->dev);
1812
1813         tegra_i2c_release_dma(i2c_dev);
1814 release_clocks:
1815         tegra_i2c_release_clocks(i2c_dev);
1816
1817         return err;
1818 }
1819
1820 static int tegra_i2c_remove(struct platform_device *pdev)
1821 {
1822         struct tegra_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1823
1824         i2c_del_adapter(&i2c_dev->adapter);
1825         pm_runtime_disable(i2c_dev->dev);
1826
1827         tegra_i2c_release_dma(i2c_dev);
1828         tegra_i2c_release_clocks(i2c_dev);
1829
1830         return 0;
1831 }
1832
1833 static int __maybe_unused tegra_i2c_runtime_resume(struct device *dev)
1834 {
1835         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1836         int err;
1837
1838         err = pinctrl_pm_select_default_state(dev);
1839         if (err)
1840                 return err;
1841
1842         err = clk_bulk_enable(i2c_dev->nclocks, i2c_dev->clocks);
1843         if (err)
1844                 return err;
1845
1846         /*
1847          * VI I2C device is attached to VE power domain which goes through
1848          * power ON/OFF during runtime PM resume/suspend, meaning that
1849          * controller needs to be re-initialized after power ON.
1850          */
1851         if (i2c_dev->is_vi) {
1852                 err = tegra_i2c_init(i2c_dev);
1853                 if (err)
1854                         goto disable_clocks;
1855         }
1856
1857         return 0;
1858
1859 disable_clocks:
1860         clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1861
1862         return err;
1863 }
1864
1865 static int __maybe_unused tegra_i2c_runtime_suspend(struct device *dev)
1866 {
1867         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1868
1869         clk_bulk_disable(i2c_dev->nclocks, i2c_dev->clocks);
1870
1871         return pinctrl_pm_select_idle_state(dev);
1872 }
1873
1874 static int __maybe_unused tegra_i2c_suspend(struct device *dev)
1875 {
1876         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1877         int err;
1878
1879         i2c_mark_adapter_suspended(&i2c_dev->adapter);
1880
1881         if (!pm_runtime_status_suspended(dev)) {
1882                 err = tegra_i2c_runtime_suspend(dev);
1883                 if (err)
1884                         return err;
1885         }
1886
1887         return 0;
1888 }
1889
1890 static int __maybe_unused tegra_i2c_resume(struct device *dev)
1891 {
1892         struct tegra_i2c_dev *i2c_dev = dev_get_drvdata(dev);
1893         int err;
1894
1895         /*
1896          * We need to ensure that clocks are enabled so that registers can be
1897          * restored in tegra_i2c_init().
1898          */
1899         err = tegra_i2c_runtime_resume(dev);
1900         if (err)
1901                 return err;
1902
1903         err = tegra_i2c_init(i2c_dev);
1904         if (err)
1905                 return err;
1906
1907         /*
1908          * In case we are runtime suspended, disable clocks again so that we
1909          * don't unbalance the clock reference counts during the next runtime
1910          * resume transition.
1911          */
1912         if (pm_runtime_status_suspended(dev)) {
1913                 err = tegra_i2c_runtime_suspend(dev);
1914                 if (err)
1915                         return err;
1916         }
1917
1918         i2c_mark_adapter_resumed(&i2c_dev->adapter);
1919
1920         return 0;
1921 }
1922
1923 static const struct dev_pm_ops tegra_i2c_pm = {
1924         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(tegra_i2c_suspend, tegra_i2c_resume)
1925         SET_RUNTIME_PM_OPS(tegra_i2c_runtime_suspend, tegra_i2c_runtime_resume,
1926                            NULL)
1927 };
1928
1929 static struct platform_driver tegra_i2c_driver = {
1930         .probe = tegra_i2c_probe,
1931         .remove = tegra_i2c_remove,
1932         .driver = {
1933                 .name = "tegra-i2c",
1934                 .of_match_table = tegra_i2c_of_match,
1935                 .pm = &tegra_i2c_pm,
1936         },
1937 };
1938 module_platform_driver(tegra_i2c_driver);
1939
1940 MODULE_DESCRIPTION("NVIDIA Tegra I2C Bus Controller driver");
1941 MODULE_AUTHOR("Colin Cross");
1942 MODULE_LICENSE("GPL v2");