1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2007-2012 ST-Ericsson AB
4 * ST DDC I2C master mode driver, used in e.g. U300 series platforms.
5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 * Author: Jonas Aaberg <jonas.aberg@stericsson.com>
8 #include <linux/init.h>
9 #include <linux/module.h>
10 #include <linux/platform_device.h>
11 #include <linux/delay.h>
12 #include <linux/i2c.h>
13 #include <linux/spinlock.h>
14 #include <linux/completion.h>
15 #include <linux/err.h>
16 #include <linux/interrupt.h>
17 #include <linux/clk.h>
19 #include <linux/slab.h>
21 /* the name of this kernel module */
24 /* CR (Control Register) 8bit (R/W) */
25 #define I2C_CR (0x00000000)
26 #define I2C_CR_RESET_VALUE (0x00)
27 #define I2C_CR_RESET_UMASK (0x00)
28 #define I2C_CR_DDC1_ENABLE (0x80)
29 #define I2C_CR_TRANS_ENABLE (0x40)
30 #define I2C_CR_PERIPHERAL_ENABLE (0x20)
31 #define I2C_CR_DDC2B_ENABLE (0x10)
32 #define I2C_CR_START_ENABLE (0x08)
33 #define I2C_CR_ACK_ENABLE (0x04)
34 #define I2C_CR_STOP_ENABLE (0x02)
35 #define I2C_CR_INTERRUPT_ENABLE (0x01)
36 /* SR1 (Status Register 1) 8bit (R/-) */
37 #define I2C_SR1 (0x00000004)
38 #define I2C_SR1_RESET_VALUE (0x00)
39 #define I2C_SR1_RESET_UMASK (0x00)
40 #define I2C_SR1_EVF_IND (0x80)
41 #define I2C_SR1_ADD10_IND (0x40)
42 #define I2C_SR1_TRA_IND (0x20)
43 #define I2C_SR1_BUSY_IND (0x10)
44 #define I2C_SR1_BTF_IND (0x08)
45 #define I2C_SR1_ADSL_IND (0x04)
46 #define I2C_SR1_MSL_IND (0x02)
47 #define I2C_SR1_SB_IND (0x01)
48 /* SR2 (Status Register 2) 8bit (R/-) */
49 #define I2C_SR2 (0x00000008)
50 #define I2C_SR2_RESET_VALUE (0x00)
51 #define I2C_SR2_RESET_UMASK (0x40)
52 #define I2C_SR2_MASK (0xBF)
53 #define I2C_SR2_SCLFAL_IND (0x80)
54 #define I2C_SR2_ENDAD_IND (0x20)
55 #define I2C_SR2_AF_IND (0x10)
56 #define I2C_SR2_STOPF_IND (0x08)
57 #define I2C_SR2_ARLO_IND (0x04)
58 #define I2C_SR2_BERR_IND (0x02)
59 #define I2C_SR2_DDC2BF_IND (0x01)
60 /* CCR (Clock Control Register) 8bit (R/W) */
61 #define I2C_CCR (0x0000000C)
62 #define I2C_CCR_RESET_VALUE (0x00)
63 #define I2C_CCR_RESET_UMASK (0x00)
64 #define I2C_CCR_MASK (0xFF)
65 #define I2C_CCR_FMSM (0x80)
66 #define I2C_CCR_CC_MASK (0x7F)
67 /* OAR1 (Own Address Register 1) 8bit (R/W) */
68 #define I2C_OAR1 (0x00000010)
69 #define I2C_OAR1_RESET_VALUE (0x00)
70 #define I2C_OAR1_RESET_UMASK (0x00)
71 #define I2C_OAR1_ADD_MASK (0xFF)
72 /* OAR2 (Own Address Register 2) 8bit (R/W) */
73 #define I2C_OAR2 (0x00000014)
74 #define I2C_OAR2_RESET_VALUE (0x40)
75 #define I2C_OAR2_RESET_UMASK (0x19)
76 #define I2C_OAR2_MASK (0xE6)
77 #define I2C_OAR2_FR_25_10MHZ (0x00)
78 #define I2C_OAR2_FR_10_1667MHZ (0x20)
79 #define I2C_OAR2_FR_1667_2667MHZ (0x40)
80 #define I2C_OAR2_FR_2667_40MHZ (0x60)
81 #define I2C_OAR2_FR_40_5333MHZ (0x80)
82 #define I2C_OAR2_FR_5333_66MHZ (0xA0)
83 #define I2C_OAR2_FR_66_80MHZ (0xC0)
84 #define I2C_OAR2_FR_80_100MHZ (0xE0)
85 #define I2C_OAR2_FR_MASK (0xE0)
86 #define I2C_OAR2_ADD_MASK (0x06)
87 /* DR (Data Register) 8bit (R/W) */
88 #define I2C_DR (0x00000018)
89 #define I2C_DR_RESET_VALUE (0x00)
90 #define I2C_DR_RESET_UMASK (0xFF)
91 #define I2C_DR_D_MASK (0xFF)
92 /* ECCR (Extended Clock Control Register) 8bit (R/W) */
93 #define I2C_ECCR (0x0000001C)
94 #define I2C_ECCR_RESET_VALUE (0x00)
95 #define I2C_ECCR_RESET_UMASK (0xE0)
96 #define I2C_ECCR_MASK (0x1F)
97 #define I2C_ECCR_CC_MASK (0x1F)
100 * These events are more or less responses to commands
101 * sent into the hardware, presumably reflecting the state
102 * of an internal state machine.
105 STU300_EVENT_NONE = 0,
118 STU300_ERROR_NONE = 0,
119 STU300_ERROR_ACKNOWLEDGE_FAILURE,
120 STU300_ERROR_BUS_ERROR,
121 STU300_ERROR_ARBITRATION_LOST,
125 /* timeout waiting for the controller to respond */
126 #define STU300_TIMEOUT (msecs_to_jiffies(1000))
129 * The number of address send athemps tried before giving up.
130 * If the first one fails it seems like 5 to 8 attempts are required.
132 #define NUM_ADDR_RESEND_ATTEMPTS 12
134 /* I2C clock speed, in Hz 0-400kHz*/
135 static unsigned int scl_frequency = I2C_MAX_STANDARD_MODE_FREQ;
136 module_param(scl_frequency, uint, 0644);
139 * struct stu300_dev - the stu300 driver state holder
140 * @pdev: parent platform device
141 * @adapter: corresponding I2C adapter
142 * @clk: hardware block clock
143 * @irq: assigned interrupt line
144 * @cmd_issue_lock: this locks the following cmd_ variables
145 * @cmd_complete: acknowledge completion for an I2C command
146 * @cmd_event: expected event coming in as a response to a command
147 * @cmd_err: error code as response to a command
148 * @speed: current bus speed in Hz
149 * @msg_index: index of current message
150 * @msg_len: length of current message
154 struct platform_device *pdev;
155 struct i2c_adapter adapter;
156 void __iomem *virtbase;
159 spinlock_t cmd_issue_lock;
160 struct completion cmd_complete;
161 enum stu300_event cmd_event;
162 enum stu300_error cmd_err;
168 /* Local forward function declarations */
169 static int stu300_init_hw(struct stu300_dev *dev);
172 * The block needs writes in both MSW and LSW in order
173 * for all data lines to reach their destination.
175 static inline void stu300_wr8(u32 value, void __iomem *address)
177 writel((value << 16) | value, address);
181 * This merely masks off the duplicates which appear
182 * in bytes 1-3. You _MUST_ use 32-bit bus access on this
183 * device, else it will not work.
185 static inline u32 stu300_r8(void __iomem *address)
187 return readl(address) & 0x000000FFU;
190 static void stu300_irq_enable(struct stu300_dev *dev)
193 val = stu300_r8(dev->virtbase + I2C_CR);
194 val |= I2C_CR_INTERRUPT_ENABLE;
195 /* Twice paranoia (possible HW glitch) */
196 stu300_wr8(val, dev->virtbase + I2C_CR);
197 stu300_wr8(val, dev->virtbase + I2C_CR);
200 static void stu300_irq_disable(struct stu300_dev *dev)
203 val = stu300_r8(dev->virtbase + I2C_CR);
204 val &= ~I2C_CR_INTERRUPT_ENABLE;
205 /* Twice paranoia (possible HW glitch) */
206 stu300_wr8(val, dev->virtbase + I2C_CR);
207 stu300_wr8(val, dev->virtbase + I2C_CR);
212 * Tells whether a certain event or events occurred in
213 * response to a command. The events represent states in
214 * the internal state machine of the hardware. The events
215 * are not very well described in the hardware
216 * documentation and can only be treated as abstract state
219 * @ret 0 = event has not occurred or unknown error, any
220 * other value means the correct event occurred or an error.
223 static int stu300_event_occurred(struct stu300_dev *dev,
224 enum stu300_event mr_event) {
228 /* What event happened? */
229 status1 = stu300_r8(dev->virtbase + I2C_SR1);
231 if (!(status1 & I2C_SR1_EVF_IND))
232 /* No event at all */
235 status2 = stu300_r8(dev->virtbase + I2C_SR2);
237 /* Block any multiple interrupts */
238 stu300_irq_disable(dev);
240 /* Check for errors first */
241 if (status2 & I2C_SR2_AF_IND) {
242 dev->cmd_err = STU300_ERROR_ACKNOWLEDGE_FAILURE;
244 } else if (status2 & I2C_SR2_BERR_IND) {
245 dev->cmd_err = STU300_ERROR_BUS_ERROR;
247 } else if (status2 & I2C_SR2_ARLO_IND) {
248 dev->cmd_err = STU300_ERROR_ARBITRATION_LOST;
254 if (status1 & I2C_SR1_ADSL_IND)
261 if (status1 & I2C_SR1_BTF_IND) {
266 if (status2 & I2C_SR2_STOPF_IND)
270 if (status1 & I2C_SR1_SB_IND)
271 /* Clear start bit */
275 if (status2 & I2C_SR2_ENDAD_IND) {
276 /* First check for any errors */
281 if (status1 & I2C_SR1_ADD10_IND)
287 /* If we get here, we're on thin ice.
288 * Here we are in a status where we have
289 * gotten a response that does not match
292 dev->cmd_err = STU300_ERROR_UNKNOWN;
293 dev_err(&dev->pdev->dev,
294 "Unhandled interrupt! %d sr1: 0x%x sr2: 0x%x\n",
295 mr_event, status1, status2);
299 static irqreturn_t stu300_irh(int irq, void *data)
301 struct stu300_dev *dev = data;
304 /* Just make sure that the block is clocked */
305 clk_enable(dev->clk);
307 /* See if this was what we were waiting for */
308 spin_lock(&dev->cmd_issue_lock);
310 res = stu300_event_occurred(dev, dev->cmd_event);
311 if (res || dev->cmd_err != STU300_ERROR_NONE)
312 complete(&dev->cmd_complete);
314 spin_unlock(&dev->cmd_issue_lock);
316 clk_disable(dev->clk);
322 * Sends a command and then waits for the bits masked by *flagmask*
323 * to go high or low by IRQ awaiting.
325 static int stu300_start_and_await_event(struct stu300_dev *dev,
327 enum stu300_event mr_event)
331 /* Lock command issue, fill in an event we wait for */
332 spin_lock_irq(&dev->cmd_issue_lock);
333 init_completion(&dev->cmd_complete);
334 dev->cmd_err = STU300_ERROR_NONE;
335 dev->cmd_event = mr_event;
336 spin_unlock_irq(&dev->cmd_issue_lock);
338 /* Turn on interrupt, send command and wait. */
339 cr_value |= I2C_CR_INTERRUPT_ENABLE;
340 stu300_wr8(cr_value, dev->virtbase + I2C_CR);
341 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
344 dev_err(&dev->pdev->dev,
345 "wait_for_completion_interruptible_timeout() "
346 "returned %d waiting for event %04x\n", ret, mr_event);
351 dev_err(&dev->pdev->dev, "controller timed out "
352 "waiting for event %d, reinit hardware\n", mr_event);
353 (void) stu300_init_hw(dev);
357 if (dev->cmd_err != STU300_ERROR_NONE) {
358 dev_err(&dev->pdev->dev, "controller (start) "
359 "error %d waiting for event %d, reinit hardware\n",
360 dev->cmd_err, mr_event);
361 (void) stu300_init_hw(dev);
369 * This waits for a flag to be set, if it is not set on entry, an interrupt is
370 * configured to wait for the flag using a completion.
372 static int stu300_await_event(struct stu300_dev *dev,
373 enum stu300_event mr_event)
377 /* Is it already here? */
378 spin_lock_irq(&dev->cmd_issue_lock);
379 dev->cmd_err = STU300_ERROR_NONE;
380 dev->cmd_event = mr_event;
382 init_completion(&dev->cmd_complete);
384 /* Turn on the I2C interrupt for current operation */
385 stu300_irq_enable(dev);
387 /* Unlock the command block and wait for the event to occur */
388 spin_unlock_irq(&dev->cmd_issue_lock);
390 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
393 dev_err(&dev->pdev->dev,
394 "wait_for_completion_interruptible_timeout()"
395 "returned %d waiting for event %04x\n", ret, mr_event);
400 if (mr_event != STU300_EVENT_6) {
401 dev_err(&dev->pdev->dev, "controller "
402 "timed out waiting for event %d, reinit "
403 "hardware\n", mr_event);
404 (void) stu300_init_hw(dev);
409 if (dev->cmd_err != STU300_ERROR_NONE) {
410 if (mr_event != STU300_EVENT_6) {
411 dev_err(&dev->pdev->dev, "controller "
412 "error (await_event) %d waiting for event %d, "
413 "reinit hardware\n", dev->cmd_err, mr_event);
414 (void) stu300_init_hw(dev);
423 * Waits for the busy bit to go low by repeated polling.
425 #define BUSY_RELEASE_ATTEMPTS 10
426 static int stu300_wait_while_busy(struct stu300_dev *dev)
428 unsigned long timeout;
431 for (i = 0; i < BUSY_RELEASE_ATTEMPTS; i++) {
432 timeout = jiffies + STU300_TIMEOUT;
434 while (!time_after(jiffies, timeout)) {
436 if ((stu300_r8(dev->virtbase + I2C_SR1) &
437 I2C_SR1_BUSY_IND) == 0)
442 dev_err(&dev->pdev->dev, "transaction timed out "
443 "waiting for device to be free (not busy). "
444 "Attempt: %d\n", i+1);
446 dev_err(&dev->pdev->dev, "base address = "
447 "0x%p, reinit hardware\n", dev->virtbase);
449 (void) stu300_init_hw(dev);
452 dev_err(&dev->pdev->dev, "giving up after %d attempts "
453 "to reset the bus.\n", BUSY_RELEASE_ATTEMPTS);
458 struct stu300_clkset {
463 static const struct stu300_clkset stu300_clktable[] = {
465 { 2500000, I2C_OAR2_FR_25_10MHZ },
466 { 10000000, I2C_OAR2_FR_10_1667MHZ },
467 { 16670000, I2C_OAR2_FR_1667_2667MHZ },
468 { 26670000, I2C_OAR2_FR_2667_40MHZ },
469 { 40000000, I2C_OAR2_FR_40_5333MHZ },
470 { 53330000, I2C_OAR2_FR_5333_66MHZ },
471 { 66000000, I2C_OAR2_FR_66_80MHZ },
472 { 80000000, I2C_OAR2_FR_80_100MHZ },
473 { 100000000, 0xFFU },
477 static int stu300_set_clk(struct stu300_dev *dev, unsigned long clkrate)
483 /* Locate the appropriate clock setting */
484 while (i < ARRAY_SIZE(stu300_clktable) - 1 &&
485 stu300_clktable[i].rate < clkrate)
488 if (stu300_clktable[i].setting == 0xFFU) {
489 dev_err(&dev->pdev->dev, "too %s clock rate requested "
490 "(%lu Hz).\n", i ? "high" : "low", clkrate);
494 stu300_wr8(stu300_clktable[i].setting,
495 dev->virtbase + I2C_OAR2);
497 dev_dbg(&dev->pdev->dev, "Clock rate %lu Hz, I2C bus speed %d Hz "
498 "virtbase %p\n", clkrate, dev->speed, dev->virtbase);
500 if (dev->speed > I2C_MAX_STANDARD_MODE_FREQ)
502 val = ((clkrate/dev->speed) - 9)/3 + 1;
504 /* Standard Mode I2C */
505 val = ((clkrate/dev->speed) - 7)/2 + 1;
507 /* According to spec the divider must be > 2 */
509 dev_err(&dev->pdev->dev, "too low clock rate (%lu Hz).\n",
514 /* We have 12 bits clock divider only! */
515 if (val & 0xFFFFF000U) {
516 dev_err(&dev->pdev->dev, "too high clock rate (%lu Hz).\n",
521 if (dev->speed > I2C_MAX_STANDARD_MODE_FREQ) {
523 stu300_wr8((val & I2C_CCR_CC_MASK) | I2C_CCR_FMSM,
524 dev->virtbase + I2C_CCR);
525 dev_dbg(&dev->pdev->dev, "set clock divider to 0x%08x, "
526 "Fast Mode I2C\n", val);
529 stu300_wr8((val & I2C_CCR_CC_MASK),
530 dev->virtbase + I2C_CCR);
531 dev_dbg(&dev->pdev->dev, "set clock divider to "
532 "0x%08x, Standard Mode I2C\n", val);
536 stu300_wr8(((val >> 7) & 0x1F),
537 dev->virtbase + I2C_ECCR);
543 static int stu300_init_hw(struct stu300_dev *dev)
546 unsigned long clkrate;
549 /* Disable controller */
550 stu300_wr8(0x00, dev->virtbase + I2C_CR);
552 * Set own address to some default value (0x00).
553 * We do not support slave mode anyway.
555 stu300_wr8(0x00, dev->virtbase + I2C_OAR1);
557 * The I2C controller only operates properly in 26 MHz but we
558 * program this driver as if we didn't know. This will also set the two
559 * high bits of the own address to zero as well.
560 * There is no known hardware issue with running in 13 MHz
561 * However, speeds over 200 kHz are not used.
563 clkrate = clk_get_rate(dev->clk);
564 ret = stu300_set_clk(dev, clkrate);
569 * Enable block, do it TWICE (hardware glitch)
570 * Setting bit 7 can enable DDC mode. (Not used currently.)
572 stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
573 dev->virtbase + I2C_CR);
574 stu300_wr8(I2C_CR_PERIPHERAL_ENABLE,
575 dev->virtbase + I2C_CR);
576 /* Make a dummy read of the status register SR1 & SR2 */
577 dummy = stu300_r8(dev->virtbase + I2C_SR2);
578 dummy = stu300_r8(dev->virtbase + I2C_SR1);
585 /* Send slave address. */
586 static int stu300_send_address(struct stu300_dev *dev,
587 struct i2c_msg *msg, int resend)
592 if (msg->flags & I2C_M_TEN) {
593 /* This is probably how 10 bit addresses look */
594 val = (0xf0 | (((u32) msg->addr & 0x300) >> 7)) &
596 if (msg->flags & I2C_M_RD)
597 /* This is the direction bit */
600 val = i2c_8bit_addr_from_msg(msg);
604 if (msg->flags & I2C_M_RD)
605 dev_dbg(&dev->pdev->dev, "read resend\n");
607 dev_dbg(&dev->pdev->dev, "write resend\n");
610 stu300_wr8(val, dev->virtbase + I2C_DR);
612 /* For 10bit addressing, await 10bit request (EVENT 9) */
613 if (msg->flags & I2C_M_TEN) {
614 ret = stu300_await_event(dev, STU300_EVENT_9);
616 * The slave device wants a 10bit address, send the rest
617 * of the bits (the LSBits)
619 val = msg->addr & I2C_DR_D_MASK;
620 /* This clears "event 9" */
621 stu300_wr8(val, dev->virtbase + I2C_DR);
625 /* FIXME: Why no else here? two events for 10bit?
626 * Await event 6 (normal) or event 9 (10bit)
630 dev_dbg(&dev->pdev->dev, "await event 6\n");
631 ret = stu300_await_event(dev, STU300_EVENT_6);
634 * Clear any pending EVENT 6 no matter what happened during
637 val = stu300_r8(dev->virtbase + I2C_CR);
638 val |= I2C_CR_PERIPHERAL_ENABLE;
639 stu300_wr8(val, dev->virtbase + I2C_CR);
644 static int stu300_xfer_msg(struct i2c_adapter *adap,
645 struct i2c_msg *msg, int stop)
652 struct stu300_dev *dev = i2c_get_adapdata(adap);
654 clk_enable(dev->clk);
656 /* Remove this if (0) to trace each and every message. */
658 dev_dbg(&dev->pdev->dev, "I2C message to: 0x%04x, len: %d, "
659 "flags: 0x%04x, stop: %d\n",
660 msg->addr, msg->len, msg->flags, stop);
664 * For some reason, sending the address sometimes fails when running
665 * on the 13 MHz clock. No interrupt arrives. This is a work around,
666 * which tries to restart and send the address up to 10 times before
667 * really giving up. Usually 5 to 8 attempts are enough.
671 dev_dbg(&dev->pdev->dev, "wait while busy\n");
672 /* Check that the bus is free, or wait until some timeout */
673 ret = stu300_wait_while_busy(dev);
678 dev_dbg(&dev->pdev->dev, "re-int hw\n");
680 * According to ST, there is no problem if the clock is
681 * changed between 13 and 26 MHz during a transfer.
683 ret = stu300_init_hw(dev);
687 /* Send a start condition */
688 cr = I2C_CR_PERIPHERAL_ENABLE;
689 /* Setting the START bit puts the block in master mode */
690 if (!(msg->flags & I2C_M_NOSTART))
691 cr |= I2C_CR_START_ENABLE;
692 if ((msg->flags & I2C_M_RD) && (msg->len > 1))
693 /* On read more than 1 byte, we need ack. */
694 cr |= I2C_CR_ACK_ENABLE;
695 /* Check that it gets through */
696 if (!(msg->flags & I2C_M_NOSTART)) {
698 dev_dbg(&dev->pdev->dev, "send start event\n");
699 ret = stu300_start_and_await_event(dev, cr,
704 dev_dbg(&dev->pdev->dev, "send address\n");
708 ret = stu300_send_address(dev, msg, attempts != 0);
712 dev_dbg(&dev->pdev->dev, "failed sending address, "
713 "retrying. Attempt: %d msg_index: %d/%d\n",
714 attempts, dev->msg_index, dev->msg_len);
717 } while (ret != 0 && attempts < NUM_ADDR_RESEND_ATTEMPTS);
719 if (attempts < NUM_ADDR_RESEND_ATTEMPTS && attempts > 0) {
720 dev_dbg(&dev->pdev->dev, "managed to get address "
721 "through after %d attempts\n", attempts);
722 } else if (attempts == NUM_ADDR_RESEND_ATTEMPTS) {
723 dev_dbg(&dev->pdev->dev, "I give up, tried %d times "
724 "to resend address.\n",
725 NUM_ADDR_RESEND_ATTEMPTS);
730 if (msg->flags & I2C_M_RD) {
731 /* READ: we read the actual bytes one at a time */
732 for (i = 0; i < msg->len; i++) {
733 if (i == msg->len-1) {
735 * Disable ACK and set STOP condition before
738 val = I2C_CR_PERIPHERAL_ENABLE;
741 val |= I2C_CR_STOP_ENABLE;
744 dev->virtbase + I2C_CR);
746 /* Wait for this byte... */
747 ret = stu300_await_event(dev, STU300_EVENT_7);
750 /* This clears event 7 */
751 msg->buf[i] = (u8) stu300_r8(dev->virtbase + I2C_DR);
754 /* WRITE: we send the actual bytes one at a time */
755 for (i = 0; i < msg->len; i++) {
757 stu300_wr8(msg->buf[i],
758 dev->virtbase + I2C_DR);
760 ret = stu300_await_event(dev, STU300_EVENT_8);
761 /* Next write to DR will clear event 8 */
763 dev_err(&dev->pdev->dev, "error awaiting "
764 "event 8 (%d)\n", ret);
769 if (!(msg->flags & I2C_M_IGNORE_NAK)) {
770 if (stu300_r8(dev->virtbase + I2C_SR2) &
772 dev_err(&dev->pdev->dev, "I2C payload "
773 "send returned NAK!\n");
779 /* Send stop condition */
780 val = I2C_CR_PERIPHERAL_ENABLE;
781 val |= I2C_CR_STOP_ENABLE;
782 stu300_wr8(val, dev->virtbase + I2C_CR);
786 /* Check that the bus is free, or wait until some timeout occurs */
787 ret = stu300_wait_while_busy(dev);
789 dev_err(&dev->pdev->dev, "timeout waiting for transfer "
794 /* Dummy read status registers */
795 val = stu300_r8(dev->virtbase + I2C_SR2);
796 val = stu300_r8(dev->virtbase + I2C_SR1);
800 /* Disable controller */
801 stu300_wr8(0x00, dev->virtbase + I2C_CR);
802 clk_disable(dev->clk);
806 static int stu300_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
812 struct stu300_dev *dev = i2c_get_adapdata(adap);
815 for (i = 0; i < num; i++) {
817 * Another driver appears to send stop for each message,
818 * here we only do that for the last message. Possibly some
819 * peripherals require this behaviour, then their drivers
820 * have to send single messages in order to get "stop" for
825 ret = stu300_xfer_msg(adap, &msgs[i], (i == (num - 1)));
836 static int stu300_xfer_todo(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
838 /* TODO: implement polling for this case if need be. */
839 WARN(1, "%s: atomic transfers not implemented\n", dev_name(&adap->dev));
843 static u32 stu300_func(struct i2c_adapter *adap)
845 /* This is the simplest thing you can think of... */
846 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR;
849 static const struct i2c_algorithm stu300_algo = {
850 .master_xfer = stu300_xfer,
851 .master_xfer_atomic = stu300_xfer_todo,
852 .functionality = stu300_func,
855 static const struct i2c_adapter_quirks stu300_quirks = {
856 .flags = I2C_AQ_NO_ZERO_LEN,
859 static int stu300_probe(struct platform_device *pdev)
861 struct stu300_dev *dev;
862 struct i2c_adapter *adap;
866 dev = devm_kzalloc(&pdev->dev, sizeof(struct stu300_dev), GFP_KERNEL);
871 dev->clk = devm_clk_get(&pdev->dev, NULL);
872 if (IS_ERR(dev->clk)) {
873 dev_err(&pdev->dev, "could not retrieve i2c bus clock\n");
874 return PTR_ERR(dev->clk);
878 dev->virtbase = devm_platform_ioremap_resource(pdev, 0);
879 dev_dbg(&pdev->dev, "initialize bus device I2C%d on virtual "
880 "base %p\n", bus_nr, dev->virtbase);
881 if (IS_ERR(dev->virtbase))
882 return PTR_ERR(dev->virtbase);
884 dev->irq = platform_get_irq(pdev, 0);
885 ret = devm_request_irq(&pdev->dev, dev->irq, stu300_irh, 0, NAME, dev);
889 dev->speed = scl_frequency;
891 clk_prepare_enable(dev->clk);
892 ret = stu300_init_hw(dev);
893 clk_disable(dev->clk);
895 dev_err(&dev->pdev->dev, "error initializing hardware.\n");
899 /* IRQ event handling initialization */
900 spin_lock_init(&dev->cmd_issue_lock);
901 dev->cmd_event = STU300_EVENT_NONE;
902 dev->cmd_err = STU300_ERROR_NONE;
904 adap = &dev->adapter;
905 adap->owner = THIS_MODULE;
906 /* DDC class but actually often used for more generic I2C */
907 adap->class = I2C_CLASS_DEPRECATED;
908 strlcpy(adap->name, "ST Microelectronics DDC I2C adapter",
911 adap->algo = &stu300_algo;
912 adap->dev.parent = &pdev->dev;
913 adap->dev.of_node = pdev->dev.of_node;
914 adap->quirks = &stu300_quirks;
916 i2c_set_adapdata(adap, dev);
918 /* i2c device drivers may be active on return from add_adapter() */
919 ret = i2c_add_numbered_adapter(adap);
923 platform_set_drvdata(pdev, dev);
924 dev_info(&pdev->dev, "ST DDC I2C @ %p, irq %d\n",
925 dev->virtbase, dev->irq);
930 #ifdef CONFIG_PM_SLEEP
931 static int stu300_suspend(struct device *device)
933 struct stu300_dev *dev = dev_get_drvdata(device);
935 /* Turn off everything */
936 stu300_wr8(0x00, dev->virtbase + I2C_CR);
940 static int stu300_resume(struct device *device)
943 struct stu300_dev *dev = dev_get_drvdata(device);
945 clk_enable(dev->clk);
946 ret = stu300_init_hw(dev);
947 clk_disable(dev->clk);
950 dev_err(device, "error re-initializing hardware.\n");
954 static SIMPLE_DEV_PM_OPS(stu300_pm, stu300_suspend, stu300_resume);
955 #define STU300_I2C_PM (&stu300_pm)
957 #define STU300_I2C_PM NULL
960 static int stu300_remove(struct platform_device *pdev)
962 struct stu300_dev *dev = platform_get_drvdata(pdev);
964 i2c_del_adapter(&dev->adapter);
965 /* Turn off everything */
966 stu300_wr8(0x00, dev->virtbase + I2C_CR);
970 static const struct of_device_id stu300_dt_match[] = {
971 { .compatible = "st,ddci2c" },
974 MODULE_DEVICE_TABLE(of, stu300_dt_match);
976 static struct platform_driver stu300_i2c_driver = {
980 .of_match_table = stu300_dt_match,
982 .probe = stu300_probe,
983 .remove = stu300_remove,
987 static int __init stu300_init(void)
989 return platform_driver_register(&stu300_i2c_driver);
992 static void __exit stu300_exit(void)
994 platform_driver_unregister(&stu300_i2c_driver);
998 * The systems using this bus often have very basic devices such
999 * as regulators on the I2C bus, so this needs to be loaded early.
1000 * Therefore it is registered in the subsys_initcall().
1002 subsys_initcall(stu300_init);
1003 module_exit(stu300_exit);
1005 MODULE_AUTHOR("Linus Walleij <linus.walleij@stericsson.com>");
1006 MODULE_DESCRIPTION("ST Micro DDC I2C adapter (" NAME ")");
1007 MODULE_LICENSE("GPL");
1008 MODULE_ALIAS("platform:" NAME);