1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
14 * This driver is based on i2c-stm32f4.c
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c-smbus.h>
22 #include <linux/interrupt.h>
24 #include <linux/iopoll.h>
25 #include <linux/mfd/syscon.h>
26 #include <linux/module.h>
28 #include <linux/of_address.h>
29 #include <linux/of_platform.h>
30 #include <linux/platform_device.h>
31 #include <linux/pinctrl/consumer.h>
32 #include <linux/pm_runtime.h>
33 #include <linux/pm_wakeirq.h>
34 #include <linux/regmap.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
38 #include "i2c-stm32.h"
40 /* STM32F7 I2C registers */
41 #define STM32F7_I2C_CR1 0x00
42 #define STM32F7_I2C_CR2 0x04
43 #define STM32F7_I2C_OAR1 0x08
44 #define STM32F7_I2C_OAR2 0x0C
45 #define STM32F7_I2C_PECR 0x20
46 #define STM32F7_I2C_TIMINGR 0x10
47 #define STM32F7_I2C_ISR 0x18
48 #define STM32F7_I2C_ICR 0x1C
49 #define STM32F7_I2C_RXDR 0x24
50 #define STM32F7_I2C_TXDR 0x28
52 /* STM32F7 I2C control 1 */
53 #define STM32F7_I2C_CR1_PECEN BIT(23)
54 #define STM32F7_I2C_CR1_SMBHEN BIT(20)
55 #define STM32F7_I2C_CR1_WUPEN BIT(18)
56 #define STM32F7_I2C_CR1_SBC BIT(16)
57 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
58 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
59 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
60 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
61 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
62 #define STM32F7_I2C_CR1_ERRIE BIT(7)
63 #define STM32F7_I2C_CR1_TCIE BIT(6)
64 #define STM32F7_I2C_CR1_STOPIE BIT(5)
65 #define STM32F7_I2C_CR1_NACKIE BIT(4)
66 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
67 #define STM32F7_I2C_CR1_RXIE BIT(2)
68 #define STM32F7_I2C_CR1_TXIE BIT(1)
69 #define STM32F7_I2C_CR1_PE BIT(0)
70 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
71 | STM32F7_I2C_CR1_TCIE \
72 | STM32F7_I2C_CR1_STOPIE \
73 | STM32F7_I2C_CR1_NACKIE \
74 | STM32F7_I2C_CR1_RXIE \
75 | STM32F7_I2C_CR1_TXIE)
76 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
77 | STM32F7_I2C_CR1_STOPIE \
78 | STM32F7_I2C_CR1_NACKIE \
79 | STM32F7_I2C_CR1_RXIE \
80 | STM32F7_I2C_CR1_TXIE)
82 /* STM32F7 I2C control 2 */
83 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
84 #define STM32F7_I2C_CR2_RELOAD BIT(24)
85 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
86 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
87 #define STM32F7_I2C_CR2_NACK BIT(15)
88 #define STM32F7_I2C_CR2_STOP BIT(14)
89 #define STM32F7_I2C_CR2_START BIT(13)
90 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
91 #define STM32F7_I2C_CR2_ADD10 BIT(11)
92 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
93 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
94 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
95 STM32F7_I2C_CR2_SADD10_MASK))
96 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
97 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
99 /* STM32F7 I2C Own Address 1 */
100 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
101 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
102 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
103 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
104 STM32F7_I2C_OAR1_OA1_10_MASK))
105 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
106 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
107 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
108 | STM32F7_I2C_OAR1_OA1_10_MASK \
109 | STM32F7_I2C_OAR1_OA1EN \
110 | STM32F7_I2C_OAR1_OA1MODE)
112 /* STM32F7 I2C Own Address 2 */
113 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
114 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
115 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
116 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
117 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
118 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
119 | STM32F7_I2C_OAR2_OA2_7_MASK \
120 | STM32F7_I2C_OAR2_OA2EN)
122 /* STM32F7 I2C Interrupt Status */
123 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
124 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
125 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
126 #define STM32F7_I2C_ISR_DIR BIT(16)
127 #define STM32F7_I2C_ISR_BUSY BIT(15)
128 #define STM32F7_I2C_ISR_PECERR BIT(11)
129 #define STM32F7_I2C_ISR_ARLO BIT(9)
130 #define STM32F7_I2C_ISR_BERR BIT(8)
131 #define STM32F7_I2C_ISR_TCR BIT(7)
132 #define STM32F7_I2C_ISR_TC BIT(6)
133 #define STM32F7_I2C_ISR_STOPF BIT(5)
134 #define STM32F7_I2C_ISR_NACKF BIT(4)
135 #define STM32F7_I2C_ISR_ADDR BIT(3)
136 #define STM32F7_I2C_ISR_RXNE BIT(2)
137 #define STM32F7_I2C_ISR_TXIS BIT(1)
138 #define STM32F7_I2C_ISR_TXE BIT(0)
140 /* STM32F7 I2C Interrupt Clear */
141 #define STM32F7_I2C_ICR_PECCF BIT(11)
142 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
143 #define STM32F7_I2C_ICR_BERRCF BIT(8)
144 #define STM32F7_I2C_ICR_STOPCF BIT(5)
145 #define STM32F7_I2C_ICR_NACKCF BIT(4)
146 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
148 /* STM32F7 I2C Timing */
149 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
150 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
151 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
152 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
153 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
155 #define STM32F7_I2C_MAX_LEN 0xff
156 #define STM32F7_I2C_DMA_LEN_MIN 0x16
158 STM32F7_SLAVE_HOSTNOTIFY,
159 STM32F7_SLAVE_7_10_BITS_ADDR,
160 STM32F7_SLAVE_7_BITS_ADDR,
161 STM32F7_I2C_MAX_SLAVE
164 #define STM32F7_I2C_DNF_DEFAULT 0
165 #define STM32F7_I2C_DNF_MAX 15
167 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
168 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
169 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
171 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
172 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
174 #define STM32F7_PRESC_MAX BIT(4)
175 #define STM32F7_SCLDEL_MAX BIT(4)
176 #define STM32F7_SDADEL_MAX BIT(4)
177 #define STM32F7_SCLH_MAX BIT(8)
178 #define STM32F7_SCLL_MAX BIT(8)
180 #define STM32F7_AUTOSUSPEND_DELAY (HZ / 100)
183 * struct stm32f7_i2c_regs - i2c f7 registers backup
184 * @cr1: Control register 1
185 * @cr2: Control register 2
186 * @oar1: Own address 1 register
187 * @oar2: Own address 2 register
188 * @tmgr: Timing register
190 struct stm32f7_i2c_regs {
199 * struct stm32f7_i2c_spec - private i2c specification timing
200 * @rate: I2C bus speed (Hz)
201 * @fall_max: Max fall time of both SDA and SCL signals (ns)
202 * @rise_max: Max rise time of both SDA and SCL signals (ns)
203 * @hddat_min: Min data hold time (ns)
204 * @vddat_max: Max data valid time (ns)
205 * @sudat_min: Min data setup time (ns)
206 * @l_min: Min low period of the SCL clock (ns)
207 * @h_min: Min high period of the SCL clock (ns)
209 struct stm32f7_i2c_spec {
221 * struct stm32f7_i2c_setup - private I2C timing setup parameters
222 * @speed_freq: I2C speed frequency (Hz)
223 * @clock_src: I2C clock source frequency (Hz)
224 * @rise_time: Rise time (ns)
225 * @fall_time: Fall time (ns)
226 * @dnf: Digital filter coefficient (0-16)
227 * @analog_filter: Analog filter delay (On/Off)
228 * @fmp_clr_offset: Fast Mode Plus clear register offset from set register
230 struct stm32f7_i2c_setup {
241 * struct stm32f7_i2c_timings - private I2C output parameters
243 * @presc: Prescaler value
244 * @scldel: Data setup time
245 * @sdadel: Data hold time
246 * @sclh: SCL high period (master mode)
247 * @scll: SCL low period (master mode)
249 struct stm32f7_i2c_timings {
250 struct list_head node;
259 * struct stm32f7_i2c_msg - client specific data
260 * @addr: 8-bit or 10-bit slave addr, including r/w bit
261 * @count: number of bytes to be transferred
263 * @result: result of the transfer
264 * @stop: last I2C msg to be sent, i.e. STOP to be generated
265 * @smbus: boolean to know if the I2C IP is used in SMBus mode
266 * @size: type of SMBus protocol
267 * @read_write: direction of SMBus protocol
268 * SMBus block read and SMBus block write - block read process call protocols
269 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
270 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
271 * This buffer has to be 32-bit aligned to be compliant with memory address
272 * register in DMA mode.
274 struct stm32f7_i2c_msg {
283 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
287 * struct stm32f7_i2c_dev - private data of the controller
288 * @adap: I2C adapter for this controller
289 * @dev: device for this controller
290 * @base: virtual memory area
291 * @complete: completion of I2C message
293 * @bus_rate: I2C clock frequency of the controller
294 * @msg: Pointer to data to be written
295 * @msg_num: number of I2C messages to be executed
296 * @msg_id: message identifiant
297 * @f7_msg: customized i2c msg for driver usage
298 * @setup: I2C timing input setup
299 * @timing: I2C computed timings
300 * @slave: list of slave devices registered on the I2C bus
301 * @slave_running: slave device currently used
302 * @backup_regs: backup of i2c controller registers (for suspend/resume)
303 * @slave_dir: transfer direction for the current slave device
304 * @master_mode: boolean to know in which mode the I2C is running (master or
307 * @use_dma: boolean to know if dma is used in the current transfer
308 * @regmap: holds SYSCFG phandle for Fast Mode Plus bits
309 * @fmp_sreg: register address for setting Fast Mode Plus bits
310 * @fmp_creg: register address for clearing Fast Mode Plus bits
311 * @fmp_mask: mask for Fast Mode Plus bits in set register
312 * @wakeup_src: boolean to know if the device is a wakeup source
313 * @smbus_mode: states that the controller is configured in SMBus mode
314 * @host_notify_client: SMBus host-notify client
316 struct stm32f7_i2c_dev {
317 struct i2c_adapter adap;
320 struct completion complete;
322 unsigned int bus_rate;
324 unsigned int msg_num;
326 struct stm32f7_i2c_msg f7_msg;
327 struct stm32f7_i2c_setup setup;
328 struct stm32f7_i2c_timings timing;
329 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
330 struct i2c_client *slave_running;
331 struct stm32f7_i2c_regs backup_regs;
334 struct stm32_i2c_dma *dma;
336 struct regmap *regmap;
342 struct i2c_client *host_notify_client;
346 * All these values are coming from I2C Specification, Version 6.0, 4th of
349 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
350 * and Fast-mode Plus I2C-bus devices
352 static struct stm32f7_i2c_spec stm32f7_i2c_specs[] = {
354 .rate = I2C_MAX_STANDARD_MODE_FREQ,
364 .rate = I2C_MAX_FAST_MODE_FREQ,
374 .rate = I2C_MAX_FAST_MODE_PLUS_FREQ,
385 static const struct stm32f7_i2c_setup stm32f7_setup = {
386 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
387 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
388 .dnf = STM32F7_I2C_DNF_DEFAULT,
389 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
392 static const struct stm32f7_i2c_setup stm32mp15_setup = {
393 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
394 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
395 .dnf = STM32F7_I2C_DNF_DEFAULT,
396 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
397 .fmp_clr_offset = 0x40,
400 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
402 writel_relaxed(readl_relaxed(reg) | mask, reg);
405 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
407 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
410 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
412 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
415 static struct stm32f7_i2c_spec *stm32f7_get_specs(u32 rate)
419 for (i = 0; i < ARRAY_SIZE(stm32f7_i2c_specs); i++)
420 if (rate <= stm32f7_i2c_specs[i].rate)
421 return &stm32f7_i2c_specs[i];
423 return ERR_PTR(-EINVAL);
426 #define RATE_MIN(rate) ((rate) * 8 / 10)
427 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
428 struct stm32f7_i2c_setup *setup,
429 struct stm32f7_i2c_timings *output)
431 struct stm32f7_i2c_spec *specs;
432 u32 p_prev = STM32F7_PRESC_MAX;
433 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
435 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
437 u32 clk_error_prev = i2cbus;
439 u32 af_delay_min, af_delay_max;
441 u32 clk_min, clk_max;
442 int sdadel_min, sdadel_max;
444 struct stm32f7_i2c_timings *v, *_v, *s;
445 struct list_head solutions;
449 specs = stm32f7_get_specs(setup->speed_freq);
450 if (specs == ERR_PTR(-EINVAL)) {
451 dev_err(i2c_dev->dev, "speed out of bound {%d}\n",
456 if ((setup->rise_time > specs->rise_max) ||
457 (setup->fall_time > specs->fall_max)) {
458 dev_err(i2c_dev->dev,
459 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
460 setup->rise_time, specs->rise_max,
461 setup->fall_time, specs->fall_max);
465 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
466 dev_err(i2c_dev->dev,
467 "DNF out of bound %d/%d\n",
468 setup->dnf, STM32F7_I2C_DNF_MAX);
472 /* Analog and Digital Filters */
474 (setup->analog_filter ?
475 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
477 (setup->analog_filter ?
478 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
479 dnf_delay = setup->dnf * i2cclk;
481 sdadel_min = specs->hddat_min + setup->fall_time -
482 af_delay_min - (setup->dnf + 3) * i2cclk;
484 sdadel_max = specs->vddat_max - setup->rise_time -
485 af_delay_max - (setup->dnf + 4) * i2cclk;
487 scldel_min = setup->rise_time + specs->sudat_min;
494 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
495 sdadel_min, sdadel_max, scldel_min);
497 INIT_LIST_HEAD(&solutions);
498 /* Compute possible values for PRESC, SCLDEL and SDADEL */
499 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
500 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
501 u32 scldel = (l + 1) * (p + 1) * i2cclk;
503 if (scldel < scldel_min)
506 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
507 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
509 if (((sdadel >= sdadel_min) &&
510 (sdadel <= sdadel_max)) &&
512 v = kmalloc(sizeof(*v), GFP_KERNEL);
523 list_add_tail(&v->node,
534 if (list_empty(&solutions)) {
535 dev_err(i2c_dev->dev, "no Prescaler solution\n");
540 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
542 clk_max = NSEC_PER_SEC / RATE_MIN(setup->speed_freq);
543 clk_min = NSEC_PER_SEC / setup->speed_freq;
546 * Among Prescaler possibilities discovered above figures out SCL Low
547 * and High Period. Provided:
548 * - SCL Low Period has to be higher than SCL Clock Low Period
549 * defined by I2C Specification. I2C Clock has to be lower than
550 * (SCL Low Period - Analog/Digital filters) / 4.
551 * - SCL High Period has to be lower than SCL Clock High Period
552 * defined by I2C Specification
553 * - I2C Clock has to be lower than SCL High Period
555 list_for_each_entry(v, &solutions, node) {
556 u32 prescaler = (v->presc + 1) * i2cclk;
558 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
559 u32 tscl_l = (l + 1) * prescaler + tsync;
561 if ((tscl_l < specs->l_min) ||
563 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
567 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
568 u32 tscl_h = (h + 1) * prescaler + tsync;
569 u32 tscl = tscl_l + tscl_h +
570 setup->rise_time + setup->fall_time;
572 if ((tscl >= clk_min) && (tscl <= clk_max) &&
573 (tscl_h >= specs->h_min) &&
575 int clk_error = tscl - i2cbus;
578 clk_error = -clk_error;
580 if (clk_error < clk_error_prev) {
581 clk_error_prev = clk_error;
592 dev_err(i2c_dev->dev, "no solution at all\n");
597 output->presc = s->presc;
598 output->scldel = s->scldel;
599 output->sdadel = s->sdadel;
600 output->scll = s->scll;
601 output->sclh = s->sclh;
603 dev_dbg(i2c_dev->dev,
604 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
606 output->scldel, output->sdadel,
607 output->scll, output->sclh);
610 /* Release list and memory */
611 list_for_each_entry_safe(v, _v, &solutions, node) {
619 static u32 stm32f7_get_lower_rate(u32 rate)
621 int i = ARRAY_SIZE(stm32f7_i2c_specs);
624 if (stm32f7_i2c_specs[i].rate < rate)
627 return stm32f7_i2c_specs[i].rate;
630 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
631 struct stm32f7_i2c_setup *setup)
633 struct i2c_timings timings, *t = &timings;
636 t->bus_freq_hz = I2C_MAX_STANDARD_MODE_FREQ;
637 t->scl_rise_ns = i2c_dev->setup.rise_time;
638 t->scl_fall_ns = i2c_dev->setup.fall_time;
640 i2c_parse_fw_timings(i2c_dev->dev, t, false);
642 if (t->bus_freq_hz > I2C_MAX_FAST_MODE_PLUS_FREQ) {
643 dev_err(i2c_dev->dev, "Invalid bus speed (%i>%i)\n",
644 t->bus_freq_hz, I2C_MAX_FAST_MODE_PLUS_FREQ);
648 setup->speed_freq = t->bus_freq_hz;
649 i2c_dev->setup.rise_time = t->scl_rise_ns;
650 i2c_dev->setup.fall_time = t->scl_fall_ns;
651 setup->clock_src = clk_get_rate(i2c_dev->clk);
653 if (!setup->clock_src) {
654 dev_err(i2c_dev->dev, "clock rate is 0\n");
659 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
662 dev_err(i2c_dev->dev,
663 "failed to compute I2C timings.\n");
664 if (setup->speed_freq <= I2C_MAX_STANDARD_MODE_FREQ)
667 stm32f7_get_lower_rate(setup->speed_freq);
668 dev_warn(i2c_dev->dev,
669 "downgrade I2C Speed Freq to (%i)\n",
675 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
679 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Clk Source(%i)\n",
680 setup->speed_freq, setup->clock_src);
681 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
682 setup->rise_time, setup->fall_time);
683 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
684 (setup->analog_filter ? "On" : "Off"), setup->dnf);
686 i2c_dev->bus_rate = setup->speed_freq;
691 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
693 void __iomem *base = i2c_dev->base;
694 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
696 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
699 static void stm32f7_i2c_dma_callback(void *arg)
701 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
702 struct stm32_i2c_dma *dma = i2c_dev->dma;
703 struct device *dev = dma->chan_using->device->dev;
705 stm32f7_i2c_disable_dma_req(i2c_dev);
706 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
707 complete(&dma->dma_complete);
710 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
712 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
715 /* Timing settings */
716 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
717 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
718 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
719 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
720 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
721 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
724 if (i2c_dev->setup.analog_filter)
725 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
726 STM32F7_I2C_CR1_ANFOFF);
728 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
729 STM32F7_I2C_CR1_ANFOFF);
731 /* Program the Digital Filter */
732 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
733 STM32F7_I2C_CR1_DNF_MASK);
734 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
735 STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
737 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
741 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
743 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
744 void __iomem *base = i2c_dev->base;
747 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
752 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
754 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
755 void __iomem *base = i2c_dev->base;
758 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
761 /* Flush RX buffer has no data is expected */
762 readb_relaxed(base + STM32F7_I2C_RXDR);
766 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
768 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
771 if (i2c_dev->use_dma)
772 f7_msg->count -= STM32F7_I2C_MAX_LEN;
774 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
776 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
777 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
778 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
780 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
781 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
784 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
787 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
789 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
794 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
795 * data received inform us how many data will follow.
797 stm32f7_i2c_read_rx_data(i2c_dev);
800 * Update NBYTES with the value read to continue the transfer
802 val = f7_msg->buf - sizeof(u8);
803 f7_msg->count = *val;
804 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
805 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
806 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
807 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
810 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
812 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
814 dev_info(i2c_dev->dev, "Trying to recover bus\n");
816 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
819 stm32f7_i2c_hw_config(i2c_dev);
824 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
829 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
831 !(status & STM32F7_I2C_ISR_BUSY),
836 dev_info(i2c_dev->dev, "bus busy\n");
838 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
840 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
847 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
850 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
851 void __iomem *base = i2c_dev->base;
855 f7_msg->addr = msg->addr;
856 f7_msg->buf = msg->buf;
857 f7_msg->count = msg->len;
859 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
861 reinit_completion(&i2c_dev->complete);
863 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
864 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
866 /* Set transfer direction */
867 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
868 if (msg->flags & I2C_M_RD)
869 cr2 |= STM32F7_I2C_CR2_RD_WRN;
871 /* Set slave address */
872 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
873 if (msg->flags & I2C_M_TEN) {
874 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
875 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
876 cr2 |= STM32F7_I2C_CR2_ADD10;
878 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
879 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
882 /* Set nb bytes to transfer and reload if needed */
883 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
884 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
885 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
886 cr2 |= STM32F7_I2C_CR2_RELOAD;
888 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
891 /* Enable NACK, STOP, error and transfer complete interrupts */
892 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
893 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
895 /* Clear DMA req and TX/RX interrupt */
896 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
897 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
899 /* Configure DMA or enable RX/TX interrupt */
900 i2c_dev->use_dma = false;
901 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
902 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
903 msg->flags & I2C_M_RD,
904 f7_msg->count, f7_msg->buf,
905 stm32f7_i2c_dma_callback,
908 i2c_dev->use_dma = true;
910 dev_warn(i2c_dev->dev, "can't use DMA\n");
913 if (!i2c_dev->use_dma) {
914 if (msg->flags & I2C_M_RD)
915 cr1 |= STM32F7_I2C_CR1_RXIE;
917 cr1 |= STM32F7_I2C_CR1_TXIE;
919 if (msg->flags & I2C_M_RD)
920 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
922 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
925 /* Configure Start/Repeated Start */
926 cr2 |= STM32F7_I2C_CR2_START;
928 i2c_dev->master_mode = true;
930 /* Write configurations registers */
931 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
932 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
935 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
936 unsigned short flags, u8 command,
937 union i2c_smbus_data *data)
939 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
940 struct device *dev = i2c_dev->dev;
941 void __iomem *base = i2c_dev->base;
946 reinit_completion(&i2c_dev->complete);
948 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
949 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
951 /* Set transfer direction */
952 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
953 if (f7_msg->read_write)
954 cr2 |= STM32F7_I2C_CR2_RD_WRN;
956 /* Set slave address */
957 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
958 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
960 f7_msg->smbus_buf[0] = command;
961 switch (f7_msg->size) {
962 case I2C_SMBUS_QUICK:
970 case I2C_SMBUS_BYTE_DATA:
971 if (f7_msg->read_write) {
972 f7_msg->stop = false;
974 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
978 f7_msg->smbus_buf[1] = data->byte;
981 case I2C_SMBUS_WORD_DATA:
982 if (f7_msg->read_write) {
983 f7_msg->stop = false;
985 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
989 f7_msg->smbus_buf[1] = data->word & 0xff;
990 f7_msg->smbus_buf[2] = data->word >> 8;
993 case I2C_SMBUS_BLOCK_DATA:
994 if (f7_msg->read_write) {
995 f7_msg->stop = false;
997 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1000 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
1002 dev_err(dev, "Invalid block write size %d\n",
1006 f7_msg->count = data->block[0] + 2;
1007 for (i = 1; i < f7_msg->count; i++)
1008 f7_msg->smbus_buf[i] = data->block[i - 1];
1011 case I2C_SMBUS_PROC_CALL:
1012 f7_msg->stop = false;
1014 f7_msg->smbus_buf[1] = data->word & 0xff;
1015 f7_msg->smbus_buf[2] = data->word >> 8;
1016 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1017 f7_msg->read_write = I2C_SMBUS_READ;
1019 case I2C_SMBUS_BLOCK_PROC_CALL:
1020 f7_msg->stop = false;
1021 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
1022 dev_err(dev, "Invalid block write size %d\n",
1026 f7_msg->count = data->block[0] + 2;
1027 for (i = 1; i < f7_msg->count; i++)
1028 f7_msg->smbus_buf[i] = data->block[i - 1];
1029 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
1030 f7_msg->read_write = I2C_SMBUS_READ;
1032 case I2C_SMBUS_I2C_BLOCK_DATA:
1033 /* Rely on emulated i2c transfer (through master_xfer) */
1036 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
1040 f7_msg->buf = f7_msg->smbus_buf;
1043 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
1044 cr1 |= STM32F7_I2C_CR1_PECEN;
1045 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1046 if (!f7_msg->read_write)
1049 cr1 &= ~STM32F7_I2C_CR1_PECEN;
1050 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
1053 /* Set number of bytes to be transferred */
1054 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
1055 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1057 /* Enable NACK, STOP, error and transfer complete interrupts */
1058 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
1059 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
1061 /* Clear DMA req and TX/RX interrupt */
1062 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1063 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1065 /* Configure DMA or enable RX/TX interrupt */
1066 i2c_dev->use_dma = false;
1067 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
1068 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1069 cr2 & STM32F7_I2C_CR2_RD_WRN,
1070 f7_msg->count, f7_msg->buf,
1071 stm32f7_i2c_dma_callback,
1074 i2c_dev->use_dma = true;
1076 dev_warn(i2c_dev->dev, "can't use DMA\n");
1079 if (!i2c_dev->use_dma) {
1080 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1081 cr1 |= STM32F7_I2C_CR1_RXIE;
1083 cr1 |= STM32F7_I2C_CR1_TXIE;
1085 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1086 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1088 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1092 cr2 |= STM32F7_I2C_CR2_START;
1094 i2c_dev->master_mode = true;
1096 /* Write configurations registers */
1097 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1098 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1103 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1105 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1106 void __iomem *base = i2c_dev->base;
1110 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1111 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1113 /* Set transfer direction */
1114 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1116 switch (f7_msg->size) {
1117 case I2C_SMBUS_BYTE_DATA:
1120 case I2C_SMBUS_WORD_DATA:
1121 case I2C_SMBUS_PROC_CALL:
1124 case I2C_SMBUS_BLOCK_DATA:
1125 case I2C_SMBUS_BLOCK_PROC_CALL:
1127 cr2 |= STM32F7_I2C_CR2_RELOAD;
1131 f7_msg->buf = f7_msg->smbus_buf;
1132 f7_msg->stop = true;
1134 /* Add one byte for PEC if needed */
1135 if (cr1 & STM32F7_I2C_CR1_PECEN)
1138 /* Set number of bytes to be transferred */
1139 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1140 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1143 * Configure RX/TX interrupt:
1145 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1146 cr1 |= STM32F7_I2C_CR1_RXIE;
1149 * Configure DMA or enable RX/TX interrupt:
1150 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1151 * dma as we don't know in advance how many data will be received
1153 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1154 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1156 i2c_dev->use_dma = false;
1157 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1158 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1159 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1160 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1161 cr2 & STM32F7_I2C_CR2_RD_WRN,
1162 f7_msg->count, f7_msg->buf,
1163 stm32f7_i2c_dma_callback,
1167 i2c_dev->use_dma = true;
1169 dev_warn(i2c_dev->dev, "can't use DMA\n");
1172 if (!i2c_dev->use_dma)
1173 cr1 |= STM32F7_I2C_CR1_RXIE;
1175 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1177 /* Configure Repeated Start */
1178 cr2 |= STM32F7_I2C_CR2_START;
1180 /* Write configurations registers */
1181 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1182 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1185 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1187 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1188 u8 count, internal_pec, received_pec;
1190 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1192 switch (f7_msg->size) {
1193 case I2C_SMBUS_BYTE:
1194 case I2C_SMBUS_BYTE_DATA:
1195 received_pec = f7_msg->smbus_buf[1];
1197 case I2C_SMBUS_WORD_DATA:
1198 case I2C_SMBUS_PROC_CALL:
1199 received_pec = f7_msg->smbus_buf[2];
1201 case I2C_SMBUS_BLOCK_DATA:
1202 case I2C_SMBUS_BLOCK_PROC_CALL:
1203 count = f7_msg->smbus_buf[0];
1204 received_pec = f7_msg->smbus_buf[count];
1207 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1211 if (internal_pec != received_pec) {
1212 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1213 internal_pec, received_pec);
1220 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1227 if (slave->flags & I2C_CLIENT_TEN) {
1229 * For 10-bit addr, addcode = 11110XY with
1230 * X = Bit 9 of slave address
1231 * Y = Bit 8 of slave address
1233 addr = slave->addr >> 8;
1235 if (addr == addcode)
1238 addr = slave->addr & 0x7f;
1239 if (addr == addcode)
1246 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1248 struct i2c_client *slave = i2c_dev->slave_running;
1249 void __iomem *base = i2c_dev->base;
1253 if (i2c_dev->slave_dir) {
1254 /* Notify i2c slave that new read transfer is starting */
1255 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1258 * Disable slave TX config in case of I2C combined message
1259 * (I2C Write followed by I2C Read)
1261 mask = STM32F7_I2C_CR2_RELOAD;
1262 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1263 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1264 STM32F7_I2C_CR1_TCIE;
1265 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1267 /* Enable TX empty, STOP, NACK interrupts */
1268 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1269 STM32F7_I2C_CR1_TXIE;
1270 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1272 /* Write 1st data byte */
1273 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1275 /* Notify i2c slave that new write transfer is starting */
1276 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1278 /* Set reload mode to be able to ACK/NACK each received byte */
1279 mask = STM32F7_I2C_CR2_RELOAD;
1280 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1283 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1284 * Set Slave Byte Control to be able to ACK/NACK each data
1287 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1288 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1289 STM32F7_I2C_CR1_TCIE;
1290 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1294 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1296 void __iomem *base = i2c_dev->base;
1297 u32 isr, addcode, dir, mask;
1300 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1301 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1302 dir = isr & STM32F7_I2C_ISR_DIR;
1304 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1305 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1306 i2c_dev->slave_running = i2c_dev->slave[i];
1307 i2c_dev->slave_dir = dir;
1309 /* Start I2C slave processing */
1310 stm32f7_i2c_slave_start(i2c_dev);
1312 /* Clear ADDR flag */
1313 mask = STM32F7_I2C_ICR_ADDRCF;
1314 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1320 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1321 struct i2c_client *slave, int *id)
1325 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1326 if (i2c_dev->slave[i] == slave) {
1332 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1337 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1338 struct i2c_client *slave, int *id)
1340 struct device *dev = i2c_dev->dev;
1344 * slave[STM32F7_SLAVE_HOSTNOTIFY] support only SMBus Host address (0x8)
1345 * slave[STM32F7_SLAVE_7_10_BITS_ADDR] supports 7-bit and 10-bit slave address
1346 * slave[STM32F7_SLAVE_7_BITS_ADDR] supports 7-bit slave address only
1348 if (i2c_dev->smbus_mode && (slave->addr == 0x08)) {
1349 if (i2c_dev->slave[STM32F7_SLAVE_HOSTNOTIFY])
1351 *id = STM32F7_SLAVE_HOSTNOTIFY;
1355 for (i = STM32F7_I2C_MAX_SLAVE - 1; i > STM32F7_SLAVE_HOSTNOTIFY; i--) {
1356 if ((i == STM32F7_SLAVE_7_BITS_ADDR) &&
1357 (slave->flags & I2C_CLIENT_TEN))
1359 if (!i2c_dev->slave[i]) {
1366 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1371 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1375 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1376 if (i2c_dev->slave[i])
1383 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1388 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1389 if (i2c_dev->slave[i])
1396 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1398 void __iomem *base = i2c_dev->base;
1399 u32 cr2, status, mask;
1403 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1405 /* Slave transmitter mode */
1406 if (status & STM32F7_I2C_ISR_TXIS) {
1407 i2c_slave_event(i2c_dev->slave_running,
1408 I2C_SLAVE_READ_PROCESSED,
1411 /* Write data byte */
1412 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1415 /* Transfer Complete Reload for Slave receiver mode */
1416 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1418 * Read data byte then set NBYTES to receive next byte or NACK
1419 * the current received byte
1421 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1422 ret = i2c_slave_event(i2c_dev->slave_running,
1423 I2C_SLAVE_WRITE_RECEIVED,
1426 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1427 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1428 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1430 mask = STM32F7_I2C_CR2_NACK;
1431 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1436 if (status & STM32F7_I2C_ISR_NACKF) {
1437 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1438 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1442 if (status & STM32F7_I2C_ISR_STOPF) {
1443 /* Disable interrupts */
1444 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1446 if (i2c_dev->slave_dir) {
1448 * Flush TX buffer in order to not used the byte in
1449 * TXDR for the next transfer
1451 mask = STM32F7_I2C_ISR_TXE;
1452 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1455 /* Clear STOP flag */
1456 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1458 /* Notify i2c slave that a STOP flag has been detected */
1459 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1461 i2c_dev->slave_running = NULL;
1464 /* Address match received */
1465 if (status & STM32F7_I2C_ISR_ADDR)
1466 stm32f7_i2c_slave_addr(i2c_dev);
1471 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1473 struct stm32f7_i2c_dev *i2c_dev = data;
1474 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1475 struct stm32_i2c_dma *dma = i2c_dev->dma;
1476 void __iomem *base = i2c_dev->base;
1478 int ret = IRQ_HANDLED;
1480 /* Check if the interrupt if for a slave device */
1481 if (!i2c_dev->master_mode) {
1482 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1486 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1489 if (status & STM32F7_I2C_ISR_TXIS)
1490 stm32f7_i2c_write_tx_data(i2c_dev);
1493 if (status & STM32F7_I2C_ISR_RXNE)
1494 stm32f7_i2c_read_rx_data(i2c_dev);
1497 if (status & STM32F7_I2C_ISR_NACKF) {
1498 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK (addr %x)\n",
1499 __func__, f7_msg->addr);
1500 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1501 if (i2c_dev->use_dma) {
1502 stm32f7_i2c_disable_dma_req(i2c_dev);
1503 dmaengine_terminate_all(dma->chan_using);
1505 f7_msg->result = -ENXIO;
1508 /* STOP detection flag */
1509 if (status & STM32F7_I2C_ISR_STOPF) {
1510 /* Disable interrupts */
1511 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1512 mask = STM32F7_I2C_XFER_IRQ_MASK;
1514 mask = STM32F7_I2C_ALL_IRQ_MASK;
1515 stm32f7_i2c_disable_irq(i2c_dev, mask);
1517 /* Clear STOP flag */
1518 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1520 if (i2c_dev->use_dma && !f7_msg->result) {
1521 ret = IRQ_WAKE_THREAD;
1523 i2c_dev->master_mode = false;
1524 complete(&i2c_dev->complete);
1528 /* Transfer complete */
1529 if (status & STM32F7_I2C_ISR_TC) {
1531 mask = STM32F7_I2C_CR2_STOP;
1532 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1533 } else if (i2c_dev->use_dma && !f7_msg->result) {
1534 ret = IRQ_WAKE_THREAD;
1535 } else if (f7_msg->smbus) {
1536 stm32f7_i2c_smbus_rep_start(i2c_dev);
1540 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1544 if (status & STM32F7_I2C_ISR_TCR) {
1546 stm32f7_i2c_smbus_reload(i2c_dev);
1548 stm32f7_i2c_reload(i2c_dev);
1554 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1556 struct stm32f7_i2c_dev *i2c_dev = data;
1557 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1558 struct stm32_i2c_dma *dma = i2c_dev->dma;
1563 * Wait for dma transfer completion before sending next message or
1564 * notity the end of xfer to the client
1566 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1568 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1569 stm32f7_i2c_disable_dma_req(i2c_dev);
1570 dmaengine_terminate_all(dma->chan_using);
1571 f7_msg->result = -ETIMEDOUT;
1574 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1576 if (status & STM32F7_I2C_ISR_TC) {
1577 if (f7_msg->smbus) {
1578 stm32f7_i2c_smbus_rep_start(i2c_dev);
1582 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1585 i2c_dev->master_mode = false;
1586 complete(&i2c_dev->complete);
1592 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1594 struct stm32f7_i2c_dev *i2c_dev = data;
1595 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1596 void __iomem *base = i2c_dev->base;
1597 struct device *dev = i2c_dev->dev;
1598 struct stm32_i2c_dma *dma = i2c_dev->dma;
1601 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1604 if (status & STM32F7_I2C_ISR_BERR) {
1605 dev_err(dev, "<%s>: Bus error\n", __func__);
1606 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1607 stm32f7_i2c_release_bus(&i2c_dev->adap);
1608 f7_msg->result = -EIO;
1611 /* Arbitration loss */
1612 if (status & STM32F7_I2C_ISR_ARLO) {
1613 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1614 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1615 f7_msg->result = -EAGAIN;
1618 if (status & STM32F7_I2C_ISR_PECERR) {
1619 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1620 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1621 f7_msg->result = -EINVAL;
1624 if (!i2c_dev->slave_running) {
1626 /* Disable interrupts */
1627 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1628 mask = STM32F7_I2C_XFER_IRQ_MASK;
1630 mask = STM32F7_I2C_ALL_IRQ_MASK;
1631 stm32f7_i2c_disable_irq(i2c_dev, mask);
1635 if (i2c_dev->use_dma) {
1636 stm32f7_i2c_disable_dma_req(i2c_dev);
1637 dmaengine_terminate_all(dma->chan_using);
1640 i2c_dev->master_mode = false;
1641 complete(&i2c_dev->complete);
1646 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1647 struct i2c_msg msgs[], int num)
1649 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1650 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1651 struct stm32_i2c_dma *dma = i2c_dev->dma;
1652 unsigned long time_left;
1655 i2c_dev->msg = msgs;
1656 i2c_dev->msg_num = num;
1657 i2c_dev->msg_id = 0;
1658 f7_msg->smbus = false;
1660 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1664 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1668 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1670 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1671 i2c_dev->adap.timeout);
1672 ret = f7_msg->result;
1675 * It is possible that some unsent data have already been
1676 * written into TXDR. To avoid sending old data in a
1677 * further transfer, flush TXDR in case of any error
1679 writel_relaxed(STM32F7_I2C_ISR_TXE,
1680 i2c_dev->base + STM32F7_I2C_ISR);
1685 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1686 i2c_dev->msg->addr);
1687 if (i2c_dev->use_dma)
1688 dmaengine_terminate_all(dma->chan_using);
1689 stm32f7_i2c_wait_free_bus(i2c_dev);
1694 pm_runtime_mark_last_busy(i2c_dev->dev);
1695 pm_runtime_put_autosuspend(i2c_dev->dev);
1697 return (ret < 0) ? ret : num;
1700 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1701 unsigned short flags, char read_write,
1702 u8 command, int size,
1703 union i2c_smbus_data *data)
1705 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1706 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1707 struct stm32_i2c_dma *dma = i2c_dev->dma;
1708 struct device *dev = i2c_dev->dev;
1709 unsigned long timeout;
1712 f7_msg->addr = addr;
1713 f7_msg->size = size;
1714 f7_msg->read_write = read_write;
1715 f7_msg->smbus = true;
1717 ret = pm_runtime_resume_and_get(dev);
1721 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1725 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1729 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1730 i2c_dev->adap.timeout);
1731 ret = f7_msg->result;
1734 * It is possible that some unsent data have already been
1735 * written into TXDR. To avoid sending old data in a
1736 * further transfer, flush TXDR in case of any error
1738 writel_relaxed(STM32F7_I2C_ISR_TXE,
1739 i2c_dev->base + STM32F7_I2C_ISR);
1744 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1745 if (i2c_dev->use_dma)
1746 dmaengine_terminate_all(dma->chan_using);
1747 stm32f7_i2c_wait_free_bus(i2c_dev);
1753 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1754 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1759 if (read_write && size != I2C_SMBUS_QUICK) {
1761 case I2C_SMBUS_BYTE:
1762 case I2C_SMBUS_BYTE_DATA:
1763 data->byte = f7_msg->smbus_buf[0];
1765 case I2C_SMBUS_WORD_DATA:
1766 case I2C_SMBUS_PROC_CALL:
1767 data->word = f7_msg->smbus_buf[0] |
1768 (f7_msg->smbus_buf[1] << 8);
1770 case I2C_SMBUS_BLOCK_DATA:
1771 case I2C_SMBUS_BLOCK_PROC_CALL:
1772 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1773 data->block[i] = f7_msg->smbus_buf[i];
1776 dev_err(dev, "Unsupported smbus transaction\n");
1782 pm_runtime_mark_last_busy(dev);
1783 pm_runtime_put_autosuspend(dev);
1787 static void stm32f7_i2c_enable_wakeup(struct stm32f7_i2c_dev *i2c_dev,
1790 void __iomem *base = i2c_dev->base;
1791 u32 mask = STM32F7_I2C_CR1_WUPEN;
1793 if (!i2c_dev->wakeup_src)
1797 device_set_wakeup_enable(i2c_dev->dev, true);
1798 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1800 device_set_wakeup_enable(i2c_dev->dev, false);
1801 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1805 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1807 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1808 void __iomem *base = i2c_dev->base;
1809 struct device *dev = i2c_dev->dev;
1810 u32 oar1, oar2, mask;
1813 if (slave->flags & I2C_CLIENT_PEC) {
1814 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1818 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1819 dev_err(dev, "Too much slave registered\n");
1823 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1827 ret = pm_runtime_resume_and_get(dev);
1831 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1832 stm32f7_i2c_enable_wakeup(i2c_dev, true);
1836 /* Slave SMBus Host */
1837 i2c_dev->slave[id] = slave;
1841 /* Configure Own Address 1 */
1842 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1843 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1844 if (slave->flags & I2C_CLIENT_TEN) {
1845 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1846 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1848 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1850 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1851 i2c_dev->slave[id] = slave;
1852 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1856 /* Configure Own Address 2 */
1857 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1858 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1859 if (slave->flags & I2C_CLIENT_TEN) {
1864 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1865 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1866 i2c_dev->slave[id] = slave;
1867 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1871 dev_err(dev, "I2C slave id not supported\n");
1877 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1879 /* Enable Address match interrupt, error interrupt and enable I2C */
1880 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1882 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1886 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
1887 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1889 pm_runtime_mark_last_busy(dev);
1890 pm_runtime_put_autosuspend(dev);
1895 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1897 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1898 void __iomem *base = i2c_dev->base;
1902 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1906 WARN_ON(!i2c_dev->slave[id]);
1908 ret = pm_runtime_resume_and_get(i2c_dev->dev);
1913 mask = STM32F7_I2C_OAR1_OA1EN;
1914 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1915 } else if (id == 2) {
1916 mask = STM32F7_I2C_OAR2_OA2EN;
1917 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1920 i2c_dev->slave[id] = NULL;
1922 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
1923 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1924 stm32f7_i2c_enable_wakeup(i2c_dev, false);
1927 pm_runtime_mark_last_busy(i2c_dev->dev);
1928 pm_runtime_put_autosuspend(i2c_dev->dev);
1933 static int stm32f7_i2c_write_fm_plus_bits(struct stm32f7_i2c_dev *i2c_dev,
1938 if (i2c_dev->bus_rate <= I2C_MAX_FAST_MODE_FREQ ||
1939 IS_ERR_OR_NULL(i2c_dev->regmap))
1943 if (i2c_dev->fmp_sreg == i2c_dev->fmp_creg)
1944 ret = regmap_update_bits(i2c_dev->regmap,
1947 enable ? i2c_dev->fmp_mask : 0);
1949 ret = regmap_write(i2c_dev->regmap,
1950 enable ? i2c_dev->fmp_sreg :
1957 static int stm32f7_i2c_setup_fm_plus_bits(struct platform_device *pdev,
1958 struct stm32f7_i2c_dev *i2c_dev)
1960 struct device_node *np = pdev->dev.of_node;
1963 i2c_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg-fmp");
1964 if (IS_ERR(i2c_dev->regmap))
1968 ret = of_property_read_u32_index(np, "st,syscfg-fmp", 1,
1969 &i2c_dev->fmp_sreg);
1973 i2c_dev->fmp_creg = i2c_dev->fmp_sreg +
1974 i2c_dev->setup.fmp_clr_offset;
1976 return of_property_read_u32_index(np, "st,syscfg-fmp", 2,
1977 &i2c_dev->fmp_mask);
1980 static int stm32f7_i2c_enable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
1982 struct i2c_adapter *adap = &i2c_dev->adap;
1983 void __iomem *base = i2c_dev->base;
1984 struct i2c_client *client;
1986 client = i2c_new_slave_host_notify_device(adap);
1988 return PTR_ERR(client);
1990 i2c_dev->host_notify_client = client;
1992 /* Enable SMBus Host address */
1993 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, STM32F7_I2C_CR1_SMBHEN);
1998 static void stm32f7_i2c_disable_smbus_host(struct stm32f7_i2c_dev *i2c_dev)
2000 void __iomem *base = i2c_dev->base;
2002 if (i2c_dev->host_notify_client) {
2003 /* Disable SMBus Host address */
2004 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1,
2005 STM32F7_I2C_CR1_SMBHEN);
2006 i2c_free_slave_host_notify_device(i2c_dev->host_notify_client);
2010 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
2012 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
2014 u32 func = I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
2015 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
2016 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
2017 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
2018 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC |
2019 I2C_FUNC_SMBUS_I2C_BLOCK;
2021 if (i2c_dev->smbus_mode)
2022 func |= I2C_FUNC_SMBUS_HOST_NOTIFY;
2027 static const struct i2c_algorithm stm32f7_i2c_algo = {
2028 .master_xfer = stm32f7_i2c_xfer,
2029 .smbus_xfer = stm32f7_i2c_smbus_xfer,
2030 .functionality = stm32f7_i2c_func,
2031 .reg_slave = stm32f7_i2c_reg_slave,
2032 .unreg_slave = stm32f7_i2c_unreg_slave,
2035 static int stm32f7_i2c_probe(struct platform_device *pdev)
2037 struct stm32f7_i2c_dev *i2c_dev;
2038 const struct stm32f7_i2c_setup *setup;
2039 struct resource *res;
2040 struct i2c_adapter *adap;
2041 struct reset_control *rst;
2042 dma_addr_t phy_addr;
2043 int irq_error, irq_event, ret;
2045 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
2049 i2c_dev->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2050 if (IS_ERR(i2c_dev->base))
2051 return PTR_ERR(i2c_dev->base);
2052 phy_addr = (dma_addr_t)res->start;
2054 irq_event = platform_get_irq(pdev, 0);
2055 if (irq_event <= 0) {
2056 if (irq_event != -EPROBE_DEFER)
2057 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
2059 return irq_event ? : -ENOENT;
2062 irq_error = platform_get_irq(pdev, 1);
2063 if (irq_error <= 0) {
2064 if (irq_error != -EPROBE_DEFER)
2065 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
2067 return irq_error ? : -ENOENT;
2070 i2c_dev->wakeup_src = of_property_read_bool(pdev->dev.of_node,
2073 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
2074 if (IS_ERR(i2c_dev->clk))
2075 return dev_err_probe(&pdev->dev, PTR_ERR(i2c_dev->clk),
2076 "Failed to get controller clock\n");
2078 ret = clk_prepare_enable(i2c_dev->clk);
2080 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
2084 rst = devm_reset_control_get(&pdev->dev, NULL);
2086 ret = dev_err_probe(&pdev->dev, PTR_ERR(rst),
2087 "Error: Missing reset ctrl\n");
2090 reset_control_assert(rst);
2092 reset_control_deassert(rst);
2094 i2c_dev->dev = &pdev->dev;
2096 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
2097 stm32f7_i2c_isr_event,
2098 stm32f7_i2c_isr_event_thread,
2100 pdev->name, i2c_dev);
2102 dev_err(&pdev->dev, "Failed to request irq event %i\n",
2107 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
2108 pdev->name, i2c_dev);
2110 dev_err(&pdev->dev, "Failed to request irq error %i\n",
2115 setup = of_device_get_match_data(&pdev->dev);
2117 dev_err(&pdev->dev, "Can't get device data\n");
2121 i2c_dev->setup = *setup;
2123 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
2127 /* Setup Fast mode plus if necessary */
2128 if (i2c_dev->bus_rate > I2C_MAX_FAST_MODE_FREQ) {
2129 ret = stm32f7_i2c_setup_fm_plus_bits(pdev, i2c_dev);
2132 ret = stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2137 adap = &i2c_dev->adap;
2138 i2c_set_adapdata(adap, i2c_dev);
2139 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
2141 adap->owner = THIS_MODULE;
2142 adap->timeout = 2 * HZ;
2144 adap->algo = &stm32f7_i2c_algo;
2145 adap->dev.parent = &pdev->dev;
2146 adap->dev.of_node = pdev->dev.of_node;
2148 init_completion(&i2c_dev->complete);
2150 /* Init DMA config if supported */
2151 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
2154 if (IS_ERR(i2c_dev->dma)) {
2155 ret = PTR_ERR(i2c_dev->dma);
2156 /* DMA support is optional, only report other errors */
2159 dev_dbg(i2c_dev->dev, "No DMA option: fallback using interrupts\n");
2160 i2c_dev->dma = NULL;
2163 if (i2c_dev->wakeup_src) {
2164 device_set_wakeup_capable(i2c_dev->dev, true);
2166 ret = dev_pm_set_wake_irq(i2c_dev->dev, irq_event);
2168 dev_err(i2c_dev->dev, "Failed to set wake up irq\n");
2169 goto clr_wakeup_capable;
2173 platform_set_drvdata(pdev, i2c_dev);
2175 pm_runtime_set_autosuspend_delay(i2c_dev->dev,
2176 STM32F7_AUTOSUSPEND_DELAY);
2177 pm_runtime_use_autosuspend(i2c_dev->dev);
2178 pm_runtime_set_active(i2c_dev->dev);
2179 pm_runtime_enable(i2c_dev->dev);
2181 pm_runtime_get_noresume(&pdev->dev);
2183 stm32f7_i2c_hw_config(i2c_dev);
2185 i2c_dev->smbus_mode = of_property_read_bool(pdev->dev.of_node, "smbus");
2187 ret = i2c_add_adapter(adap);
2191 if (i2c_dev->smbus_mode) {
2192 ret = stm32f7_i2c_enable_smbus_host(i2c_dev);
2194 dev_err(i2c_dev->dev,
2195 "failed to enable SMBus Host-Notify protocol (%d)\n",
2197 goto i2c_adapter_remove;
2201 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
2203 pm_runtime_mark_last_busy(i2c_dev->dev);
2204 pm_runtime_put_autosuspend(i2c_dev->dev);
2209 i2c_del_adapter(adap);
2212 pm_runtime_put_noidle(i2c_dev->dev);
2213 pm_runtime_disable(i2c_dev->dev);
2214 pm_runtime_set_suspended(i2c_dev->dev);
2215 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2217 if (i2c_dev->wakeup_src)
2218 dev_pm_clear_wake_irq(i2c_dev->dev);
2221 if (i2c_dev->wakeup_src)
2222 device_set_wakeup_capable(i2c_dev->dev, false);
2225 stm32_i2c_dma_free(i2c_dev->dma);
2226 i2c_dev->dma = NULL;
2230 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2233 clk_disable_unprepare(i2c_dev->clk);
2238 static int stm32f7_i2c_remove(struct platform_device *pdev)
2240 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
2242 stm32f7_i2c_disable_smbus_host(i2c_dev);
2244 i2c_del_adapter(&i2c_dev->adap);
2245 pm_runtime_get_sync(i2c_dev->dev);
2247 if (i2c_dev->wakeup_src) {
2248 dev_pm_clear_wake_irq(i2c_dev->dev);
2250 * enforce that wakeup is disabled and that the device
2251 * is marked as non wakeup capable
2253 device_init_wakeup(i2c_dev->dev, false);
2256 pm_runtime_put_noidle(i2c_dev->dev);
2257 pm_runtime_disable(i2c_dev->dev);
2258 pm_runtime_set_suspended(i2c_dev->dev);
2259 pm_runtime_dont_use_autosuspend(i2c_dev->dev);
2262 stm32_i2c_dma_free(i2c_dev->dma);
2263 i2c_dev->dma = NULL;
2266 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2268 clk_disable_unprepare(i2c_dev->clk);
2273 static int __maybe_unused stm32f7_i2c_runtime_suspend(struct device *dev)
2275 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2277 if (!stm32f7_i2c_is_slave_registered(i2c_dev))
2278 clk_disable_unprepare(i2c_dev->clk);
2283 static int __maybe_unused stm32f7_i2c_runtime_resume(struct device *dev)
2285 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2288 if (!stm32f7_i2c_is_slave_registered(i2c_dev)) {
2289 ret = clk_prepare_enable(i2c_dev->clk);
2291 dev_err(dev, "failed to prepare_enable clock\n");
2299 #ifdef CONFIG_PM_SLEEP
2300 static int stm32f7_i2c_regs_backup(struct stm32f7_i2c_dev *i2c_dev)
2303 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2305 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2309 backup_regs->cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2310 backup_regs->cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
2311 backup_regs->oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
2312 backup_regs->oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
2313 backup_regs->tmgr = readl_relaxed(i2c_dev->base + STM32F7_I2C_TIMINGR);
2314 stm32f7_i2c_write_fm_plus_bits(i2c_dev, false);
2316 pm_runtime_put_sync(i2c_dev->dev);
2321 static int stm32f7_i2c_regs_restore(struct stm32f7_i2c_dev *i2c_dev)
2325 struct stm32f7_i2c_regs *backup_regs = &i2c_dev->backup_regs;
2327 ret = pm_runtime_resume_and_get(i2c_dev->dev);
2331 cr1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR1);
2332 if (cr1 & STM32F7_I2C_CR1_PE)
2333 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
2334 STM32F7_I2C_CR1_PE);
2336 writel_relaxed(backup_regs->tmgr, i2c_dev->base + STM32F7_I2C_TIMINGR);
2337 writel_relaxed(backup_regs->cr1 & ~STM32F7_I2C_CR1_PE,
2338 i2c_dev->base + STM32F7_I2C_CR1);
2339 if (backup_regs->cr1 & STM32F7_I2C_CR1_PE)
2340 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
2341 STM32F7_I2C_CR1_PE);
2342 writel_relaxed(backup_regs->cr2, i2c_dev->base + STM32F7_I2C_CR2);
2343 writel_relaxed(backup_regs->oar1, i2c_dev->base + STM32F7_I2C_OAR1);
2344 writel_relaxed(backup_regs->oar2, i2c_dev->base + STM32F7_I2C_OAR2);
2345 stm32f7_i2c_write_fm_plus_bits(i2c_dev, true);
2347 pm_runtime_put_sync(i2c_dev->dev);
2352 static int stm32f7_i2c_suspend(struct device *dev)
2354 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2357 i2c_mark_adapter_suspended(&i2c_dev->adap);
2359 if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2360 ret = stm32f7_i2c_regs_backup(i2c_dev);
2362 i2c_mark_adapter_resumed(&i2c_dev->adap);
2366 pinctrl_pm_select_sleep_state(dev);
2367 pm_runtime_force_suspend(dev);
2373 static int stm32f7_i2c_resume(struct device *dev)
2375 struct stm32f7_i2c_dev *i2c_dev = dev_get_drvdata(dev);
2378 if (!device_may_wakeup(dev) && !dev->power.wakeup_path) {
2379 ret = pm_runtime_force_resume(dev);
2382 pinctrl_pm_select_default_state(dev);
2384 ret = stm32f7_i2c_regs_restore(i2c_dev);
2389 i2c_mark_adapter_resumed(&i2c_dev->adap);
2395 static const struct dev_pm_ops stm32f7_i2c_pm_ops = {
2396 SET_RUNTIME_PM_OPS(stm32f7_i2c_runtime_suspend,
2397 stm32f7_i2c_runtime_resume, NULL)
2398 SET_SYSTEM_SLEEP_PM_OPS(stm32f7_i2c_suspend, stm32f7_i2c_resume)
2401 static const struct of_device_id stm32f7_i2c_match[] = {
2402 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
2403 { .compatible = "st,stm32mp15-i2c", .data = &stm32mp15_setup},
2406 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
2408 static struct platform_driver stm32f7_i2c_driver = {
2410 .name = "stm32f7-i2c",
2411 .of_match_table = stm32f7_i2c_match,
2412 .pm = &stm32f7_i2c_pm_ops,
2414 .probe = stm32f7_i2c_probe,
2415 .remove = stm32f7_i2c_remove,
2418 module_platform_driver(stm32f7_i2c_driver);
2420 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
2421 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
2422 MODULE_LICENSE("GPL v2");