1 // SPDX-License-Identifier: GPL-2.0
3 * Driver for STMicroelectronics STM32F7 I2C controller
5 * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
7 * Please see below a link to the documentation:
8 * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
10 * Copyright (C) M'boumba Cedric Madianga 2017
11 * Copyright (C) STMicroelectronics 2017
12 * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
14 * This driver is based on i2c-stm32f4.c
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/err.h>
20 #include <linux/i2c.h>
21 #include <linux/interrupt.h>
23 #include <linux/iopoll.h>
24 #include <linux/module.h>
26 #include <linux/of_address.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/reset.h>
30 #include <linux/slab.h>
32 #include "i2c-stm32.h"
34 /* STM32F7 I2C registers */
35 #define STM32F7_I2C_CR1 0x00
36 #define STM32F7_I2C_CR2 0x04
37 #define STM32F7_I2C_OAR1 0x08
38 #define STM32F7_I2C_OAR2 0x0C
39 #define STM32F7_I2C_PECR 0x20
40 #define STM32F7_I2C_TIMINGR 0x10
41 #define STM32F7_I2C_ISR 0x18
42 #define STM32F7_I2C_ICR 0x1C
43 #define STM32F7_I2C_RXDR 0x24
44 #define STM32F7_I2C_TXDR 0x28
46 /* STM32F7 I2C control 1 */
47 #define STM32F7_I2C_CR1_PECEN BIT(23)
48 #define STM32F7_I2C_CR1_SBC BIT(16)
49 #define STM32F7_I2C_CR1_RXDMAEN BIT(15)
50 #define STM32F7_I2C_CR1_TXDMAEN BIT(14)
51 #define STM32F7_I2C_CR1_ANFOFF BIT(12)
52 #define STM32F7_I2C_CR1_DNF_MASK GENMASK(11, 8)
53 #define STM32F7_I2C_CR1_DNF(n) (((n) & 0xf) << 8)
54 #define STM32F7_I2C_CR1_ERRIE BIT(7)
55 #define STM32F7_I2C_CR1_TCIE BIT(6)
56 #define STM32F7_I2C_CR1_STOPIE BIT(5)
57 #define STM32F7_I2C_CR1_NACKIE BIT(4)
58 #define STM32F7_I2C_CR1_ADDRIE BIT(3)
59 #define STM32F7_I2C_CR1_RXIE BIT(2)
60 #define STM32F7_I2C_CR1_TXIE BIT(1)
61 #define STM32F7_I2C_CR1_PE BIT(0)
62 #define STM32F7_I2C_ALL_IRQ_MASK (STM32F7_I2C_CR1_ERRIE \
63 | STM32F7_I2C_CR1_TCIE \
64 | STM32F7_I2C_CR1_STOPIE \
65 | STM32F7_I2C_CR1_NACKIE \
66 | STM32F7_I2C_CR1_RXIE \
67 | STM32F7_I2C_CR1_TXIE)
68 #define STM32F7_I2C_XFER_IRQ_MASK (STM32F7_I2C_CR1_TCIE \
69 | STM32F7_I2C_CR1_STOPIE \
70 | STM32F7_I2C_CR1_NACKIE \
71 | STM32F7_I2C_CR1_RXIE \
72 | STM32F7_I2C_CR1_TXIE)
74 /* STM32F7 I2C control 2 */
75 #define STM32F7_I2C_CR2_PECBYTE BIT(26)
76 #define STM32F7_I2C_CR2_RELOAD BIT(24)
77 #define STM32F7_I2C_CR2_NBYTES_MASK GENMASK(23, 16)
78 #define STM32F7_I2C_CR2_NBYTES(n) (((n) & 0xff) << 16)
79 #define STM32F7_I2C_CR2_NACK BIT(15)
80 #define STM32F7_I2C_CR2_STOP BIT(14)
81 #define STM32F7_I2C_CR2_START BIT(13)
82 #define STM32F7_I2C_CR2_HEAD10R BIT(12)
83 #define STM32F7_I2C_CR2_ADD10 BIT(11)
84 #define STM32F7_I2C_CR2_RD_WRN BIT(10)
85 #define STM32F7_I2C_CR2_SADD10_MASK GENMASK(9, 0)
86 #define STM32F7_I2C_CR2_SADD10(n) (((n) & \
87 STM32F7_I2C_CR2_SADD10_MASK))
88 #define STM32F7_I2C_CR2_SADD7_MASK GENMASK(7, 1)
89 #define STM32F7_I2C_CR2_SADD7(n) (((n) & 0x7f) << 1)
91 /* STM32F7 I2C Own Address 1 */
92 #define STM32F7_I2C_OAR1_OA1EN BIT(15)
93 #define STM32F7_I2C_OAR1_OA1MODE BIT(10)
94 #define STM32F7_I2C_OAR1_OA1_10_MASK GENMASK(9, 0)
95 #define STM32F7_I2C_OAR1_OA1_10(n) (((n) & \
96 STM32F7_I2C_OAR1_OA1_10_MASK))
97 #define STM32F7_I2C_OAR1_OA1_7_MASK GENMASK(7, 1)
98 #define STM32F7_I2C_OAR1_OA1_7(n) (((n) & 0x7f) << 1)
99 #define STM32F7_I2C_OAR1_MASK (STM32F7_I2C_OAR1_OA1_7_MASK \
100 | STM32F7_I2C_OAR1_OA1_10_MASK \
101 | STM32F7_I2C_OAR1_OA1EN \
102 | STM32F7_I2C_OAR1_OA1MODE)
104 /* STM32F7 I2C Own Address 2 */
105 #define STM32F7_I2C_OAR2_OA2EN BIT(15)
106 #define STM32F7_I2C_OAR2_OA2MSK_MASK GENMASK(10, 8)
107 #define STM32F7_I2C_OAR2_OA2MSK(n) (((n) & 0x7) << 8)
108 #define STM32F7_I2C_OAR2_OA2_7_MASK GENMASK(7, 1)
109 #define STM32F7_I2C_OAR2_OA2_7(n) (((n) & 0x7f) << 1)
110 #define STM32F7_I2C_OAR2_MASK (STM32F7_I2C_OAR2_OA2MSK_MASK \
111 | STM32F7_I2C_OAR2_OA2_7_MASK \
112 | STM32F7_I2C_OAR2_OA2EN)
114 /* STM32F7 I2C Interrupt Status */
115 #define STM32F7_I2C_ISR_ADDCODE_MASK GENMASK(23, 17)
116 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
117 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
118 #define STM32F7_I2C_ISR_DIR BIT(16)
119 #define STM32F7_I2C_ISR_BUSY BIT(15)
120 #define STM32F7_I2C_ISR_PECERR BIT(11)
121 #define STM32F7_I2C_ISR_ARLO BIT(9)
122 #define STM32F7_I2C_ISR_BERR BIT(8)
123 #define STM32F7_I2C_ISR_TCR BIT(7)
124 #define STM32F7_I2C_ISR_TC BIT(6)
125 #define STM32F7_I2C_ISR_STOPF BIT(5)
126 #define STM32F7_I2C_ISR_NACKF BIT(4)
127 #define STM32F7_I2C_ISR_ADDR BIT(3)
128 #define STM32F7_I2C_ISR_RXNE BIT(2)
129 #define STM32F7_I2C_ISR_TXIS BIT(1)
130 #define STM32F7_I2C_ISR_TXE BIT(0)
132 /* STM32F7 I2C Interrupt Clear */
133 #define STM32F7_I2C_ICR_PECCF BIT(11)
134 #define STM32F7_I2C_ICR_ARLOCF BIT(9)
135 #define STM32F7_I2C_ICR_BERRCF BIT(8)
136 #define STM32F7_I2C_ICR_STOPCF BIT(5)
137 #define STM32F7_I2C_ICR_NACKCF BIT(4)
138 #define STM32F7_I2C_ICR_ADDRCF BIT(3)
140 /* STM32F7 I2C Timing */
141 #define STM32F7_I2C_TIMINGR_PRESC(n) (((n) & 0xf) << 28)
142 #define STM32F7_I2C_TIMINGR_SCLDEL(n) (((n) & 0xf) << 20)
143 #define STM32F7_I2C_TIMINGR_SDADEL(n) (((n) & 0xf) << 16)
144 #define STM32F7_I2C_TIMINGR_SCLH(n) (((n) & 0xff) << 8)
145 #define STM32F7_I2C_TIMINGR_SCLL(n) ((n) & 0xff)
147 #define STM32F7_I2C_MAX_LEN 0xff
148 #define STM32F7_I2C_DMA_LEN_MIN 0x16
149 #define STM32F7_I2C_MAX_SLAVE 0x2
151 #define STM32F7_I2C_DNF_DEFAULT 0
152 #define STM32F7_I2C_DNF_MAX 15
154 #define STM32F7_I2C_ANALOG_FILTER_ENABLE 1
155 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */
156 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */
158 #define STM32F7_I2C_RISE_TIME_DEFAULT 25 /* ns */
159 #define STM32F7_I2C_FALL_TIME_DEFAULT 10 /* ns */
161 #define STM32F7_PRESC_MAX BIT(4)
162 #define STM32F7_SCLDEL_MAX BIT(4)
163 #define STM32F7_SDADEL_MAX BIT(4)
164 #define STM32F7_SCLH_MAX BIT(8)
165 #define STM32F7_SCLL_MAX BIT(8)
168 * struct stm32f7_i2c_spec - private i2c specification timing
169 * @rate: I2C bus speed (Hz)
170 * @rate_min: 80% of I2C bus speed (Hz)
171 * @rate_max: 100% of I2C bus speed (Hz)
172 * @fall_max: Max fall time of both SDA and SCL signals (ns)
173 * @rise_max: Max rise time of both SDA and SCL signals (ns)
174 * @hddat_min: Min data hold time (ns)
175 * @vddat_max: Max data valid time (ns)
176 * @sudat_min: Min data setup time (ns)
177 * @l_min: Min low period of the SCL clock (ns)
178 * @h_min: Min high period of the SCL clock (ns)
180 struct stm32f7_i2c_spec {
194 * struct stm32f7_i2c_setup - private I2C timing setup parameters
195 * @speed: I2C speed mode (standard, Fast Plus)
196 * @speed_freq: I2C speed frequency (Hz)
197 * @clock_src: I2C clock source frequency (Hz)
198 * @rise_time: Rise time (ns)
199 * @fall_time: Fall time (ns)
200 * @dnf: Digital filter coefficient (0-16)
201 * @analog_filter: Analog filter delay (On/Off)
203 struct stm32f7_i2c_setup {
204 enum stm32_i2c_speed speed;
214 * struct stm32f7_i2c_timings - private I2C output parameters
216 * @presc: Prescaler value
217 * @scldel: Data setup time
218 * @sdadel: Data hold time
219 * @sclh: SCL high period (master mode)
220 * @scll: SCL low period (master mode)
222 struct stm32f7_i2c_timings {
223 struct list_head node;
232 * struct stm32f7_i2c_msg - client specific data
233 * @addr: 8-bit or 10-bit slave addr, including r/w bit
234 * @count: number of bytes to be transferred
236 * @result: result of the transfer
237 * @stop: last I2C msg to be sent, i.e. STOP to be generated
238 * @smbus: boolean to know if the I2C IP is used in SMBus mode
239 * @size: type of SMBus protocol
240 * @read_write: direction of SMBus protocol
241 * SMBus block read and SMBus block write - block read process call protocols
242 * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
243 * contain a maximum of 32 bytes of data + byte command + byte count + PEC
244 * This buffer has to be 32-bit aligned to be compliant with memory address
245 * register in DMA mode.
247 struct stm32f7_i2c_msg {
256 u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
260 * struct stm32f7_i2c_dev - private data of the controller
261 * @adap: I2C adapter for this controller
262 * @dev: device for this controller
263 * @base: virtual memory area
264 * @complete: completion of I2C message
266 * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
267 * @msg: Pointer to data to be written
268 * @msg_num: number of I2C messages to be executed
269 * @msg_id: message identifiant
270 * @f7_msg: customized i2c msg for driver usage
271 * @setup: I2C timing input setup
272 * @timing: I2C computed timings
273 * @slave: list of slave devices registered on the I2C bus
274 * @slave_running: slave device currently used
275 * @slave_dir: transfer direction for the current slave device
276 * @master_mode: boolean to know in which mode the I2C is running (master or
279 * @use_dma: boolean to know if dma is used in the current transfer
281 struct stm32f7_i2c_dev {
282 struct i2c_adapter adap;
285 struct completion complete;
289 unsigned int msg_num;
291 struct stm32f7_i2c_msg f7_msg;
292 struct stm32f7_i2c_setup setup;
293 struct stm32f7_i2c_timings timing;
294 struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
295 struct i2c_client *slave_running;
298 struct stm32_i2c_dma *dma;
303 * All these values are coming from I2C Specification, Version 6.0, 4th of
306 * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
307 * and Fast-mode Plus I2C-bus devices
309 static struct stm32f7_i2c_spec i2c_specs[] = {
310 [STM32_I2C_SPEED_STANDARD] = {
322 [STM32_I2C_SPEED_FAST] = {
334 [STM32_I2C_SPEED_FAST_PLUS] = {
348 static const struct stm32f7_i2c_setup stm32f7_setup = {
349 .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
350 .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
351 .dnf = STM32F7_I2C_DNF_DEFAULT,
352 .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
355 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
357 writel_relaxed(readl_relaxed(reg) | mask, reg);
360 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
362 writel_relaxed(readl_relaxed(reg) & ~mask, reg);
365 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
367 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
370 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
371 struct stm32f7_i2c_setup *setup,
372 struct stm32f7_i2c_timings *output)
374 u32 p_prev = STM32F7_PRESC_MAX;
375 u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
377 u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
379 u32 clk_error_prev = i2cbus;
381 u32 af_delay_min, af_delay_max;
383 u32 clk_min, clk_max;
384 int sdadel_min, sdadel_max;
386 struct stm32f7_i2c_timings *v, *_v, *s;
387 struct list_head solutions;
391 if (setup->speed >= STM32_I2C_SPEED_END) {
392 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
393 setup->speed, STM32_I2C_SPEED_END - 1);
397 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
398 (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
399 dev_err(i2c_dev->dev,
400 "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
401 setup->rise_time, i2c_specs[setup->speed].rise_max,
402 setup->fall_time, i2c_specs[setup->speed].fall_max);
406 if (setup->dnf > STM32F7_I2C_DNF_MAX) {
407 dev_err(i2c_dev->dev,
408 "DNF out of bound %d/%d\n",
409 setup->dnf, STM32F7_I2C_DNF_MAX);
413 if (setup->speed_freq > i2c_specs[setup->speed].rate) {
414 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
415 setup->speed_freq, i2c_specs[setup->speed].rate);
419 /* Analog and Digital Filters */
421 (setup->analog_filter ?
422 STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
424 (setup->analog_filter ?
425 STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
426 dnf_delay = setup->dnf * i2cclk;
428 sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
429 af_delay_min - (setup->dnf + 3) * i2cclk;
431 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
432 af_delay_max - (setup->dnf + 4) * i2cclk;
434 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
441 dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
442 sdadel_min, sdadel_max, scldel_min);
444 INIT_LIST_HEAD(&solutions);
445 /* Compute possible values for PRESC, SCLDEL and SDADEL */
446 for (p = 0; p < STM32F7_PRESC_MAX; p++) {
447 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
448 u32 scldel = (l + 1) * (p + 1) * i2cclk;
450 if (scldel < scldel_min)
453 for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
454 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
456 if (((sdadel >= sdadel_min) &&
457 (sdadel <= sdadel_max)) &&
459 v = kmalloc(sizeof(*v), GFP_KERNEL);
470 list_add_tail(&v->node,
477 if (list_empty(&solutions)) {
478 dev_err(i2c_dev->dev, "no Prescaler solution\n");
483 tsync = af_delay_min + dnf_delay + (2 * i2cclk);
485 clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
486 clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
489 * Among Prescaler possibilities discovered above figures out SCL Low
490 * and High Period. Provided:
491 * - SCL Low Period has to be higher than SCL Clock Low Period
492 * defined by I2C Specification. I2C Clock has to be lower than
493 * (SCL Low Period - Analog/Digital filters) / 4.
494 * - SCL High Period has to be lower than SCL Clock High Period
495 * defined by I2C Specification
496 * - I2C Clock has to be lower than SCL High Period
498 list_for_each_entry(v, &solutions, node) {
499 u32 prescaler = (v->presc + 1) * i2cclk;
501 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
502 u32 tscl_l = (l + 1) * prescaler + tsync;
504 if ((tscl_l < i2c_specs[setup->speed].l_min) ||
506 ((tscl_l - af_delay_min - dnf_delay) / 4))) {
510 for (h = 0; h < STM32F7_SCLH_MAX; h++) {
511 u32 tscl_h = (h + 1) * prescaler + tsync;
512 u32 tscl = tscl_l + tscl_h +
513 setup->rise_time + setup->fall_time;
515 if ((tscl >= clk_min) && (tscl <= clk_max) &&
516 (tscl_h >= i2c_specs[setup->speed].h_min) &&
518 int clk_error = tscl - i2cbus;
521 clk_error = -clk_error;
523 if (clk_error < clk_error_prev) {
524 clk_error_prev = clk_error;
535 dev_err(i2c_dev->dev, "no solution at all\n");
540 output->presc = s->presc;
541 output->scldel = s->scldel;
542 output->sdadel = s->sdadel;
543 output->scll = s->scll;
544 output->sclh = s->sclh;
546 dev_dbg(i2c_dev->dev,
547 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
549 output->scldel, output->sdadel,
550 output->scll, output->sclh);
553 /* Release list and memory */
554 list_for_each_entry_safe(v, _v, &solutions, node) {
562 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
563 struct stm32f7_i2c_setup *setup)
567 setup->speed = i2c_dev->speed;
568 setup->speed_freq = i2c_specs[setup->speed].rate;
569 setup->clock_src = clk_get_rate(i2c_dev->clk);
571 if (!setup->clock_src) {
572 dev_err(i2c_dev->dev, "clock rate is 0\n");
577 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
580 dev_err(i2c_dev->dev,
581 "failed to compute I2C timings.\n");
582 if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
584 setup->speed = i2c_dev->speed;
586 i2c_specs[setup->speed].rate;
587 dev_warn(i2c_dev->dev,
588 "downgrade I2C Speed Freq to (%i)\n",
589 i2c_specs[setup->speed].rate);
597 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
601 dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
602 setup->speed, setup->speed_freq, setup->clock_src);
603 dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
604 setup->rise_time, setup->fall_time);
605 dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
606 (setup->analog_filter ? "On" : "Off"), setup->dnf);
611 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
613 void __iomem *base = i2c_dev->base;
614 u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
616 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
619 static void stm32f7_i2c_dma_callback(void *arg)
621 struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
622 struct stm32_i2c_dma *dma = i2c_dev->dma;
623 struct device *dev = dma->chan_using->device->dev;
625 stm32f7_i2c_disable_dma_req(i2c_dev);
626 dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
627 complete(&dma->dma_complete);
630 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
632 struct stm32f7_i2c_timings *t = &i2c_dev->timing;
635 /* Timing settings */
636 timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
637 timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
638 timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
639 timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
640 timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
641 writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
644 if (i2c_dev->setup.analog_filter)
645 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
646 STM32F7_I2C_CR1_ANFOFF);
648 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
649 STM32F7_I2C_CR1_ANFOFF);
651 /* Program the Digital Filter */
652 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
653 STM32F7_I2C_CR1_DNF_MASK);
654 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
655 STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
657 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
661 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
663 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
664 void __iomem *base = i2c_dev->base;
667 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
672 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
674 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
675 void __iomem *base = i2c_dev->base;
678 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
681 /* Flush RX buffer has no data is expected */
682 readb_relaxed(base + STM32F7_I2C_RXDR);
686 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
688 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
691 if (i2c_dev->use_dma)
692 f7_msg->count -= STM32F7_I2C_MAX_LEN;
694 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
696 cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
697 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
698 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
700 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
701 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
704 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
707 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
709 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
714 * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
715 * data received inform us how many data will follow.
717 stm32f7_i2c_read_rx_data(i2c_dev);
720 * Update NBYTES with the value read to continue the transfer
722 val = f7_msg->buf - sizeof(u8);
723 f7_msg->count = *val;
724 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
725 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
726 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
727 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
730 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
732 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
734 dev_info(i2c_dev->dev, "Trying to recover bus\n");
736 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
739 stm32f7_i2c_hw_config(i2c_dev);
744 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
749 ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
751 !(status & STM32F7_I2C_ISR_BUSY),
756 dev_info(i2c_dev->dev, "bus busy\n");
758 ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
760 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
767 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
770 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
771 void __iomem *base = i2c_dev->base;
775 f7_msg->addr = msg->addr;
776 f7_msg->buf = msg->buf;
777 f7_msg->count = msg->len;
779 f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
781 reinit_completion(&i2c_dev->complete);
783 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
784 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
786 /* Set transfer direction */
787 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
788 if (msg->flags & I2C_M_RD)
789 cr2 |= STM32F7_I2C_CR2_RD_WRN;
791 /* Set slave address */
792 cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
793 if (msg->flags & I2C_M_TEN) {
794 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
795 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
796 cr2 |= STM32F7_I2C_CR2_ADD10;
798 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
799 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
802 /* Set nb bytes to transfer and reload if needed */
803 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
804 if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
805 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
806 cr2 |= STM32F7_I2C_CR2_RELOAD;
808 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
811 /* Enable NACK, STOP, error and transfer complete interrupts */
812 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
813 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
815 /* Clear DMA req and TX/RX interrupt */
816 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
817 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
819 /* Configure DMA or enable RX/TX interrupt */
820 i2c_dev->use_dma = false;
821 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
822 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
823 msg->flags & I2C_M_RD,
824 f7_msg->count, f7_msg->buf,
825 stm32f7_i2c_dma_callback,
828 i2c_dev->use_dma = true;
830 dev_warn(i2c_dev->dev, "can't use DMA\n");
833 if (!i2c_dev->use_dma) {
834 if (msg->flags & I2C_M_RD)
835 cr1 |= STM32F7_I2C_CR1_RXIE;
837 cr1 |= STM32F7_I2C_CR1_TXIE;
839 if (msg->flags & I2C_M_RD)
840 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
842 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
845 /* Configure Start/Repeated Start */
846 cr2 |= STM32F7_I2C_CR2_START;
848 i2c_dev->master_mode = true;
850 /* Write configurations registers */
851 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
852 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
855 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
856 unsigned short flags, u8 command,
857 union i2c_smbus_data *data)
859 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
860 struct device *dev = i2c_dev->dev;
861 void __iomem *base = i2c_dev->base;
866 reinit_completion(&i2c_dev->complete);
868 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
869 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
871 /* Set transfer direction */
872 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
873 if (f7_msg->read_write)
874 cr2 |= STM32F7_I2C_CR2_RD_WRN;
876 /* Set slave address */
877 cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
878 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
880 f7_msg->smbus_buf[0] = command;
881 switch (f7_msg->size) {
882 case I2C_SMBUS_QUICK:
890 case I2C_SMBUS_BYTE_DATA:
891 if (f7_msg->read_write) {
892 f7_msg->stop = false;
894 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
898 f7_msg->smbus_buf[1] = data->byte;
901 case I2C_SMBUS_WORD_DATA:
902 if (f7_msg->read_write) {
903 f7_msg->stop = false;
905 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
909 f7_msg->smbus_buf[1] = data->word & 0xff;
910 f7_msg->smbus_buf[2] = data->word >> 8;
913 case I2C_SMBUS_BLOCK_DATA:
914 if (f7_msg->read_write) {
915 f7_msg->stop = false;
917 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
920 if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
922 dev_err(dev, "Invalid block write size %d\n",
926 f7_msg->count = data->block[0] + 2;
927 for (i = 1; i < f7_msg->count; i++)
928 f7_msg->smbus_buf[i] = data->block[i - 1];
931 case I2C_SMBUS_PROC_CALL:
932 f7_msg->stop = false;
934 f7_msg->smbus_buf[1] = data->word & 0xff;
935 f7_msg->smbus_buf[2] = data->word >> 8;
936 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
937 f7_msg->read_write = I2C_SMBUS_READ;
939 case I2C_SMBUS_BLOCK_PROC_CALL:
940 f7_msg->stop = false;
941 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
942 dev_err(dev, "Invalid block write size %d\n",
946 f7_msg->count = data->block[0] + 2;
947 for (i = 1; i < f7_msg->count; i++)
948 f7_msg->smbus_buf[i] = data->block[i - 1];
949 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
950 f7_msg->read_write = I2C_SMBUS_READ;
953 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
957 f7_msg->buf = f7_msg->smbus_buf;
960 if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
961 cr1 |= STM32F7_I2C_CR1_PECEN;
962 cr2 |= STM32F7_I2C_CR2_PECBYTE;
963 if (!f7_msg->read_write)
966 cr1 &= ~STM32F7_I2C_CR1_PECEN;
967 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
970 /* Set number of bytes to be transferred */
971 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
972 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
974 /* Enable NACK, STOP, error and transfer complete interrupts */
975 cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
976 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
978 /* Clear DMA req and TX/RX interrupt */
979 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
980 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
982 /* Configure DMA or enable RX/TX interrupt */
983 i2c_dev->use_dma = false;
984 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
985 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
986 cr2 & STM32F7_I2C_CR2_RD_WRN,
987 f7_msg->count, f7_msg->buf,
988 stm32f7_i2c_dma_callback,
991 i2c_dev->use_dma = true;
993 dev_warn(i2c_dev->dev, "can't use DMA\n");
996 if (!i2c_dev->use_dma) {
997 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
998 cr1 |= STM32F7_I2C_CR1_RXIE;
1000 cr1 |= STM32F7_I2C_CR1_TXIE;
1002 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1003 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1005 cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1009 cr2 |= STM32F7_I2C_CR2_START;
1011 i2c_dev->master_mode = true;
1013 /* Write configurations registers */
1014 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1015 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1020 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1022 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1023 void __iomem *base = i2c_dev->base;
1027 cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1028 cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1030 /* Set transfer direction */
1031 cr2 |= STM32F7_I2C_CR2_RD_WRN;
1033 switch (f7_msg->size) {
1034 case I2C_SMBUS_BYTE_DATA:
1037 case I2C_SMBUS_WORD_DATA:
1038 case I2C_SMBUS_PROC_CALL:
1041 case I2C_SMBUS_BLOCK_DATA:
1042 case I2C_SMBUS_BLOCK_PROC_CALL:
1044 cr2 |= STM32F7_I2C_CR2_RELOAD;
1048 f7_msg->buf = f7_msg->smbus_buf;
1049 f7_msg->stop = true;
1051 /* Add one byte for PEC if needed */
1052 if (cr1 & STM32F7_I2C_CR1_PECEN)
1055 /* Set number of bytes to be transferred */
1056 cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1057 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1060 * Configure RX/TX interrupt:
1062 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1063 cr1 |= STM32F7_I2C_CR1_RXIE;
1066 * Configure DMA or enable RX/TX interrupt:
1067 * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1068 * dma as we don't know in advance how many data will be received
1070 cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1071 STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1073 i2c_dev->use_dma = false;
1074 if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1075 f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1076 f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1077 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1078 cr2 & STM32F7_I2C_CR2_RD_WRN,
1079 f7_msg->count, f7_msg->buf,
1080 stm32f7_i2c_dma_callback,
1084 i2c_dev->use_dma = true;
1086 dev_warn(i2c_dev->dev, "can't use DMA\n");
1089 if (!i2c_dev->use_dma)
1090 cr1 |= STM32F7_I2C_CR1_RXIE;
1092 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1094 /* Configure Repeated Start */
1095 cr2 |= STM32F7_I2C_CR2_START;
1097 /* Write configurations registers */
1098 writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1099 writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1102 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1104 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1105 u8 count, internal_pec, received_pec;
1107 internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1109 switch (f7_msg->size) {
1110 case I2C_SMBUS_BYTE:
1111 case I2C_SMBUS_BYTE_DATA:
1112 received_pec = f7_msg->smbus_buf[1];
1114 case I2C_SMBUS_WORD_DATA:
1115 case I2C_SMBUS_PROC_CALL:
1116 received_pec = f7_msg->smbus_buf[2];
1118 case I2C_SMBUS_BLOCK_DATA:
1119 case I2C_SMBUS_BLOCK_PROC_CALL:
1120 count = f7_msg->smbus_buf[0];
1121 received_pec = f7_msg->smbus_buf[count];
1124 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1128 if (internal_pec != received_pec) {
1129 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1130 internal_pec, received_pec);
1137 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1144 if (slave->flags & I2C_CLIENT_TEN) {
1146 * For 10-bit addr, addcode = 11110XY with
1147 * X = Bit 9 of slave address
1148 * Y = Bit 8 of slave address
1150 addr = slave->addr >> 8;
1152 if (addr == addcode)
1155 addr = slave->addr & 0x7f;
1156 if (addr == addcode)
1163 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1165 struct i2c_client *slave = i2c_dev->slave_running;
1166 void __iomem *base = i2c_dev->base;
1170 if (i2c_dev->slave_dir) {
1171 /* Notify i2c slave that new read transfer is starting */
1172 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1175 * Disable slave TX config in case of I2C combined message
1176 * (I2C Write followed by I2C Read)
1178 mask = STM32F7_I2C_CR2_RELOAD;
1179 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1180 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1181 STM32F7_I2C_CR1_TCIE;
1182 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1184 /* Enable TX empty, STOP, NACK interrupts */
1185 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1186 STM32F7_I2C_CR1_TXIE;
1187 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1189 /* Write 1st data byte */
1190 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1192 /* Notify i2c slave that new write transfer is starting */
1193 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1195 /* Set reload mode to be able to ACK/NACK each received byte */
1196 mask = STM32F7_I2C_CR2_RELOAD;
1197 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1200 * Set STOP, NACK, RX empty and transfer complete interrupts.*
1201 * Set Slave Byte Control to be able to ACK/NACK each data
1204 mask = STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1205 STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1206 STM32F7_I2C_CR1_TCIE;
1207 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1211 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1213 void __iomem *base = i2c_dev->base;
1214 u32 isr, addcode, dir, mask;
1217 isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1218 addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1219 dir = isr & STM32F7_I2C_ISR_DIR;
1221 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1222 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1223 i2c_dev->slave_running = i2c_dev->slave[i];
1224 i2c_dev->slave_dir = dir;
1226 /* Start I2C slave processing */
1227 stm32f7_i2c_slave_start(i2c_dev);
1229 /* Clear ADDR flag */
1230 mask = STM32F7_I2C_ICR_ADDRCF;
1231 writel_relaxed(mask, base + STM32F7_I2C_ICR);
1237 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1238 struct i2c_client *slave, int *id)
1242 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1243 if (i2c_dev->slave[i] == slave) {
1249 dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1254 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1255 struct i2c_client *slave, int *id)
1257 struct device *dev = i2c_dev->dev;
1261 * slave[0] supports 7-bit and 10-bit slave address
1262 * slave[1] supports 7-bit slave address only
1264 for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
1265 if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
1267 if (!i2c_dev->slave[i]) {
1273 dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1278 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1282 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1283 if (i2c_dev->slave[i])
1290 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1295 for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1296 if (i2c_dev->slave[i])
1303 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1305 void __iomem *base = i2c_dev->base;
1306 u32 cr2, status, mask;
1310 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1312 /* Slave transmitter mode */
1313 if (status & STM32F7_I2C_ISR_TXIS) {
1314 i2c_slave_event(i2c_dev->slave_running,
1315 I2C_SLAVE_READ_PROCESSED,
1318 /* Write data byte */
1319 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1322 /* Transfer Complete Reload for Slave receiver mode */
1323 if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1325 * Read data byte then set NBYTES to receive next byte or NACK
1326 * the current received byte
1328 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1329 ret = i2c_slave_event(i2c_dev->slave_running,
1330 I2C_SLAVE_WRITE_RECEIVED,
1333 cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1334 cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1335 writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1337 mask = STM32F7_I2C_CR2_NACK;
1338 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1343 if (status & STM32F7_I2C_ISR_NACKF) {
1344 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1345 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1349 if (status & STM32F7_I2C_ISR_STOPF) {
1350 /* Disable interrupts */
1351 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1353 if (i2c_dev->slave_dir) {
1355 * Flush TX buffer in order to not used the byte in
1356 * TXDR for the next transfer
1358 mask = STM32F7_I2C_ISR_TXE;
1359 stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1362 /* Clear STOP flag */
1363 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1365 /* Notify i2c slave that a STOP flag has been detected */
1366 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1368 i2c_dev->slave_running = NULL;
1371 /* Address match received */
1372 if (status & STM32F7_I2C_ISR_ADDR)
1373 stm32f7_i2c_slave_addr(i2c_dev);
1378 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1380 struct stm32f7_i2c_dev *i2c_dev = data;
1381 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1382 struct stm32_i2c_dma *dma = i2c_dev->dma;
1383 void __iomem *base = i2c_dev->base;
1385 int ret = IRQ_HANDLED;
1387 /* Check if the interrupt if for a slave device */
1388 if (!i2c_dev->master_mode) {
1389 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1393 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1396 if (status & STM32F7_I2C_ISR_TXIS)
1397 stm32f7_i2c_write_tx_data(i2c_dev);
1400 if (status & STM32F7_I2C_ISR_RXNE)
1401 stm32f7_i2c_read_rx_data(i2c_dev);
1404 if (status & STM32F7_I2C_ISR_NACKF) {
1405 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1406 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1407 if (i2c_dev->use_dma) {
1408 stm32f7_i2c_disable_dma_req(i2c_dev);
1409 dmaengine_terminate_all(dma->chan_using);
1411 f7_msg->result = -ENXIO;
1414 /* STOP detection flag */
1415 if (status & STM32F7_I2C_ISR_STOPF) {
1416 /* Disable interrupts */
1417 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1418 mask = STM32F7_I2C_XFER_IRQ_MASK;
1420 mask = STM32F7_I2C_ALL_IRQ_MASK;
1421 stm32f7_i2c_disable_irq(i2c_dev, mask);
1423 /* Clear STOP flag */
1424 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1426 if (i2c_dev->use_dma && !f7_msg->result) {
1427 ret = IRQ_WAKE_THREAD;
1429 i2c_dev->master_mode = false;
1430 complete(&i2c_dev->complete);
1434 /* Transfer complete */
1435 if (status & STM32F7_I2C_ISR_TC) {
1437 mask = STM32F7_I2C_CR2_STOP;
1438 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1439 } else if (i2c_dev->use_dma && !f7_msg->result) {
1440 ret = IRQ_WAKE_THREAD;
1441 } else if (f7_msg->smbus) {
1442 stm32f7_i2c_smbus_rep_start(i2c_dev);
1446 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1450 if (status & STM32F7_I2C_ISR_TCR) {
1452 stm32f7_i2c_smbus_reload(i2c_dev);
1454 stm32f7_i2c_reload(i2c_dev);
1460 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1462 struct stm32f7_i2c_dev *i2c_dev = data;
1463 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1464 struct stm32_i2c_dma *dma = i2c_dev->dma;
1469 * Wait for dma transfer completion before sending next message or
1470 * notity the end of xfer to the client
1472 ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1474 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1475 stm32f7_i2c_disable_dma_req(i2c_dev);
1476 dmaengine_terminate_all(dma->chan_using);
1477 f7_msg->result = -ETIMEDOUT;
1480 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1482 if (status & STM32F7_I2C_ISR_TC) {
1483 if (f7_msg->smbus) {
1484 stm32f7_i2c_smbus_rep_start(i2c_dev);
1488 stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1491 i2c_dev->master_mode = false;
1492 complete(&i2c_dev->complete);
1498 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1500 struct stm32f7_i2c_dev *i2c_dev = data;
1501 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1502 void __iomem *base = i2c_dev->base;
1503 struct device *dev = i2c_dev->dev;
1504 struct stm32_i2c_dma *dma = i2c_dev->dma;
1507 status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1510 if (status & STM32F7_I2C_ISR_BERR) {
1511 dev_err(dev, "<%s>: Bus error\n", __func__);
1512 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1513 stm32f7_i2c_release_bus(&i2c_dev->adap);
1514 f7_msg->result = -EIO;
1517 /* Arbitration loss */
1518 if (status & STM32F7_I2C_ISR_ARLO) {
1519 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1520 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1521 f7_msg->result = -EAGAIN;
1524 if (status & STM32F7_I2C_ISR_PECERR) {
1525 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1526 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1527 f7_msg->result = -EINVAL;
1530 if (!i2c_dev->slave_running) {
1532 /* Disable interrupts */
1533 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1534 mask = STM32F7_I2C_XFER_IRQ_MASK;
1536 mask = STM32F7_I2C_ALL_IRQ_MASK;
1537 stm32f7_i2c_disable_irq(i2c_dev, mask);
1541 if (i2c_dev->use_dma) {
1542 stm32f7_i2c_disable_dma_req(i2c_dev);
1543 dmaengine_terminate_all(dma->chan_using);
1546 i2c_dev->master_mode = false;
1547 complete(&i2c_dev->complete);
1552 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1553 struct i2c_msg msgs[], int num)
1555 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1556 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1557 struct stm32_i2c_dma *dma = i2c_dev->dma;
1558 unsigned long time_left;
1561 i2c_dev->msg = msgs;
1562 i2c_dev->msg_num = num;
1563 i2c_dev->msg_id = 0;
1564 f7_msg->smbus = false;
1566 ret = clk_enable(i2c_dev->clk);
1568 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1572 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1576 stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1578 time_left = wait_for_completion_timeout(&i2c_dev->complete,
1579 i2c_dev->adap.timeout);
1580 ret = f7_msg->result;
1583 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1584 i2c_dev->msg->addr);
1585 if (i2c_dev->use_dma)
1586 dmaengine_terminate_all(dma->chan_using);
1587 stm32f7_i2c_wait_free_bus(i2c_dev);
1592 clk_disable(i2c_dev->clk);
1594 return (ret < 0) ? ret : num;
1597 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1598 unsigned short flags, char read_write,
1599 u8 command, int size,
1600 union i2c_smbus_data *data)
1602 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1603 struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1604 struct stm32_i2c_dma *dma = i2c_dev->dma;
1605 struct device *dev = i2c_dev->dev;
1606 unsigned long timeout;
1609 f7_msg->addr = addr;
1610 f7_msg->size = size;
1611 f7_msg->read_write = read_write;
1612 f7_msg->smbus = true;
1614 ret = clk_enable(i2c_dev->clk);
1616 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1620 ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1624 ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1628 timeout = wait_for_completion_timeout(&i2c_dev->complete,
1629 i2c_dev->adap.timeout);
1630 ret = f7_msg->result;
1635 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1636 if (i2c_dev->use_dma)
1637 dmaengine_terminate_all(dma->chan_using);
1638 stm32f7_i2c_wait_free_bus(i2c_dev);
1644 if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1645 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1650 if (read_write && size != I2C_SMBUS_QUICK) {
1652 case I2C_SMBUS_BYTE:
1653 case I2C_SMBUS_BYTE_DATA:
1654 data->byte = f7_msg->smbus_buf[0];
1656 case I2C_SMBUS_WORD_DATA:
1657 case I2C_SMBUS_PROC_CALL:
1658 data->word = f7_msg->smbus_buf[0] |
1659 (f7_msg->smbus_buf[1] << 8);
1661 case I2C_SMBUS_BLOCK_DATA:
1662 case I2C_SMBUS_BLOCK_PROC_CALL:
1663 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1664 data->block[i] = f7_msg->smbus_buf[i];
1667 dev_err(dev, "Unsupported smbus transaction\n");
1673 clk_disable(i2c_dev->clk);
1677 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1679 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1680 void __iomem *base = i2c_dev->base;
1681 struct device *dev = i2c_dev->dev;
1682 u32 oar1, oar2, mask;
1685 if (slave->flags & I2C_CLIENT_PEC) {
1686 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1690 if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1691 dev_err(dev, "Too much slave registered\n");
1695 ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1699 if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1700 ret = clk_enable(i2c_dev->clk);
1702 dev_err(dev, "Failed to enable clock\n");
1708 /* Configure Own Address 1 */
1709 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1710 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1711 if (slave->flags & I2C_CLIENT_TEN) {
1712 oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1713 oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1715 oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1717 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1718 i2c_dev->slave[id] = slave;
1719 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1720 } else if (id == 1) {
1721 /* Configure Own Address 2 */
1722 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1723 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1724 if (slave->flags & I2C_CLIENT_TEN) {
1729 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1730 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1731 i2c_dev->slave[id] = slave;
1732 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1739 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1741 /* Enable Address match interrupt, error interrupt and enable I2C */
1742 mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1744 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1749 if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1750 clk_disable(i2c_dev->clk);
1755 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1757 struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1758 void __iomem *base = i2c_dev->base;
1762 ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1766 WARN_ON(!i2c_dev->slave[id]);
1769 mask = STM32F7_I2C_OAR1_OA1EN;
1770 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1772 mask = STM32F7_I2C_OAR2_OA2EN;
1773 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1776 i2c_dev->slave[id] = NULL;
1778 if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1779 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1780 clk_disable(i2c_dev->clk);
1786 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1788 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1789 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1790 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1791 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1792 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC;
1795 static struct i2c_algorithm stm32f7_i2c_algo = {
1796 .master_xfer = stm32f7_i2c_xfer,
1797 .smbus_xfer = stm32f7_i2c_smbus_xfer,
1798 .functionality = stm32f7_i2c_func,
1799 .reg_slave = stm32f7_i2c_reg_slave,
1800 .unreg_slave = stm32f7_i2c_unreg_slave,
1803 static int stm32f7_i2c_probe(struct platform_device *pdev)
1805 struct stm32f7_i2c_dev *i2c_dev;
1806 const struct stm32f7_i2c_setup *setup;
1807 struct resource *res;
1808 u32 clk_rate, rise_time, fall_time;
1809 struct i2c_adapter *adap;
1810 struct reset_control *rst;
1811 dma_addr_t phy_addr;
1812 int irq_error, irq_event, ret;
1814 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1818 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1819 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1820 if (IS_ERR(i2c_dev->base))
1821 return PTR_ERR(i2c_dev->base);
1822 phy_addr = (dma_addr_t)res->start;
1824 irq_event = platform_get_irq(pdev, 0);
1825 if (irq_event <= 0) {
1826 if (irq_event != -EPROBE_DEFER)
1827 dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
1829 return irq_event ? : -ENOENT;
1832 irq_error = platform_get_irq(pdev, 1);
1833 if (irq_error <= 0) {
1834 if (irq_error != -EPROBE_DEFER)
1835 dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
1837 return irq_error ? : -ENOENT;
1840 i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1841 if (IS_ERR(i2c_dev->clk)) {
1842 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1843 return PTR_ERR(i2c_dev->clk);
1845 ret = clk_prepare_enable(i2c_dev->clk);
1847 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1851 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1852 ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1854 if (!ret && clk_rate >= 1000000)
1855 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1856 else if (!ret && clk_rate >= 400000)
1857 i2c_dev->speed = STM32_I2C_SPEED_FAST;
1858 else if (!ret && clk_rate >= 100000)
1859 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1861 rst = devm_reset_control_get(&pdev->dev, NULL);
1863 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1867 reset_control_assert(rst);
1869 reset_control_deassert(rst);
1871 i2c_dev->dev = &pdev->dev;
1873 ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1874 stm32f7_i2c_isr_event,
1875 stm32f7_i2c_isr_event_thread,
1877 pdev->name, i2c_dev);
1879 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1884 ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
1885 pdev->name, i2c_dev);
1887 dev_err(&pdev->dev, "Failed to request irq error %i\n",
1892 setup = of_device_get_match_data(&pdev->dev);
1894 dev_err(&pdev->dev, "Can't get device data\n");
1898 i2c_dev->setup = *setup;
1900 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
1903 i2c_dev->setup.rise_time = rise_time;
1905 ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
1908 i2c_dev->setup.fall_time = fall_time;
1910 ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
1914 stm32f7_i2c_hw_config(i2c_dev);
1916 adap = &i2c_dev->adap;
1917 i2c_set_adapdata(adap, i2c_dev);
1918 snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
1920 adap->owner = THIS_MODULE;
1921 adap->timeout = 2 * HZ;
1923 adap->algo = &stm32f7_i2c_algo;
1924 adap->dev.parent = &pdev->dev;
1925 adap->dev.of_node = pdev->dev.of_node;
1927 init_completion(&i2c_dev->complete);
1929 /* Init DMA config if supported */
1930 i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1933 if (PTR_ERR(i2c_dev->dma) == -ENODEV)
1934 i2c_dev->dma = NULL;
1935 else if (IS_ERR(i2c_dev->dma)) {
1936 ret = PTR_ERR(i2c_dev->dma);
1937 if (ret != -EPROBE_DEFER)
1939 "Failed to request dma error %i\n", ret);
1943 ret = i2c_add_adapter(adap);
1947 platform_set_drvdata(pdev, i2c_dev);
1949 clk_disable(i2c_dev->clk);
1951 dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
1956 clk_disable_unprepare(i2c_dev->clk);
1961 static int stm32f7_i2c_remove(struct platform_device *pdev)
1963 struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1966 stm32_i2c_dma_free(i2c_dev->dma);
1967 i2c_dev->dma = NULL;
1970 i2c_del_adapter(&i2c_dev->adap);
1972 clk_unprepare(i2c_dev->clk);
1977 static const struct of_device_id stm32f7_i2c_match[] = {
1978 { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
1981 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
1983 static struct platform_driver stm32f7_i2c_driver = {
1985 .name = "stm32f7-i2c",
1986 .of_match_table = stm32f7_i2c_match,
1988 .probe = stm32f7_i2c_probe,
1989 .remove = stm32f7_i2c_remove,
1992 module_platform_driver(stm32f7_i2c_driver);
1994 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
1995 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
1996 MODULE_LICENSE("GPL v2");