drivers/i2c/busses/i2c-stm32f7.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Driver for STMicroelectronics STM32F7 I2C controller
   4  *
   5  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   6  * reference manual.
   7  * Please see below a link to the documentation:
   8  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   9  *
  10  * Copyright (C) M'boumba Cedric Madianga 2017
  11  * Copyright (C) STMicroelectronics 2017
  12  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  13  *
  14  * This driver is based on i2c-stm32f4.c
  15  *
  16  */
  17 #include <linux/clk.h>
  18 #include <linux/delay.h>
  19 #include <linux/err.h>
  20 #include <linux/i2c.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/iopoll.h>
  24 #include <linux/module.h>
  25 #include <linux/of.h>
  26 #include <linux/of_address.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/reset.h>
  30 #include <linux/slab.h>
  31
  32 #include "i2c-stm32.h"
  33
  34 /* STM32F7 I2C registers */
  35 #define STM32F7_I2C_CR1                         0x00
  36 #define STM32F7_I2C_CR2                         0x04
  37 #define STM32F7_I2C_OAR1                        0x08
  38 #define STM32F7_I2C_OAR2                        0x0C
  39 #define STM32F7_I2C_PECR                        0x20
  40 #define STM32F7_I2C_TIMINGR                     0x10
  41 #define STM32F7_I2C_ISR                         0x18
  42 #define STM32F7_I2C_ICR                         0x1C
  43 #define STM32F7_I2C_RXDR                        0x24
  44 #define STM32F7_I2C_TXDR                        0x28
  45
  46 /* STM32F7 I2C control 1 */
  47 #define STM32F7_I2C_CR1_PECEN                   BIT(23)
  48 #define STM32F7_I2C_CR1_SBC                     BIT(16)
  49 #define STM32F7_I2C_CR1_RXDMAEN                 BIT(15)
  50 #define STM32F7_I2C_CR1_TXDMAEN                 BIT(14)
  51 #define STM32F7_I2C_CR1_ANFOFF                  BIT(12)
  52 #define STM32F7_I2C_CR1_DNF_MASK                GENMASK(11, 8)
  53 #define STM32F7_I2C_CR1_DNF(n)                  (((n) & 0xf) << 8)
  54 #define STM32F7_I2C_CR1_ERRIE                   BIT(7)
  55 #define STM32F7_I2C_CR1_TCIE                    BIT(6)
  56 #define STM32F7_I2C_CR1_STOPIE                  BIT(5)
  57 #define STM32F7_I2C_CR1_NACKIE                  BIT(4)
  58 #define STM32F7_I2C_CR1_ADDRIE                  BIT(3)
  59 #define STM32F7_I2C_CR1_RXIE                    BIT(2)
  60 #define STM32F7_I2C_CR1_TXIE                    BIT(1)
  61 #define STM32F7_I2C_CR1_PE                      BIT(0)
  62 #define STM32F7_I2C_ALL_IRQ_MASK                (STM32F7_I2C_CR1_ERRIE \
  63                                                 | STM32F7_I2C_CR1_TCIE \
  64                                                 | STM32F7_I2C_CR1_STOPIE \
  65                                                 | STM32F7_I2C_CR1_NACKIE \
  66                                                 | STM32F7_I2C_CR1_RXIE \
  67                                                 | STM32F7_I2C_CR1_TXIE)
  68 #define STM32F7_I2C_XFER_IRQ_MASK               (STM32F7_I2C_CR1_TCIE \
  69                                                 | STM32F7_I2C_CR1_STOPIE \
  70                                                 | STM32F7_I2C_CR1_NACKIE \
  71                                                 | STM32F7_I2C_CR1_RXIE \
  72                                                 | STM32F7_I2C_CR1_TXIE)
  73
  74 /* STM32F7 I2C control 2 */
  75 #define STM32F7_I2C_CR2_PECBYTE                 BIT(26)
  76 #define STM32F7_I2C_CR2_RELOAD                  BIT(24)
  77 #define STM32F7_I2C_CR2_NBYTES_MASK             GENMASK(23, 16)
  78 #define STM32F7_I2C_CR2_NBYTES(n)               (((n) & 0xff) << 16)
  79 #define STM32F7_I2C_CR2_NACK                    BIT(15)
  80 #define STM32F7_I2C_CR2_STOP                    BIT(14)
  81 #define STM32F7_I2C_CR2_START                   BIT(13)
  82 #define STM32F7_I2C_CR2_HEAD10R                 BIT(12)
  83 #define STM32F7_I2C_CR2_ADD10                   BIT(11)
  84 #define STM32F7_I2C_CR2_RD_WRN                  BIT(10)
  85 #define STM32F7_I2C_CR2_SADD10_MASK             GENMASK(9, 0)
  86 #define STM32F7_I2C_CR2_SADD10(n)               (((n) & \
  87                                                 STM32F7_I2C_CR2_SADD10_MASK))
  88 #define STM32F7_I2C_CR2_SADD7_MASK              GENMASK(7, 1)
  89 #define STM32F7_I2C_CR2_SADD7(n)                (((n) & 0x7f) << 1)
  90
  91 /* STM32F7 I2C Own Address 1 */
  92 #define STM32F7_I2C_OAR1_OA1EN                  BIT(15)
  93 #define STM32F7_I2C_OAR1_OA1MODE                BIT(10)
  94 #define STM32F7_I2C_OAR1_OA1_10_MASK            GENMASK(9, 0)
  95 #define STM32F7_I2C_OAR1_OA1_10(n)              (((n) & \
  96                                                 STM32F7_I2C_OAR1_OA1_10_MASK))
  97 #define STM32F7_I2C_OAR1_OA1_7_MASK             GENMASK(7, 1)
  98 #define STM32F7_I2C_OAR1_OA1_7(n)               (((n) & 0x7f) << 1)
  99 #define STM32F7_I2C_OAR1_MASK                   (STM32F7_I2C_OAR1_OA1_7_MASK \
 100                                                 | STM32F7_I2C_OAR1_OA1_10_MASK \
 101                                                 | STM32F7_I2C_OAR1_OA1EN \
 102                                                 | STM32F7_I2C_OAR1_OA1MODE)
 103
 104 /* STM32F7 I2C Own Address 2 */
 105 #define STM32F7_I2C_OAR2_OA2EN                  BIT(15)
 106 #define STM32F7_I2C_OAR2_OA2MSK_MASK            GENMASK(10, 8)
 107 #define STM32F7_I2C_OAR2_OA2MSK(n)              (((n) & 0x7) << 8)
 108 #define STM32F7_I2C_OAR2_OA2_7_MASK             GENMASK(7, 1)
 109 #define STM32F7_I2C_OAR2_OA2_7(n)               (((n) & 0x7f) << 1)
 110 #define STM32F7_I2C_OAR2_MASK                   (STM32F7_I2C_OAR2_OA2MSK_MASK \
 111                                                 | STM32F7_I2C_OAR2_OA2_7_MASK \
 112                                                 | STM32F7_I2C_OAR2_OA2EN)
 113
 114 /* STM32F7 I2C Interrupt Status */
 115 #define STM32F7_I2C_ISR_ADDCODE_MASK            GENMASK(23, 17)
 116 #define STM32F7_I2C_ISR_ADDCODE_GET(n) \
 117                                 (((n) & STM32F7_I2C_ISR_ADDCODE_MASK) >> 17)
 118 #define STM32F7_I2C_ISR_DIR                     BIT(16)
 119 #define STM32F7_I2C_ISR_BUSY                    BIT(15)
 120 #define STM32F7_I2C_ISR_PECERR                  BIT(11)
 121 #define STM32F7_I2C_ISR_ARLO                    BIT(9)
 122 #define STM32F7_I2C_ISR_BERR                    BIT(8)
 123 #define STM32F7_I2C_ISR_TCR                     BIT(7)
 124 #define STM32F7_I2C_ISR_TC                      BIT(6)
 125 #define STM32F7_I2C_ISR_STOPF                   BIT(5)
 126 #define STM32F7_I2C_ISR_NACKF                   BIT(4)
 127 #define STM32F7_I2C_ISR_ADDR                    BIT(3)
 128 #define STM32F7_I2C_ISR_RXNE                    BIT(2)
 129 #define STM32F7_I2C_ISR_TXIS                    BIT(1)
 130 #define STM32F7_I2C_ISR_TXE                     BIT(0)
 131
 132 /* STM32F7 I2C Interrupt Clear */
 133 #define STM32F7_I2C_ICR_PECCF                   BIT(11)
 134 #define STM32F7_I2C_ICR_ARLOCF                  BIT(9)
 135 #define STM32F7_I2C_ICR_BERRCF                  BIT(8)
 136 #define STM32F7_I2C_ICR_STOPCF                  BIT(5)
 137 #define STM32F7_I2C_ICR_NACKCF                  BIT(4)
 138 #define STM32F7_I2C_ICR_ADDRCF                  BIT(3)
 139
 140 /* STM32F7 I2C Timing */
 141 #define STM32F7_I2C_TIMINGR_PRESC(n)            (((n) & 0xf) << 28)
 142 #define STM32F7_I2C_TIMINGR_SCLDEL(n)           (((n) & 0xf) << 20)
 143 #define STM32F7_I2C_TIMINGR_SDADEL(n)           (((n) & 0xf) << 16)
 144 #define STM32F7_I2C_TIMINGR_SCLH(n)             (((n) & 0xff) << 8)
 145 #define STM32F7_I2C_TIMINGR_SCLL(n)             ((n) & 0xff)
 146
 147 #define STM32F7_I2C_MAX_LEN                     0xff
 148 #define STM32F7_I2C_DMA_LEN_MIN                 0x16
 149 #define STM32F7_I2C_MAX_SLAVE                   0x2
 150
 151 #define STM32F7_I2C_DNF_DEFAULT                 0
 152 #define STM32F7_I2C_DNF_MAX                     15
 153
 154 #define STM32F7_I2C_ANALOG_FILTER_ENABLE        1
 155 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN     50      /* ns */
 156 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX     260     /* ns */
 157
 158 #define STM32F7_I2C_RISE_TIME_DEFAULT           25      /* ns */
 159 #define STM32F7_I2C_FALL_TIME_DEFAULT           10      /* ns */
 160
 161 #define STM32F7_PRESC_MAX                       BIT(4)
 162 #define STM32F7_SCLDEL_MAX                      BIT(4)
 163 #define STM32F7_SDADEL_MAX                      BIT(4)
 164 #define STM32F7_SCLH_MAX                        BIT(8)
 165 #define STM32F7_SCLL_MAX                        BIT(8)
 166
 167 /**
 168  * struct stm32f7_i2c_spec - private i2c specification timing
 169  * @rate: I2C bus speed (Hz)
 170  * @rate_min: 80% of I2C bus speed (Hz)
 171  * @rate_max: 100% of I2C bus speed (Hz)
 172  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 173  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 174  * @hddat_min: Min data hold time (ns)
 175  * @vddat_max: Max data valid time (ns)
 176  * @sudat_min: Min data setup time (ns)
 177  * @l_min: Min low period of the SCL clock (ns)
 178  * @h_min: Min high period of the SCL clock (ns)
 179  */
 180 struct stm32f7_i2c_spec {
 181         u32 rate;
 182         u32 rate_min;
 183         u32 rate_max;
 184         u32 fall_max;
 185         u32 rise_max;
 186         u32 hddat_min;
 187         u32 vddat_max;
 188         u32 sudat_min;
 189         u32 l_min;
 190         u32 h_min;
 191 };
 192
 193 /**
 194  * struct stm32f7_i2c_setup - private I2C timing setup parameters
 195  * @speed: I2C speed mode (standard, Fast Plus)
 196  * @speed_freq: I2C speed frequency  (Hz)
 197  * @clock_src: I2C clock source frequency (Hz)
 198  * @rise_time: Rise time (ns)
 199  * @fall_time: Fall time (ns)
 200  * @dnf: Digital filter coefficient (0-16)
 201  * @analog_filter: Analog filter delay (On/Off)
 202  */
 203 struct stm32f7_i2c_setup {
 204         enum stm32_i2c_speed speed;
 205         u32 speed_freq;
 206         u32 clock_src;
 207         u32 rise_time;
 208         u32 fall_time;
 209         u8 dnf;
 210         bool analog_filter;
 211 };
 212
 213 /**
 214  * struct stm32f7_i2c_timings - private I2C output parameters
 215  * @node: List entry
 216  * @presc: Prescaler value
 217  * @scldel: Data setup time
 218  * @sdadel: Data hold time
 219  * @sclh: SCL high period (master mode)
 220  * @scll: SCL low period (master mode)
 221  */
 222 struct stm32f7_i2c_timings {
 223         struct list_head node;
 224         u8 presc;
 225         u8 scldel;
 226         u8 sdadel;
 227         u8 sclh;
 228         u8 scll;
 229 };
 230
 231 /**
 232  * struct stm32f7_i2c_msg - client specific data
 233  * @addr: 8-bit or 10-bit slave addr, including r/w bit
 234  * @count: number of bytes to be transferred
 235  * @buf: data buffer
 236  * @result: result of the transfer
 237  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 238  * @smbus: boolean to know if the I2C IP is used in SMBus mode
 239  * @size: type of SMBus protocol
 240  * @read_write: direction of SMBus protocol
 241  * SMBus block read and SMBus block write - block read process call protocols
 242  * @smbus_buf: buffer to be used for SMBus protocol transfer. It will
 243  * contain a maximum of 32 bytes of data + byte command + byte count + PEC
 244  * This buffer has to be 32-bit aligned to be compliant with memory address
 245  * register in DMA mode.
 246  */
 247 struct stm32f7_i2c_msg {
 248         u16 addr;
 249         u32 count;
 250         u8 *buf;
 251         int result;
 252         bool stop;
 253         bool smbus;
 254         int size;
 255         char read_write;
 256         u8 smbus_buf[I2C_SMBUS_BLOCK_MAX + 3] __aligned(4);
 257 };
 258
 259 /**
 260  * struct stm32f7_i2c_dev - private data of the controller
 261  * @adap: I2C adapter for this controller
 262  * @dev: device for this controller
 263  * @base: virtual memory area
 264  * @complete: completion of I2C message
 265  * @clk: hw i2c clock
 266  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 267  * @msg: Pointer to data to be written
 268  * @msg_num: number of I2C messages to be executed
 269  * @msg_id: message identifiant
 270  * @f7_msg: customized i2c msg for driver usage
 271  * @setup: I2C timing input setup
 272  * @timing: I2C computed timings
 273  * @slave: list of slave devices registered on the I2C bus
 274  * @slave_running: slave device currently used
 275  * @slave_dir: transfer direction for the current slave device
 276  * @master_mode: boolean to know in which mode the I2C is running (master or
 277  * slave)
 278  * @dma: dma data
 279  * @use_dma: boolean to know if dma is used in the current transfer
 280  */
 281 struct stm32f7_i2c_dev {
 282         struct i2c_adapter adap;
 283         struct device *dev;
 284         void __iomem *base;
 285         struct completion complete;
 286         struct clk *clk;
 287         int speed;
 288         struct i2c_msg *msg;
 289         unsigned int msg_num;
 290         unsigned int msg_id;
 291         struct stm32f7_i2c_msg f7_msg;
 292         struct stm32f7_i2c_setup setup;
 293         struct stm32f7_i2c_timings timing;
 294         struct i2c_client *slave[STM32F7_I2C_MAX_SLAVE];
 295         struct i2c_client *slave_running;
 296         u32 slave_dir;
 297         bool master_mode;
 298         struct stm32_i2c_dma *dma;
 299         bool use_dma;
 300 };
 301
 302 /*
 303  * All these values are coming from I2C Specification, Version 6.0, 4th of
 304  * April 2014.
 305  *
 306  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 307  * and Fast-mode Plus I2C-bus devices
 308  */
 309 static struct stm32f7_i2c_spec i2c_specs[] = {
 310         [STM32_I2C_SPEED_STANDARD] = {
 311                 .rate = 100000,
 312                 .rate_min = 80000,
 313                 .rate_max = 100000,
 314                 .fall_max = 300,
 315                 .rise_max = 1000,
 316                 .hddat_min = 0,
 317                 .vddat_max = 3450,
 318                 .sudat_min = 250,
 319                 .l_min = 4700,
 320                 .h_min = 4000,
 321         },
 322         [STM32_I2C_SPEED_FAST] = {
 323                 .rate = 400000,
 324                 .rate_min = 320000,
 325                 .rate_max = 400000,
 326                 .fall_max = 300,
 327                 .rise_max = 300,
 328                 .hddat_min = 0,
 329                 .vddat_max = 900,
 330                 .sudat_min = 100,
 331                 .l_min = 1300,
 332                 .h_min = 600,
 333         },
 334         [STM32_I2C_SPEED_FAST_PLUS] = {
 335                 .rate = 1000000,
 336                 .rate_min = 800000,
 337                 .rate_max = 1000000,
 338                 .fall_max = 100,
 339                 .rise_max = 120,
 340                 .hddat_min = 0,
 341                 .vddat_max = 450,
 342                 .sudat_min = 50,
 343                 .l_min = 500,
 344                 .h_min = 260,
 345         },
 346 };
 347
 348 static const struct stm32f7_i2c_setup stm32f7_setup = {
 349         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 350         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 351         .dnf = STM32F7_I2C_DNF_DEFAULT,
 352         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 353 };
 354
 355 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 356 {
 357         writel_relaxed(readl_relaxed(reg) | mask, reg);
 358 }
 359
 360 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 361 {
 362         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 363 }
 364
 365 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 366 {
 367         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 368 }
 369
 370 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 371                                       struct stm32f7_i2c_setup *setup,
 372                                       struct stm32f7_i2c_timings *output)
 373 {
 374         u32 p_prev = STM32F7_PRESC_MAX;
 375         u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 376                                        setup->clock_src);
 377         u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 378                                        setup->speed_freq);
 379         u32 clk_error_prev = i2cbus;
 380         u32 tsync;
 381         u32 af_delay_min, af_delay_max;
 382         u32 dnf_delay;
 383         u32 clk_min, clk_max;
 384         int sdadel_min, sdadel_max;
 385         int scldel_min;
 386         struct stm32f7_i2c_timings *v, *_v, *s;
 387         struct list_head solutions;
 388         u16 p, l, a, h;
 389         int ret = 0;
 390
 391         if (setup->speed >= STM32_I2C_SPEED_END) {
 392                 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
 393                         setup->speed, STM32_I2C_SPEED_END - 1);
 394                 return -EINVAL;
 395         }
 396
 397         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 398             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 399                 dev_err(i2c_dev->dev,
 400                         "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 401                         setup->rise_time, i2c_specs[setup->speed].rise_max,
 402                         setup->fall_time, i2c_specs[setup->speed].fall_max);
 403                 return -EINVAL;
 404         }
 405
 406         if (setup->dnf > STM32F7_I2C_DNF_MAX) {
 407                 dev_err(i2c_dev->dev,
 408                         "DNF out of bound %d/%d\n",
 409                         setup->dnf, STM32F7_I2C_DNF_MAX);
 410                 return -EINVAL;
 411         }
 412
 413         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 414                 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
 415                         setup->speed_freq, i2c_specs[setup->speed].rate);
 416                 return -EINVAL;
 417         }
 418
 419         /*  Analog and Digital Filters */
 420         af_delay_min =
 421                 (setup->analog_filter ?
 422                  STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 423         af_delay_max =
 424                 (setup->analog_filter ?
 425                  STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 426         dnf_delay = setup->dnf * i2cclk;
 427
 428         sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
 429                 af_delay_min - (setup->dnf + 3) * i2cclk;
 430
 431         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 432                 af_delay_max - (setup->dnf + 4) * i2cclk;
 433
 434         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 435
 436         if (sdadel_min < 0)
 437                 sdadel_min = 0;
 438         if (sdadel_max < 0)
 439                 sdadel_max = 0;
 440
 441         dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 442                 sdadel_min, sdadel_max, scldel_min);
 443
 444         INIT_LIST_HEAD(&solutions);
 445         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 446         for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 447                 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 448                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 449
 450                         if (scldel < scldel_min)
 451                                 continue;
 452
 453                         for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 454                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 455
 456                                 if (((sdadel >= sdadel_min) &&
 457                                      (sdadel <= sdadel_max)) &&
 458                                     (p != p_prev)) {
 459                                         v = kmalloc(sizeof(*v), GFP_KERNEL);
 460                                         if (!v) {
 461                                                 ret = -ENOMEM;
 462                                                 goto exit;
 463                                         }
 464
 465                                         v->presc = p;
 466                                         v->scldel = l;
 467                                         v->sdadel = a;
 468                                         p_prev = p;
 469
 470                                         list_add_tail(&v->node,
 471                                                       &solutions);
 472                                 }
 473                         }
 474                 }
 475         }
 476
 477         if (list_empty(&solutions)) {
 478                 dev_err(i2c_dev->dev, "no Prescaler solution\n");
 479                 ret = -EPERM;
 480                 goto exit;
 481         }
 482
 483         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 484         s = NULL;
 485         clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 486         clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 487
 488         /*
 489          * Among Prescaler possibilities discovered above figures out SCL Low
 490          * and High Period. Provided:
 491          * - SCL Low Period has to be higher than SCL Clock Low Period
 492          *   defined by I2C Specification. I2C Clock has to be lower than
 493          *   (SCL Low Period - Analog/Digital filters) / 4.
 494          * - SCL High Period has to be lower than SCL Clock High Period
 495          *   defined by I2C Specification
 496          * - I2C Clock has to be lower than SCL High Period
 497          */
 498         list_for_each_entry(v, &solutions, node) {
 499                 u32 prescaler = (v->presc + 1) * i2cclk;
 500
 501                 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 502                         u32 tscl_l = (l + 1) * prescaler + tsync;
 503
 504                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 505                             (i2cclk >=
 506                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 507                                 continue;
 508                         }
 509
 510                         for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 511                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 512                                 u32 tscl = tscl_l + tscl_h +
 513                                         setup->rise_time + setup->fall_time;
 514
 515                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 516                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 517                                     (i2cclk < tscl_h)) {
 518                                         int clk_error = tscl - i2cbus;
 519
 520                                         if (clk_error < 0)
 521                                                 clk_error = -clk_error;
 522
 523                                         if (clk_error < clk_error_prev) {
 524                                                 clk_error_prev = clk_error;
 525                                                 v->scll = l;
 526                                                 v->sclh = h;
 527                                                 s = v;
 528                                         }
 529                                 }
 530                         }
 531                 }
 532         }
 533
 534         if (!s) {
 535                 dev_err(i2c_dev->dev, "no solution at all\n");
 536                 ret = -EPERM;
 537                 goto exit;
 538         }
 539
 540         output->presc = s->presc;
 541         output->scldel = s->scldel;
 542         output->sdadel = s->sdadel;
 543         output->scll = s->scll;
 544         output->sclh = s->sclh;
 545
 546         dev_dbg(i2c_dev->dev,
 547                 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 548                 output->presc,
 549                 output->scldel, output->sdadel,
 550                 output->scll, output->sclh);
 551
 552 exit:
 553         /* Release list and memory */
 554         list_for_each_entry_safe(v, _v, &solutions, node) {
 555                 list_del(&v->node);
 556                 kfree(v);
 557         }
 558
 559         return ret;
 560 }
 561
 562 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 563                                     struct stm32f7_i2c_setup *setup)
 564 {
 565         int ret = 0;
 566
 567         setup->speed = i2c_dev->speed;
 568         setup->speed_freq = i2c_specs[setup->speed].rate;
 569         setup->clock_src = clk_get_rate(i2c_dev->clk);
 570
 571         if (!setup->clock_src) {
 572                 dev_err(i2c_dev->dev, "clock rate is 0\n");
 573                 return -EINVAL;
 574         }
 575
 576         do {
 577                 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 578                                                  &i2c_dev->timing);
 579                 if (ret) {
 580                         dev_err(i2c_dev->dev,
 581                                 "failed to compute I2C timings.\n");
 582                         if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
 583                                 i2c_dev->speed--;
 584                                 setup->speed = i2c_dev->speed;
 585                                 setup->speed_freq =
 586                                         i2c_specs[setup->speed].rate;
 587                                 dev_warn(i2c_dev->dev,
 588                                          "downgrade I2C Speed Freq to (%i)\n",
 589                                          i2c_specs[setup->speed].rate);
 590                         } else {
 591                                 break;
 592                         }
 593                 }
 594         } while (ret);
 595
 596         if (ret) {
 597                 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 598                 return ret;
 599         }
 600
 601         dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
 602                 setup->speed, setup->speed_freq, setup->clock_src);
 603         dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 604                 setup->rise_time, setup->fall_time);
 605         dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 606                 (setup->analog_filter ? "On" : "Off"), setup->dnf);
 607
 608         return 0;
 609 }
 610
 611 static void stm32f7_i2c_disable_dma_req(struct stm32f7_i2c_dev *i2c_dev)
 612 {
 613         void __iomem *base = i2c_dev->base;
 614         u32 mask = STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN;
 615
 616         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
 617 }
 618
 619 static void stm32f7_i2c_dma_callback(void *arg)
 620 {
 621         struct stm32f7_i2c_dev *i2c_dev = (struct stm32f7_i2c_dev *)arg;
 622         struct stm32_i2c_dma *dma = i2c_dev->dma;
 623         struct device *dev = dma->chan_using->device->dev;
 624
 625         stm32f7_i2c_disable_dma_req(i2c_dev);
 626         dma_unmap_single(dev, dma->dma_buf, dma->dma_len, dma->dma_data_dir);
 627         complete(&dma->dma_complete);
 628 }
 629
 630 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 631 {
 632         struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 633         u32 timing = 0;
 634
 635         /* Timing settings */
 636         timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 637         timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 638         timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 639         timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 640         timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 641         writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 642
 643         /* Enable I2C */
 644         if (i2c_dev->setup.analog_filter)
 645                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 646                                      STM32F7_I2C_CR1_ANFOFF);
 647         else
 648                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 649                                      STM32F7_I2C_CR1_ANFOFF);
 650
 651         /* Program the Digital Filter */
 652         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 653                              STM32F7_I2C_CR1_DNF_MASK);
 654         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 655                              STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
 656
 657         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 658                              STM32F7_I2C_CR1_PE);
 659 }
 660
 661 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 662 {
 663         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 664         void __iomem *base = i2c_dev->base;
 665
 666         if (f7_msg->count) {
 667                 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 668                 f7_msg->count--;
 669         }
 670 }
 671
 672 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 673 {
 674         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 675         void __iomem *base = i2c_dev->base;
 676
 677         if (f7_msg->count) {
 678                 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 679                 f7_msg->count--;
 680         } else {
 681                 /* Flush RX buffer has no data is expected */
 682                 readb_relaxed(base + STM32F7_I2C_RXDR);
 683         }
 684 }
 685
 686 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 687 {
 688         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 689         u32 cr2;
 690
 691         if (i2c_dev->use_dma)
 692                 f7_msg->count -= STM32F7_I2C_MAX_LEN;
 693
 694         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 695
 696         cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 697         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 698                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 699         } else {
 700                 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 701                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 702         }
 703
 704         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 705 }
 706
 707 static void stm32f7_i2c_smbus_reload(struct stm32f7_i2c_dev *i2c_dev)
 708 {
 709         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 710         u32 cr2;
 711         u8 *val;
 712
 713         /*
 714          * For I2C_SMBUS_BLOCK_DATA && I2C_SMBUS_BLOCK_PROC_CALL, the first
 715          * data received inform us how many data will follow.
 716          */
 717         stm32f7_i2c_read_rx_data(i2c_dev);
 718
 719         /*
 720          * Update NBYTES with the value read to continue the transfer
 721          */
 722         val = f7_msg->buf - sizeof(u8);
 723         f7_msg->count = *val;
 724         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 725         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 726         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 727         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 728 }
 729
 730 static int stm32f7_i2c_release_bus(struct i2c_adapter *i2c_adap)
 731 {
 732         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 733
 734         dev_info(i2c_dev->dev, "Trying to recover bus\n");
 735
 736         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 737                              STM32F7_I2C_CR1_PE);
 738
 739         stm32f7_i2c_hw_config(i2c_dev);
 740
 741         return 0;
 742 }
 743
 744 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 745 {
 746         u32 status;
 747         int ret;
 748
 749         ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 750                                          status,
 751                                          !(status & STM32F7_I2C_ISR_BUSY),
 752                                          10, 1000);
 753         if (!ret)
 754                 return 0;
 755
 756         dev_info(i2c_dev->dev, "bus busy\n");
 757
 758         ret = stm32f7_i2c_release_bus(&i2c_dev->adap);
 759         if (ret) {
 760                 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret);
 761                 return ret;
 762         }
 763
 764         return -EBUSY;
 765 }
 766
 767 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 768                                  struct i2c_msg *msg)
 769 {
 770         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 771         void __iomem *base = i2c_dev->base;
 772         u32 cr1, cr2;
 773         int ret;
 774
 775         f7_msg->addr = msg->addr;
 776         f7_msg->buf = msg->buf;
 777         f7_msg->count = msg->len;
 778         f7_msg->result = 0;
 779         f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 780
 781         reinit_completion(&i2c_dev->complete);
 782
 783         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 784         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 785
 786         /* Set transfer direction */
 787         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 788         if (msg->flags & I2C_M_RD)
 789                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 790
 791         /* Set slave address */
 792         cr2 &= ~(STM32F7_I2C_CR2_HEAD10R | STM32F7_I2C_CR2_ADD10);
 793         if (msg->flags & I2C_M_TEN) {
 794                 cr2 &= ~STM32F7_I2C_CR2_SADD10_MASK;
 795                 cr2 |= STM32F7_I2C_CR2_SADD10(f7_msg->addr);
 796                 cr2 |= STM32F7_I2C_CR2_ADD10;
 797         } else {
 798                 cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 799                 cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 800         }
 801
 802         /* Set nb bytes to transfer and reload if needed */
 803         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 804         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 805                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 806                 cr2 |= STM32F7_I2C_CR2_RELOAD;
 807         } else {
 808                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 809         }
 810
 811         /* Enable NACK, STOP, error and transfer complete interrupts */
 812         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 813                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 814
 815         /* Clear DMA req and TX/RX interrupt */
 816         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 817                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 818
 819         /* Configure DMA or enable RX/TX interrupt */
 820         i2c_dev->use_dma = false;
 821         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 822                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 823                                               msg->flags & I2C_M_RD,
 824                                               f7_msg->count, f7_msg->buf,
 825                                               stm32f7_i2c_dma_callback,
 826                                               i2c_dev);
 827                 if (!ret)
 828                         i2c_dev->use_dma = true;
 829                 else
 830                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 831         }
 832
 833         if (!i2c_dev->use_dma) {
 834                 if (msg->flags & I2C_M_RD)
 835                         cr1 |= STM32F7_I2C_CR1_RXIE;
 836                 else
 837                         cr1 |= STM32F7_I2C_CR1_TXIE;
 838         } else {
 839                 if (msg->flags & I2C_M_RD)
 840                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
 841                 else
 842                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
 843         }
 844
 845         /* Configure Start/Repeated Start */
 846         cr2 |= STM32F7_I2C_CR2_START;
 847
 848         i2c_dev->master_mode = true;
 849
 850         /* Write configurations registers */
 851         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 852         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 853 }
 854
 855 static int stm32f7_i2c_smbus_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 856                                       unsigned short flags, u8 command,
 857                                       union i2c_smbus_data *data)
 858 {
 859         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 860         struct device *dev = i2c_dev->dev;
 861         void __iomem *base = i2c_dev->base;
 862         u32 cr1, cr2;
 863         int i, ret;
 864
 865         f7_msg->result = 0;
 866         reinit_completion(&i2c_dev->complete);
 867
 868         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 869         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 870
 871         /* Set transfer direction */
 872         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 873         if (f7_msg->read_write)
 874                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 875
 876         /* Set slave address */
 877         cr2 &= ~(STM32F7_I2C_CR2_ADD10 | STM32F7_I2C_CR2_SADD7_MASK);
 878         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 879
 880         f7_msg->smbus_buf[0] = command;
 881         switch (f7_msg->size) {
 882         case I2C_SMBUS_QUICK:
 883                 f7_msg->stop = true;
 884                 f7_msg->count = 0;
 885                 break;
 886         case I2C_SMBUS_BYTE:
 887                 f7_msg->stop = true;
 888                 f7_msg->count = 1;
 889                 break;
 890         case I2C_SMBUS_BYTE_DATA:
 891                 if (f7_msg->read_write) {
 892                         f7_msg->stop = false;
 893                         f7_msg->count = 1;
 894                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 895                 } else {
 896                         f7_msg->stop = true;
 897                         f7_msg->count = 2;
 898                         f7_msg->smbus_buf[1] = data->byte;
 899                 }
 900                 break;
 901         case I2C_SMBUS_WORD_DATA:
 902                 if (f7_msg->read_write) {
 903                         f7_msg->stop = false;
 904                         f7_msg->count = 1;
 905                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 906                 } else {
 907                         f7_msg->stop = true;
 908                         f7_msg->count = 3;
 909                         f7_msg->smbus_buf[1] = data->word & 0xff;
 910                         f7_msg->smbus_buf[2] = data->word >> 8;
 911                 }
 912                 break;
 913         case I2C_SMBUS_BLOCK_DATA:
 914                 if (f7_msg->read_write) {
 915                         f7_msg->stop = false;
 916                         f7_msg->count = 1;
 917                         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 918                 } else {
 919                         f7_msg->stop = true;
 920                         if (data->block[0] > I2C_SMBUS_BLOCK_MAX ||
 921                             !data->block[0]) {
 922                                 dev_err(dev, "Invalid block write size %d\n",
 923                                         data->block[0]);
 924                                 return -EINVAL;
 925                         }
 926                         f7_msg->count = data->block[0] + 2;
 927                         for (i = 1; i < f7_msg->count; i++)
 928                                 f7_msg->smbus_buf[i] = data->block[i - 1];
 929                 }
 930                 break;
 931         case I2C_SMBUS_PROC_CALL:
 932                 f7_msg->stop = false;
 933                 f7_msg->count = 3;
 934                 f7_msg->smbus_buf[1] = data->word & 0xff;
 935                 f7_msg->smbus_buf[2] = data->word >> 8;
 936                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 937                 f7_msg->read_write = I2C_SMBUS_READ;
 938                 break;
 939         case I2C_SMBUS_BLOCK_PROC_CALL:
 940                 f7_msg->stop = false;
 941                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX - 1) {
 942                         dev_err(dev, "Invalid block write size %d\n",
 943                                 data->block[0]);
 944                         return -EINVAL;
 945                 }
 946                 f7_msg->count = data->block[0] + 2;
 947                 for (i = 1; i < f7_msg->count; i++)
 948                         f7_msg->smbus_buf[i] = data->block[i - 1];
 949                 cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 950                 f7_msg->read_write = I2C_SMBUS_READ;
 951                 break;
 952         default:
 953                 dev_err(dev, "Unsupported smbus protocol %d\n", f7_msg->size);
 954                 return -EOPNOTSUPP;
 955         }
 956
 957         f7_msg->buf = f7_msg->smbus_buf;
 958
 959         /* Configure PEC */
 960         if ((flags & I2C_CLIENT_PEC) && f7_msg->size != I2C_SMBUS_QUICK) {
 961                 cr1 |= STM32F7_I2C_CR1_PECEN;
 962                 if (!f7_msg->read_write) {
 963                         cr2 |= STM32F7_I2C_CR2_PECBYTE;
 964                         f7_msg->count++;
 965                 }
 966         } else {
 967                 cr1 &= ~STM32F7_I2C_CR1_PECEN;
 968                 cr2 &= ~STM32F7_I2C_CR2_PECBYTE;
 969         }
 970
 971         /* Set number of bytes to be transferred */
 972         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 973         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 974
 975         /* Enable NACK, STOP, error and transfer complete interrupts */
 976         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 977                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 978
 979         /* Clear DMA req and TX/RX interrupt */
 980         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
 981                         STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
 982
 983         /* Configure DMA or enable RX/TX interrupt */
 984         i2c_dev->use_dma = false;
 985         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN) {
 986                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
 987                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
 988                                               f7_msg->count, f7_msg->buf,
 989                                               stm32f7_i2c_dma_callback,
 990                                               i2c_dev);
 991                 if (!ret)
 992                         i2c_dev->use_dma = true;
 993                 else
 994                         dev_warn(i2c_dev->dev, "can't use DMA\n");
 995         }
 996
 997         if (!i2c_dev->use_dma) {
 998                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
 999                         cr1 |= STM32F7_I2C_CR1_RXIE;
1000                 else
1001                         cr1 |= STM32F7_I2C_CR1_TXIE;
1002         } else {
1003                 if (cr2 & STM32F7_I2C_CR2_RD_WRN)
1004                         cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1005                 else
1006                         cr1 |= STM32F7_I2C_CR1_TXDMAEN;
1007         }
1008
1009         /* Set Start bit */
1010         cr2 |= STM32F7_I2C_CR2_START;
1011
1012         i2c_dev->master_mode = true;
1013
1014         /* Write configurations registers */
1015         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1016         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1017
1018         return 0;
1019 }
1020
1021 static void stm32f7_i2c_smbus_rep_start(struct stm32f7_i2c_dev *i2c_dev)
1022 {
1023         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1024         void __iomem *base = i2c_dev->base;
1025         u32 cr1, cr2;
1026         int ret;
1027
1028         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
1029         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
1030
1031         /* Set transfer direction */
1032         cr2 |= STM32F7_I2C_CR2_RD_WRN;
1033
1034         switch (f7_msg->size) {
1035         case I2C_SMBUS_BYTE_DATA:
1036                 f7_msg->count = 1;
1037                 break;
1038         case I2C_SMBUS_WORD_DATA:
1039         case I2C_SMBUS_PROC_CALL:
1040                 f7_msg->count = 2;
1041                 break;
1042         case I2C_SMBUS_BLOCK_DATA:
1043         case I2C_SMBUS_BLOCK_PROC_CALL:
1044                 f7_msg->count = 1;
1045                 cr2 |= STM32F7_I2C_CR2_RELOAD;
1046                 break;
1047         }
1048
1049         f7_msg->buf = f7_msg->smbus_buf;
1050         f7_msg->stop = true;
1051
1052         /* Add one byte for PEC if needed */
1053         if (cr1 & STM32F7_I2C_CR1_PECEN) {
1054                 cr2 |= STM32F7_I2C_CR2_PECBYTE;
1055                 f7_msg->count++;
1056         }
1057
1058         /* Set number of bytes to be transferred */
1059         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK);
1060         cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
1061
1062         /*
1063          * Configure RX/TX interrupt:
1064          */
1065         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
1066         cr1 |= STM32F7_I2C_CR1_RXIE;
1067
1068         /*
1069          * Configure DMA or enable RX/TX interrupt:
1070          * For I2C_SMBUS_BLOCK_DATA and I2C_SMBUS_BLOCK_PROC_CALL we don't use
1071          * dma as we don't know in advance how many data will be received
1072          */
1073         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE |
1074                  STM32F7_I2C_CR1_RXDMAEN | STM32F7_I2C_CR1_TXDMAEN);
1075
1076         i2c_dev->use_dma = false;
1077         if (i2c_dev->dma && f7_msg->count >= STM32F7_I2C_DMA_LEN_MIN &&
1078             f7_msg->size != I2C_SMBUS_BLOCK_DATA &&
1079             f7_msg->size != I2C_SMBUS_BLOCK_PROC_CALL) {
1080                 ret = stm32_i2c_prep_dma_xfer(i2c_dev->dev, i2c_dev->dma,
1081                                               cr2 & STM32F7_I2C_CR2_RD_WRN,
1082                                               f7_msg->count, f7_msg->buf,
1083                                               stm32f7_i2c_dma_callback,
1084                                               i2c_dev);
1085
1086                 if (!ret)
1087                         i2c_dev->use_dma = true;
1088                 else
1089                         dev_warn(i2c_dev->dev, "can't use DMA\n");
1090         }
1091
1092         if (!i2c_dev->use_dma)
1093                 cr1 |= STM32F7_I2C_CR1_RXIE;
1094         else
1095                 cr1 |= STM32F7_I2C_CR1_RXDMAEN;
1096
1097         /* Configure Repeated Start */
1098         cr2 |= STM32F7_I2C_CR2_START;
1099
1100         /* Write configurations registers */
1101         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
1102         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
1103 }
1104
1105 static int stm32f7_i2c_smbus_check_pec(struct stm32f7_i2c_dev *i2c_dev)
1106 {
1107         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1108         u8 count, internal_pec, received_pec;
1109
1110         internal_pec = readl_relaxed(i2c_dev->base + STM32F7_I2C_PECR);
1111
1112         switch (f7_msg->size) {
1113         case I2C_SMBUS_BYTE:
1114         case I2C_SMBUS_BYTE_DATA:
1115                 received_pec = f7_msg->smbus_buf[1];
1116                 break;
1117         case I2C_SMBUS_WORD_DATA:
1118         case I2C_SMBUS_PROC_CALL:
1119                 received_pec = f7_msg->smbus_buf[2];
1120                 break;
1121         case I2C_SMBUS_BLOCK_DATA:
1122         case I2C_SMBUS_BLOCK_PROC_CALL:
1123                 count = f7_msg->smbus_buf[0];
1124                 received_pec = f7_msg->smbus_buf[count];
1125                 break;
1126         default:
1127                 dev_err(i2c_dev->dev, "Unsupported smbus protocol for PEC\n");
1128                 return -EINVAL;
1129         }
1130
1131         if (internal_pec != received_pec) {
1132                 dev_err(i2c_dev->dev, "Bad PEC 0x%02x vs. 0x%02x\n",
1133                         internal_pec, received_pec);
1134                 return -EBADMSG;
1135         }
1136
1137         return 0;
1138 }
1139
1140 static bool stm32f7_i2c_is_addr_match(struct i2c_client *slave, u32 addcode)
1141 {
1142         u32 addr;
1143
1144         if (!slave)
1145                 return false;
1146
1147         if (slave->flags & I2C_CLIENT_TEN) {
1148                 /*
1149                  * For 10-bit addr, addcode = 11110XY with
1150                  * X = Bit 9 of slave address
1151                  * Y = Bit 8 of slave address
1152                  */
1153                 addr = slave->addr >> 8;
1154                 addr |= 0x78;
1155                 if (addr == addcode)
1156                         return true;
1157         } else {
1158                 addr = slave->addr & 0x7f;
1159                 if (addr == addcode)
1160                         return true;
1161         }
1162
1163         return false;
1164 }
1165
1166 static void stm32f7_i2c_slave_start(struct stm32f7_i2c_dev *i2c_dev)
1167 {
1168         struct i2c_client *slave = i2c_dev->slave_running;
1169         void __iomem *base = i2c_dev->base;
1170         u32 mask;
1171         u8 value = 0;
1172
1173         if (i2c_dev->slave_dir) {
1174                 /* Notify i2c slave that new read transfer is starting */
1175                 i2c_slave_event(slave, I2C_SLAVE_READ_REQUESTED, &value);
1176
1177                 /*
1178                  * Disable slave TX config in case of I2C combined message
1179                  * (I2C Write followed by I2C Read)
1180                  */
1181                 mask = STM32F7_I2C_CR2_RELOAD;
1182                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, mask);
1183                 mask = STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1184                        STM32F7_I2C_CR1_TCIE;
1185                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR1, mask);
1186
1187                 /* Enable TX empty, STOP, NACK interrupts */
1188                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1189                         STM32F7_I2C_CR1_TXIE;
1190                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1191
1192                 /* Write 1st data byte */
1193                 writel_relaxed(value, base + STM32F7_I2C_TXDR);
1194         } else {
1195                 /* Notify i2c slave that new write transfer is starting */
1196                 i2c_slave_event(slave, I2C_SLAVE_WRITE_REQUESTED, &value);
1197
1198                 /* Set reload mode to be able to ACK/NACK each received byte */
1199                 mask = STM32F7_I2C_CR2_RELOAD;
1200                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1201
1202                 /*
1203                  * Set STOP, NACK, RX empty and transfer complete interrupts.*
1204                  * Set Slave Byte Control to be able to ACK/NACK each data
1205                  * byte received
1206                  */
1207                 mask =  STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE |
1208                         STM32F7_I2C_CR1_SBC | STM32F7_I2C_CR1_RXIE |
1209                         STM32F7_I2C_CR1_TCIE;
1210                 stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1211         }
1212 }
1213
1214 static void stm32f7_i2c_slave_addr(struct stm32f7_i2c_dev *i2c_dev)
1215 {
1216         void __iomem *base = i2c_dev->base;
1217         u32 isr, addcode, dir, mask;
1218         int i;
1219
1220         isr = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1221         addcode = STM32F7_I2C_ISR_ADDCODE_GET(isr);
1222         dir = isr & STM32F7_I2C_ISR_DIR;
1223
1224         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1225                 if (stm32f7_i2c_is_addr_match(i2c_dev->slave[i], addcode)) {
1226                         i2c_dev->slave_running = i2c_dev->slave[i];
1227                         i2c_dev->slave_dir = dir;
1228
1229                         /* Start I2C slave processing */
1230                         stm32f7_i2c_slave_start(i2c_dev);
1231
1232                         /* Clear ADDR flag */
1233                         mask = STM32F7_I2C_ICR_ADDRCF;
1234                         writel_relaxed(mask, base + STM32F7_I2C_ICR);
1235                         break;
1236                 }
1237         }
1238 }
1239
1240 static int stm32f7_i2c_get_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1241                                     struct i2c_client *slave, int *id)
1242 {
1243         int i;
1244
1245         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1246                 if (i2c_dev->slave[i] == slave) {
1247                         *id = i;
1248                         return 0;
1249                 }
1250         }
1251
1252         dev_err(i2c_dev->dev, "Slave 0x%x not registered\n", slave->addr);
1253
1254         return -ENODEV;
1255 }
1256
1257 static int stm32f7_i2c_get_free_slave_id(struct stm32f7_i2c_dev *i2c_dev,
1258                                          struct i2c_client *slave, int *id)
1259 {
1260         struct device *dev = i2c_dev->dev;
1261         int i;
1262
1263         /*
1264          * slave[0] supports 7-bit and 10-bit slave address
1265          * slave[1] supports 7-bit slave address only
1266          */
1267         for (i = STM32F7_I2C_MAX_SLAVE - 1; i >= 0; i--) {
1268                 if (i == 1 && (slave->flags & I2C_CLIENT_TEN))
1269                         continue;
1270                 if (!i2c_dev->slave[i]) {
1271                         *id = i;
1272                         return 0;
1273                 }
1274         }
1275
1276         dev_err(dev, "Slave 0x%x could not be registered\n", slave->addr);
1277
1278         return -EINVAL;
1279 }
1280
1281 static bool stm32f7_i2c_is_slave_registered(struct stm32f7_i2c_dev *i2c_dev)
1282 {
1283         int i;
1284
1285         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1286                 if (i2c_dev->slave[i])
1287                         return true;
1288         }
1289
1290         return false;
1291 }
1292
1293 static bool stm32f7_i2c_is_slave_busy(struct stm32f7_i2c_dev *i2c_dev)
1294 {
1295         int i, busy;
1296
1297         busy = 0;
1298         for (i = 0; i < STM32F7_I2C_MAX_SLAVE; i++) {
1299                 if (i2c_dev->slave[i])
1300                         busy++;
1301         }
1302
1303         return i == busy;
1304 }
1305
1306 static irqreturn_t stm32f7_i2c_slave_isr_event(struct stm32f7_i2c_dev *i2c_dev)
1307 {
1308         void __iomem *base = i2c_dev->base;
1309         u32 cr2, status, mask;
1310         u8 val;
1311         int ret;
1312
1313         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1314
1315         /* Slave transmitter mode */
1316         if (status & STM32F7_I2C_ISR_TXIS) {
1317                 i2c_slave_event(i2c_dev->slave_running,
1318                                 I2C_SLAVE_READ_PROCESSED,
1319                                 &val);
1320
1321                 /* Write data byte */
1322                 writel_relaxed(val, base + STM32F7_I2C_TXDR);
1323         }
1324
1325         /* Transfer Complete Reload for Slave receiver mode */
1326         if (status & STM32F7_I2C_ISR_TCR || status & STM32F7_I2C_ISR_RXNE) {
1327                 /*
1328                  * Read data byte then set NBYTES to receive next byte or NACK
1329                  * the current received byte
1330                  */
1331                 val = readb_relaxed(i2c_dev->base + STM32F7_I2C_RXDR);
1332                 ret = i2c_slave_event(i2c_dev->slave_running,
1333                                       I2C_SLAVE_WRITE_RECEIVED,
1334                                       &val);
1335                 if (!ret) {
1336                         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
1337                         cr2 |= STM32F7_I2C_CR2_NBYTES(1);
1338                         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
1339                 } else {
1340                         mask = STM32F7_I2C_CR2_NACK;
1341                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1342                 }
1343         }
1344
1345         /* NACK received */
1346         if (status & STM32F7_I2C_ISR_NACKF) {
1347                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1348                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1349         }
1350
1351         /* STOP received */
1352         if (status & STM32F7_I2C_ISR_STOPF) {
1353                 /* Disable interrupts */
1354                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_XFER_IRQ_MASK);
1355
1356                 if (i2c_dev->slave_dir) {
1357                         /*
1358                          * Flush TX buffer in order to not used the byte in
1359                          * TXDR for the next transfer
1360                          */
1361                         mask = STM32F7_I2C_ISR_TXE;
1362                         stm32f7_i2c_set_bits(base + STM32F7_I2C_ISR, mask);
1363                 }
1364
1365                 /* Clear STOP flag */
1366                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1367
1368                 /* Notify i2c slave that a STOP flag has been detected */
1369                 i2c_slave_event(i2c_dev->slave_running, I2C_SLAVE_STOP, &val);
1370
1371                 i2c_dev->slave_running = NULL;
1372         }
1373
1374         /* Address match received */
1375         if (status & STM32F7_I2C_ISR_ADDR)
1376                 stm32f7_i2c_slave_addr(i2c_dev);
1377
1378         return IRQ_HANDLED;
1379 }
1380
1381 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
1382 {
1383         struct stm32f7_i2c_dev *i2c_dev = data;
1384         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1385         struct stm32_i2c_dma *dma = i2c_dev->dma;
1386         void __iomem *base = i2c_dev->base;
1387         u32 status, mask;
1388         int ret = IRQ_HANDLED;
1389
1390         /* Check if the interrupt if for a slave device */
1391         if (!i2c_dev->master_mode) {
1392                 ret = stm32f7_i2c_slave_isr_event(i2c_dev);
1393                 return ret;
1394         }
1395
1396         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1397
1398         /* Tx empty */
1399         if (status & STM32F7_I2C_ISR_TXIS)
1400                 stm32f7_i2c_write_tx_data(i2c_dev);
1401
1402         /* RX not empty */
1403         if (status & STM32F7_I2C_ISR_RXNE)
1404                 stm32f7_i2c_read_rx_data(i2c_dev);
1405
1406         /* NACK received */
1407         if (status & STM32F7_I2C_ISR_NACKF) {
1408                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
1409                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
1410                 if (i2c_dev->use_dma) {
1411                         stm32f7_i2c_disable_dma_req(i2c_dev);
1412                         dmaengine_terminate_all(dma->chan_using);
1413                 }
1414                 f7_msg->result = -ENXIO;
1415         }
1416
1417         /* STOP detection flag */
1418         if (status & STM32F7_I2C_ISR_STOPF) {
1419                 /* Disable interrupts */
1420                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1421                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1422                 else
1423                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1424                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1425
1426                 /* Clear STOP flag */
1427                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
1428
1429                 if (i2c_dev->use_dma && !f7_msg->result) {
1430                         ret = IRQ_WAKE_THREAD;
1431                 } else {
1432                         i2c_dev->master_mode = false;
1433                         complete(&i2c_dev->complete);
1434                 }
1435         }
1436
1437         /* Transfer complete */
1438         if (status & STM32F7_I2C_ISR_TC) {
1439                 if (f7_msg->stop) {
1440                         mask = STM32F7_I2C_CR2_STOP;
1441                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
1442                 } else if (i2c_dev->use_dma && !f7_msg->result) {
1443                         ret = IRQ_WAKE_THREAD;
1444                 } else if (f7_msg->smbus) {
1445                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1446                 } else {
1447                         i2c_dev->msg_id++;
1448                         i2c_dev->msg++;
1449                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1450                 }
1451         }
1452
1453         if (status & STM32F7_I2C_ISR_TCR) {
1454                 if (f7_msg->smbus)
1455                         stm32f7_i2c_smbus_reload(i2c_dev);
1456                 else
1457                         stm32f7_i2c_reload(i2c_dev);
1458         }
1459
1460         return ret;
1461 }
1462
1463 static irqreturn_t stm32f7_i2c_isr_event_thread(int irq, void *data)
1464 {
1465         struct stm32f7_i2c_dev *i2c_dev = data;
1466         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1467         struct stm32_i2c_dma *dma = i2c_dev->dma;
1468         u32 status;
1469         int ret;
1470
1471         /*
1472          * Wait for dma transfer completion before sending next message or
1473          * notity the end of xfer to the client
1474          */
1475         ret = wait_for_completion_timeout(&i2c_dev->dma->dma_complete, HZ);
1476         if (!ret) {
1477                 dev_dbg(i2c_dev->dev, "<%s>: Timed out\n", __func__);
1478                 stm32f7_i2c_disable_dma_req(i2c_dev);
1479                 dmaengine_terminate_all(dma->chan_using);
1480                 f7_msg->result = -ETIMEDOUT;
1481         }
1482
1483         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1484
1485         if (status & STM32F7_I2C_ISR_TC) {
1486                 if (f7_msg->smbus) {
1487                         stm32f7_i2c_smbus_rep_start(i2c_dev);
1488                 } else {
1489                         i2c_dev->msg_id++;
1490                         i2c_dev->msg++;
1491                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
1492                 }
1493         } else {
1494                 i2c_dev->master_mode = false;
1495                 complete(&i2c_dev->complete);
1496         }
1497
1498         return IRQ_HANDLED;
1499 }
1500
1501 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
1502 {
1503         struct stm32f7_i2c_dev *i2c_dev = data;
1504         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1505         void __iomem *base = i2c_dev->base;
1506         struct device *dev = i2c_dev->dev;
1507         struct stm32_i2c_dma *dma = i2c_dev->dma;
1508         u32 status;
1509
1510         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
1511
1512         /* Bus error */
1513         if (status & STM32F7_I2C_ISR_BERR) {
1514                 dev_err(dev, "<%s>: Bus error\n", __func__);
1515                 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
1516                 stm32f7_i2c_release_bus(&i2c_dev->adap);
1517                 f7_msg->result = -EIO;
1518         }
1519
1520         /* Arbitration loss */
1521         if (status & STM32F7_I2C_ISR_ARLO) {
1522                 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
1523                 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
1524                 f7_msg->result = -EAGAIN;
1525         }
1526
1527         if (status & STM32F7_I2C_ISR_PECERR) {
1528                 dev_err(dev, "<%s>: PEC error in reception\n", __func__);
1529                 writel_relaxed(STM32F7_I2C_ICR_PECCF, base + STM32F7_I2C_ICR);
1530                 f7_msg->result = -EINVAL;
1531         }
1532
1533         if (!i2c_dev->slave_running) {
1534                 u32 mask;
1535                 /* Disable interrupts */
1536                 if (stm32f7_i2c_is_slave_registered(i2c_dev))
1537                         mask = STM32F7_I2C_XFER_IRQ_MASK;
1538                 else
1539                         mask = STM32F7_I2C_ALL_IRQ_MASK;
1540                 stm32f7_i2c_disable_irq(i2c_dev, mask);
1541         }
1542
1543         /* Disable dma */
1544         if (i2c_dev->use_dma) {
1545                 stm32f7_i2c_disable_dma_req(i2c_dev);
1546                 dmaengine_terminate_all(dma->chan_using);
1547         }
1548
1549         i2c_dev->master_mode = false;
1550         complete(&i2c_dev->complete);
1551
1552         return IRQ_HANDLED;
1553 }
1554
1555 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
1556                             struct i2c_msg msgs[], int num)
1557 {
1558         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
1559         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1560         struct stm32_i2c_dma *dma = i2c_dev->dma;
1561         unsigned long time_left;
1562         int ret;
1563
1564         i2c_dev->msg = msgs;
1565         i2c_dev->msg_num = num;
1566         i2c_dev->msg_id = 0;
1567         f7_msg->smbus = false;
1568
1569         ret = clk_enable(i2c_dev->clk);
1570         if (ret) {
1571                 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1572                 return ret;
1573         }
1574
1575         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1576         if (ret)
1577                 goto clk_free;
1578
1579         stm32f7_i2c_xfer_msg(i2c_dev, msgs);
1580
1581         time_left = wait_for_completion_timeout(&i2c_dev->complete,
1582                                                 i2c_dev->adap.timeout);
1583         ret = f7_msg->result;
1584
1585         if (!time_left) {
1586                 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
1587                         i2c_dev->msg->addr);
1588                 if (i2c_dev->use_dma)
1589                         dmaengine_terminate_all(dma->chan_using);
1590                 stm32f7_i2c_wait_free_bus(i2c_dev);
1591                 ret = -ETIMEDOUT;
1592         }
1593
1594 clk_free:
1595         clk_disable(i2c_dev->clk);
1596
1597         return (ret < 0) ? ret : num;
1598 }
1599
1600 static int stm32f7_i2c_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
1601                                   unsigned short flags, char read_write,
1602                                   u8 command, int size,
1603                                   union i2c_smbus_data *data)
1604 {
1605         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(adapter);
1606         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
1607         struct stm32_i2c_dma *dma = i2c_dev->dma;
1608         struct device *dev = i2c_dev->dev;
1609         unsigned long timeout;
1610         int i, ret;
1611
1612         f7_msg->addr = addr;
1613         f7_msg->size = size;
1614         f7_msg->read_write = read_write;
1615         f7_msg->smbus = true;
1616
1617         ret = clk_enable(i2c_dev->clk);
1618         if (ret) {
1619                 dev_err(i2c_dev->dev, "Failed to enable clock\n");
1620                 return ret;
1621         }
1622
1623         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
1624         if (ret)
1625                 goto clk_free;
1626
1627         ret = stm32f7_i2c_smbus_xfer_msg(i2c_dev, flags, command, data);
1628         if (ret)
1629                 goto clk_free;
1630
1631         timeout = wait_for_completion_timeout(&i2c_dev->complete,
1632                                               i2c_dev->adap.timeout);
1633         ret = f7_msg->result;
1634         if (ret)
1635                 goto clk_free;
1636
1637         if (!timeout) {
1638                 dev_dbg(dev, "Access to slave 0x%x timed out\n", f7_msg->addr);
1639                 if (i2c_dev->use_dma)
1640                         dmaengine_terminate_all(dma->chan_using);
1641                 stm32f7_i2c_wait_free_bus(i2c_dev);
1642                 ret = -ETIMEDOUT;
1643                 goto clk_free;
1644         }
1645
1646         /* Check PEC */
1647         if ((flags & I2C_CLIENT_PEC) && size != I2C_SMBUS_QUICK && read_write) {
1648                 ret = stm32f7_i2c_smbus_check_pec(i2c_dev);
1649                 if (ret)
1650                         goto clk_free;
1651         }
1652
1653         if (read_write && size != I2C_SMBUS_QUICK) {
1654                 switch (size) {
1655                 case I2C_SMBUS_BYTE:
1656                 case I2C_SMBUS_BYTE_DATA:
1657                         data->byte = f7_msg->smbus_buf[0];
1658                 break;
1659                 case I2C_SMBUS_WORD_DATA:
1660                 case I2C_SMBUS_PROC_CALL:
1661                         data->word = f7_msg->smbus_buf[0] |
1662                                 (f7_msg->smbus_buf[1] << 8);
1663                 break;
1664                 case I2C_SMBUS_BLOCK_DATA:
1665                 case I2C_SMBUS_BLOCK_PROC_CALL:
1666                 for (i = 0; i <= f7_msg->smbus_buf[0]; i++)
1667                         data->block[i] = f7_msg->smbus_buf[i];
1668                 break;
1669                 default:
1670                         dev_err(dev, "Unsupported smbus transaction\n");
1671                         ret = -EINVAL;
1672                 }
1673         }
1674
1675 clk_free:
1676         clk_disable(i2c_dev->clk);
1677         return ret;
1678 }
1679
1680 static int stm32f7_i2c_reg_slave(struct i2c_client *slave)
1681 {
1682         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1683         void __iomem *base = i2c_dev->base;
1684         struct device *dev = i2c_dev->dev;
1685         u32 oar1, oar2, mask;
1686         int id, ret;
1687
1688         if (slave->flags & I2C_CLIENT_PEC) {
1689                 dev_err(dev, "SMBus PEC not supported in slave mode\n");
1690                 return -EINVAL;
1691         }
1692
1693         if (stm32f7_i2c_is_slave_busy(i2c_dev)) {
1694                 dev_err(dev, "Too much slave registered\n");
1695                 return -EBUSY;
1696         }
1697
1698         ret = stm32f7_i2c_get_free_slave_id(i2c_dev, slave, &id);
1699         if (ret)
1700                 return ret;
1701
1702         if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1703                 ret = clk_enable(i2c_dev->clk);
1704                 if (ret) {
1705                         dev_err(dev, "Failed to enable clock\n");
1706                         return ret;
1707                 }
1708         }
1709
1710         if (id == 0) {
1711                 /* Configure Own Address 1 */
1712                 oar1 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR1);
1713                 oar1 &= ~STM32F7_I2C_OAR1_MASK;
1714                 if (slave->flags & I2C_CLIENT_TEN) {
1715                         oar1 |= STM32F7_I2C_OAR1_OA1_10(slave->addr);
1716                         oar1 |= STM32F7_I2C_OAR1_OA1MODE;
1717                 } else {
1718                         oar1 |= STM32F7_I2C_OAR1_OA1_7(slave->addr);
1719                 }
1720                 oar1 |= STM32F7_I2C_OAR1_OA1EN;
1721                 i2c_dev->slave[id] = slave;
1722                 writel_relaxed(oar1, i2c_dev->base + STM32F7_I2C_OAR1);
1723         } else if (id == 1) {
1724                 /* Configure Own Address 2 */
1725                 oar2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_OAR2);
1726                 oar2 &= ~STM32F7_I2C_OAR2_MASK;
1727                 if (slave->flags & I2C_CLIENT_TEN) {
1728                         ret = -EOPNOTSUPP;
1729                         goto exit;
1730                 }
1731
1732                 oar2 |= STM32F7_I2C_OAR2_OA2_7(slave->addr);
1733                 oar2 |= STM32F7_I2C_OAR2_OA2EN;
1734                 i2c_dev->slave[id] = slave;
1735                 writel_relaxed(oar2, i2c_dev->base + STM32F7_I2C_OAR2);
1736         } else {
1737                 ret = -ENODEV;
1738                 goto exit;
1739         }
1740
1741         /* Enable ACK */
1742         stm32f7_i2c_clr_bits(base + STM32F7_I2C_CR2, STM32F7_I2C_CR2_NACK);
1743
1744         /* Enable Address match interrupt, error interrupt and enable I2C  */
1745         mask = STM32F7_I2C_CR1_ADDRIE | STM32F7_I2C_CR1_ERRIE |
1746                 STM32F7_I2C_CR1_PE;
1747         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR1, mask);
1748
1749         return 0;
1750
1751 exit:
1752         if (!(stm32f7_i2c_is_slave_registered(i2c_dev)))
1753                 clk_disable(i2c_dev->clk);
1754
1755         return ret;
1756 }
1757
1758 static int stm32f7_i2c_unreg_slave(struct i2c_client *slave)
1759 {
1760         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(slave->adapter);
1761         void __iomem *base = i2c_dev->base;
1762         u32 mask;
1763         int id, ret;
1764
1765         ret = stm32f7_i2c_get_slave_id(i2c_dev, slave, &id);
1766         if (ret)
1767                 return ret;
1768
1769         WARN_ON(!i2c_dev->slave[id]);
1770
1771         if (id == 0) {
1772                 mask = STM32F7_I2C_OAR1_OA1EN;
1773                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR1, mask);
1774         } else {
1775                 mask = STM32F7_I2C_OAR2_OA2EN;
1776                 stm32f7_i2c_clr_bits(base + STM32F7_I2C_OAR2, mask);
1777         }
1778
1779         i2c_dev->slave[id] = NULL;
1780
1781         if (!(stm32f7_i2c_is_slave_registered(i2c_dev))) {
1782                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
1783                 clk_disable(i2c_dev->clk);
1784         }
1785
1786         return 0;
1787 }
1788
1789 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
1790 {
1791         return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SLAVE |
1792                 I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
1793                 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
1794                 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1795                 I2C_FUNC_SMBUS_PROC_CALL | I2C_FUNC_SMBUS_PEC;
1796 }
1797
1798 static struct i2c_algorithm stm32f7_i2c_algo = {
1799         .master_xfer = stm32f7_i2c_xfer,
1800         .smbus_xfer = stm32f7_i2c_smbus_xfer,
1801         .functionality = stm32f7_i2c_func,
1802         .reg_slave = stm32f7_i2c_reg_slave,
1803         .unreg_slave = stm32f7_i2c_unreg_slave,
1804 };
1805
1806 static int stm32f7_i2c_probe(struct platform_device *pdev)
1807 {
1808         struct stm32f7_i2c_dev *i2c_dev;
1809         const struct stm32f7_i2c_setup *setup;
1810         struct resource *res;
1811         u32 clk_rate, rise_time, fall_time;
1812         struct i2c_adapter *adap;
1813         struct reset_control *rst;
1814         dma_addr_t phy_addr;
1815         int irq_error, irq_event, ret;
1816
1817         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
1818         if (!i2c_dev)
1819                 return -ENOMEM;
1820
1821         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1822         i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
1823         if (IS_ERR(i2c_dev->base))
1824                 return PTR_ERR(i2c_dev->base);
1825         phy_addr = (dma_addr_t)res->start;
1826
1827         irq_event = platform_get_irq(pdev, 0);
1828         if (irq_event <= 0) {
1829                 if (irq_event != -EPROBE_DEFER)
1830                         dev_err(&pdev->dev, "Failed to get IRQ event: %d\n",
1831                                 irq_event);
1832                 return irq_event ? : -ENOENT;
1833         }
1834
1835         irq_error = platform_get_irq(pdev, 1);
1836         if (irq_error <= 0) {
1837                 if (irq_error != -EPROBE_DEFER)
1838                         dev_err(&pdev->dev, "Failed to get IRQ error: %d\n",
1839                                 irq_error);
1840                 return irq_error ? : -ENOENT;
1841         }
1842
1843         i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
1844         if (IS_ERR(i2c_dev->clk)) {
1845                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
1846                 return PTR_ERR(i2c_dev->clk);
1847         }
1848         ret = clk_prepare_enable(i2c_dev->clk);
1849         if (ret) {
1850                 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
1851                 return ret;
1852         }
1853
1854         i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1855         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
1856                                        &clk_rate);
1857         if (!ret && clk_rate >= 1000000)
1858                 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
1859         else if (!ret && clk_rate >= 400000)
1860                 i2c_dev->speed = STM32_I2C_SPEED_FAST;
1861         else if (!ret && clk_rate >= 100000)
1862                 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
1863
1864         rst = devm_reset_control_get(&pdev->dev, NULL);
1865         if (IS_ERR(rst)) {
1866                 dev_err(&pdev->dev, "Error: Missing controller reset\n");
1867                 ret = PTR_ERR(rst);
1868                 goto clk_free;
1869         }
1870         reset_control_assert(rst);
1871         udelay(2);
1872         reset_control_deassert(rst);
1873
1874         i2c_dev->dev = &pdev->dev;
1875
1876         ret = devm_request_threaded_irq(&pdev->dev, irq_event,
1877                                         stm32f7_i2c_isr_event,
1878                                         stm32f7_i2c_isr_event_thread,
1879                                         IRQF_ONESHOT,
1880                                         pdev->name, i2c_dev);
1881         if (ret) {
1882                 dev_err(&pdev->dev, "Failed to request irq event %i\n",
1883                         irq_event);
1884                 goto clk_free;
1885         }
1886
1887         ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
1888                                pdev->name, i2c_dev);
1889         if (ret) {
1890                 dev_err(&pdev->dev, "Failed to request irq error %i\n",
1891                         irq_error);
1892                 goto clk_free;
1893         }
1894
1895         setup = of_device_get_match_data(&pdev->dev);
1896         if (!setup) {
1897                 dev_err(&pdev->dev, "Can't get device data\n");
1898                 ret = -ENODEV;
1899                 goto clk_free;
1900         }
1901         i2c_dev->setup = *setup;
1902
1903         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
1904                                        &rise_time);
1905         if (!ret)
1906                 i2c_dev->setup.rise_time = rise_time;
1907
1908         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
1909                                        &fall_time);
1910         if (!ret)
1911                 i2c_dev->setup.fall_time = fall_time;
1912
1913         ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
1914         if (ret)
1915                 goto clk_free;
1916
1917         stm32f7_i2c_hw_config(i2c_dev);
1918
1919         adap = &i2c_dev->adap;
1920         i2c_set_adapdata(adap, i2c_dev);
1921         snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
1922                  &res->start);
1923         adap->owner = THIS_MODULE;
1924         adap->timeout = 2 * HZ;
1925         adap->retries = 3;
1926         adap->algo = &stm32f7_i2c_algo;
1927         adap->dev.parent = &pdev->dev;
1928         adap->dev.of_node = pdev->dev.of_node;
1929
1930         init_completion(&i2c_dev->complete);
1931
1932         /* Init DMA config if supported */
1933         i2c_dev->dma = stm32_i2c_dma_request(i2c_dev->dev, phy_addr,
1934                                              STM32F7_I2C_TXDR,
1935                                              STM32F7_I2C_RXDR);
1936         if (PTR_ERR(i2c_dev->dma) == -ENODEV)
1937                 i2c_dev->dma = NULL;
1938         else if (IS_ERR(i2c_dev->dma)) {
1939                 ret = PTR_ERR(i2c_dev->dma);
1940                 if (ret != -EPROBE_DEFER)
1941                         dev_err(&pdev->dev,
1942                                 "Failed to request dma error %i\n", ret);
1943                 goto clk_free;
1944         }
1945
1946         ret = i2c_add_adapter(adap);
1947         if (ret)
1948                 goto clk_free;
1949
1950         platform_set_drvdata(pdev, i2c_dev);
1951
1952         clk_disable(i2c_dev->clk);
1953
1954         dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
1955
1956         return 0;
1957
1958 clk_free:
1959         clk_disable_unprepare(i2c_dev->clk);
1960
1961         return ret;
1962 }
1963
1964 static int stm32f7_i2c_remove(struct platform_device *pdev)
1965 {
1966         struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
1967
1968         if (i2c_dev->dma) {
1969                 stm32_i2c_dma_free(i2c_dev->dma);
1970                 i2c_dev->dma = NULL;
1971         }
1972
1973         i2c_del_adapter(&i2c_dev->adap);
1974
1975         clk_unprepare(i2c_dev->clk);
1976
1977         return 0;
1978 }
1979
1980 static const struct of_device_id stm32f7_i2c_match[] = {
1981         { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
1982         {},
1983 };
1984 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
1985
1986 static struct platform_driver stm32f7_i2c_driver = {
1987         .driver = {
1988                 .name = "stm32f7-i2c",
1989                 .of_match_table = stm32f7_i2c_match,
1990         },
1991         .probe = stm32f7_i2c_probe,
1992         .remove = stm32f7_i2c_remove,
1993 };
1994
1995 module_platform_driver(stm32f7_i2c_driver);
1996
1997 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
1998 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
1999 MODULE_LICENSE("GPL v2");