drivers/i2c/busses/i2c-stm32f7.c

   1 /*
   2  * Driver for STMicroelectronics STM32F7 I2C controller
   3  *
   4  * This I2C controller is described in the STM32F75xxx and STM32F74xxx Soc
   5  * reference manual.
   6  * Please see below a link to the documentation:
   7  * http://www.st.com/resource/en/reference_manual/dm00124865.pdf
   8  *
   9  * Copyright (C) M'boumba Cedric Madianga 2017
  10  * Author: M'boumba Cedric Madianga <cedric.madianga@gmail.com>
  11  *
  12  * This driver is based on i2c-stm32f4.c
  13  *
  14  * License terms:  GNU General Public License (GPL), version 2
  15  */
  16 #include <linux/clk.h>
  17 #include <linux/delay.h>
  18 #include <linux/err.h>
  19 #include <linux/i2c.h>
  20 #include <linux/interrupt.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/module.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_irq.h>
  27 #include <linux/of_platform.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/reset.h>
  30 #include <linux/slab.h>
  31
  32 #include "i2c-stm32.h"
  33
  34 /* STM32F7 I2C registers */
  35 #define STM32F7_I2C_CR1                         0x00
  36 #define STM32F7_I2C_CR2                         0x04
  37 #define STM32F7_I2C_TIMINGR                     0x10
  38 #define STM32F7_I2C_ISR                         0x18
  39 #define STM32F7_I2C_ICR                         0x1C
  40 #define STM32F7_I2C_RXDR                        0x24
  41 #define STM32F7_I2C_TXDR                        0x28
  42
  43 /* STM32F7 I2C control 1 */
  44 #define STM32F7_I2C_CR1_ANFOFF                  BIT(12)
  45 #define STM32F7_I2C_CR1_DNF_MASK                GENMASK(11, 8)
  46 #define STM32F7_I2C_CR1_DNF(n)                  (((n) & 0xf) << 8)
  47 #define STM32F7_I2C_CR1_ERRIE                   BIT(7)
  48 #define STM32F7_I2C_CR1_TCIE                    BIT(6)
  49 #define STM32F7_I2C_CR1_STOPIE                  BIT(5)
  50 #define STM32F7_I2C_CR1_NACKIE                  BIT(4)
  51 #define STM32F7_I2C_CR1_ADDRIE                  BIT(3)
  52 #define STM32F7_I2C_CR1_RXIE                    BIT(2)
  53 #define STM32F7_I2C_CR1_TXIE                    BIT(1)
  54 #define STM32F7_I2C_CR1_PE                      BIT(0)
  55 #define STM32F7_I2C_ALL_IRQ_MASK                (STM32F7_I2C_CR1_ERRIE \
  56                                                 | STM32F7_I2C_CR1_TCIE \
  57                                                 | STM32F7_I2C_CR1_STOPIE \
  58                                                 | STM32F7_I2C_CR1_NACKIE \
  59                                                 | STM32F7_I2C_CR1_RXIE \
  60                                                 | STM32F7_I2C_CR1_TXIE)
  61
  62 /* STM32F7 I2C control 2 */
  63 #define STM32F7_I2C_CR2_RELOAD                  BIT(24)
  64 #define STM32F7_I2C_CR2_NBYTES_MASK             GENMASK(23, 16)
  65 #define STM32F7_I2C_CR2_NBYTES(n)               (((n) & 0xff) << 16)
  66 #define STM32F7_I2C_CR2_NACK                    BIT(15)
  67 #define STM32F7_I2C_CR2_STOP                    BIT(14)
  68 #define STM32F7_I2C_CR2_START                   BIT(13)
  69 #define STM32F7_I2C_CR2_RD_WRN                  BIT(10)
  70 #define STM32F7_I2C_CR2_SADD7_MASK              GENMASK(7, 1)
  71 #define STM32F7_I2C_CR2_SADD7(n)                (((n) & 0x7f) << 1)
  72
  73 /* STM32F7 I2C Interrupt Status */
  74 #define STM32F7_I2C_ISR_BUSY                    BIT(15)
  75 #define STM32F7_I2C_ISR_ARLO                    BIT(9)
  76 #define STM32F7_I2C_ISR_BERR                    BIT(8)
  77 #define STM32F7_I2C_ISR_TCR                     BIT(7)
  78 #define STM32F7_I2C_ISR_TC                      BIT(6)
  79 #define STM32F7_I2C_ISR_STOPF                   BIT(5)
  80 #define STM32F7_I2C_ISR_NACKF                   BIT(4)
  81 #define STM32F7_I2C_ISR_RXNE                    BIT(2)
  82 #define STM32F7_I2C_ISR_TXIS                    BIT(1)
  83
  84 /* STM32F7 I2C Interrupt Clear */
  85 #define STM32F7_I2C_ICR_ARLOCF                  BIT(9)
  86 #define STM32F7_I2C_ICR_BERRCF                  BIT(8)
  87 #define STM32F7_I2C_ICR_STOPCF                  BIT(5)
  88 #define STM32F7_I2C_ICR_NACKCF                  BIT(4)
  89
  90 /* STM32F7 I2C Timing */
  91 #define STM32F7_I2C_TIMINGR_PRESC(n)            (((n) & 0xf) << 28)
  92 #define STM32F7_I2C_TIMINGR_SCLDEL(n)           (((n) & 0xf) << 20)
  93 #define STM32F7_I2C_TIMINGR_SDADEL(n)           (((n) & 0xf) << 16)
  94 #define STM32F7_I2C_TIMINGR_SCLH(n)             (((n) & 0xff) << 8)
  95 #define STM32F7_I2C_TIMINGR_SCLL(n)             ((n) & 0xff)
  96
  97 #define STM32F7_I2C_MAX_LEN                     0xff
  98
  99 #define STM32F7_I2C_DNF_DEFAULT                 0
 100 #define STM32F7_I2C_DNF_MAX                     15
 101
 102 #define STM32F7_I2C_ANALOG_FILTER_ENABLE        1
 103 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MIN     50      /* ns */
 104 #define STM32F7_I2C_ANALOG_FILTER_DELAY_MAX     260     /* ns */
 105
 106 #define STM32F7_I2C_RISE_TIME_DEFAULT           25      /* ns */
 107 #define STM32F7_I2C_FALL_TIME_DEFAULT           10      /* ns */
 108
 109 #define STM32F7_PRESC_MAX                       BIT(4)
 110 #define STM32F7_SCLDEL_MAX                      BIT(4)
 111 #define STM32F7_SDADEL_MAX                      BIT(4)
 112 #define STM32F7_SCLH_MAX                        BIT(8)
 113 #define STM32F7_SCLL_MAX                        BIT(8)
 114
 115 /**
 116  * struct stm32f7_i2c_spec - private i2c specification timing
 117  * @rate: I2C bus speed (Hz)
 118  * @rate_min: 80% of I2C bus speed (Hz)
 119  * @rate_max: 100% of I2C bus speed (Hz)
 120  * @fall_max: Max fall time of both SDA and SCL signals (ns)
 121  * @rise_max: Max rise time of both SDA and SCL signals (ns)
 122  * @hddat_min: Min data hold time (ns)
 123  * @vddat_max: Max data valid time (ns)
 124  * @sudat_min: Min data setup time (ns)
 125  * @l_min: Min low period of the SCL clock (ns)
 126  * @h_min: Min high period of the SCL clock (ns)
 127  */
 128 struct stm32f7_i2c_spec {
 129         u32 rate;
 130         u32 rate_min;
 131         u32 rate_max;
 132         u32 fall_max;
 133         u32 rise_max;
 134         u32 hddat_min;
 135         u32 vddat_max;
 136         u32 sudat_min;
 137         u32 l_min;
 138         u32 h_min;
 139 };
 140
 141 /**
 142  * struct stm32f7_i2c_setup - private I2C timing setup parameters
 143  * @speed: I2C speed mode (standard, Fast Plus)
 144  * @speed_freq: I2C speed frequency  (Hz)
 145  * @clock_src: I2C clock source frequency (Hz)
 146  * @rise_time: Rise time (ns)
 147  * @fall_time: Fall time (ns)
 148  * @dnf: Digital filter coefficient (0-16)
 149  * @analog_filter: Analog filter delay (On/Off)
 150  */
 151 struct stm32f7_i2c_setup {
 152         enum stm32_i2c_speed speed;
 153         u32 speed_freq;
 154         u32 clock_src;
 155         u32 rise_time;
 156         u32 fall_time;
 157         u8 dnf;
 158         bool analog_filter;
 159 };
 160
 161 /**
 162  * struct stm32f7_i2c_timings - private I2C output parameters
 163  * @prec: Prescaler value
 164  * @scldel: Data setup time
 165  * @sdadel: Data hold time
 166  * @sclh: SCL high period (master mode)
 167  * @sclh: SCL low period (master mode)
 168  */
 169 struct stm32f7_i2c_timings {
 170         struct list_head node;
 171         u8 presc;
 172         u8 scldel;
 173         u8 sdadel;
 174         u8 sclh;
 175         u8 scll;
 176 };
 177
 178 /**
 179  * struct stm32f7_i2c_msg - client specific data
 180  * @addr: 8-bit slave addr, including r/w bit
 181  * @count: number of bytes to be transferred
 182  * @buf: data buffer
 183  * @result: result of the transfer
 184  * @stop: last I2C msg to be sent, i.e. STOP to be generated
 185  */
 186 struct stm32f7_i2c_msg {
 187         u8 addr;
 188         u32 count;
 189         u8 *buf;
 190         int result;
 191         bool stop;
 192 };
 193
 194 /**
 195  * struct stm32f7_i2c_dev - private data of the controller
 196  * @adap: I2C adapter for this controller
 197  * @dev: device for this controller
 198  * @base: virtual memory area
 199  * @complete: completion of I2C message
 200  * @clk: hw i2c clock
 201  * @speed: I2C clock frequency of the controller. Standard, Fast or Fast+
 202  * @msg: Pointer to data to be written
 203  * @msg_num: number of I2C messages to be executed
 204  * @msg_id: message identifiant
 205  * @f7_msg: customized i2c msg for driver usage
 206  * @setup: I2C timing input setup
 207  * @timing: I2C computed timings
 208  */
 209 struct stm32f7_i2c_dev {
 210         struct i2c_adapter adap;
 211         struct device *dev;
 212         void __iomem *base;
 213         struct completion complete;
 214         struct clk *clk;
 215         int speed;
 216         struct i2c_msg *msg;
 217         unsigned int msg_num;
 218         unsigned int msg_id;
 219         struct stm32f7_i2c_msg f7_msg;
 220         struct stm32f7_i2c_setup setup;
 221         struct stm32f7_i2c_timings timing;
 222 };
 223
 224 /*
 225  * All these values are coming from I2C Specification, Version 6.0, 4th of
 226  * April 2014.
 227  *
 228  * Table10. Characteristics of the SDA and SCL bus lines for Standard, Fast,
 229  * and Fast-mode Plus I2C-bus devices
 230  */
 231 static struct stm32f7_i2c_spec i2c_specs[] = {
 232         [STM32_I2C_SPEED_STANDARD] = {
 233                 .rate = 100000,
 234                 .rate_min = 80000,
 235                 .rate_max = 100000,
 236                 .fall_max = 300,
 237                 .rise_max = 1000,
 238                 .hddat_min = 0,
 239                 .vddat_max = 3450,
 240                 .sudat_min = 250,
 241                 .l_min = 4700,
 242                 .h_min = 4000,
 243         },
 244         [STM32_I2C_SPEED_FAST] = {
 245                 .rate = 400000,
 246                 .rate_min = 320000,
 247                 .rate_max = 400000,
 248                 .fall_max = 300,
 249                 .rise_max = 300,
 250                 .hddat_min = 0,
 251                 .vddat_max = 900,
 252                 .sudat_min = 100,
 253                 .l_min = 1300,
 254                 .h_min = 600,
 255         },
 256         [STM32_I2C_SPEED_FAST_PLUS] = {
 257                 .rate = 1000000,
 258                 .rate_min = 800000,
 259                 .rate_max = 1000000,
 260                 .fall_max = 100,
 261                 .rise_max = 120,
 262                 .hddat_min = 0,
 263                 .vddat_max = 450,
 264                 .sudat_min = 50,
 265                 .l_min = 500,
 266                 .h_min = 260,
 267         },
 268 };
 269
 270 static const struct stm32f7_i2c_setup stm32f7_setup = {
 271         .rise_time = STM32F7_I2C_RISE_TIME_DEFAULT,
 272         .fall_time = STM32F7_I2C_FALL_TIME_DEFAULT,
 273         .dnf = STM32F7_I2C_DNF_DEFAULT,
 274         .analog_filter = STM32F7_I2C_ANALOG_FILTER_ENABLE,
 275 };
 276
 277 static inline void stm32f7_i2c_set_bits(void __iomem *reg, u32 mask)
 278 {
 279         writel_relaxed(readl_relaxed(reg) | mask, reg);
 280 }
 281
 282 static inline void stm32f7_i2c_clr_bits(void __iomem *reg, u32 mask)
 283 {
 284         writel_relaxed(readl_relaxed(reg) & ~mask, reg);
 285 }
 286
 287 static int stm32f7_i2c_compute_timing(struct stm32f7_i2c_dev *i2c_dev,
 288                                       struct stm32f7_i2c_setup *setup,
 289                                       struct stm32f7_i2c_timings *output)
 290 {
 291         u32 p_prev = STM32F7_PRESC_MAX;
 292         u32 i2cclk = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 293                                        setup->clock_src);
 294         u32 i2cbus = DIV_ROUND_CLOSEST(NSEC_PER_SEC,
 295                                        setup->speed_freq);
 296         u32 clk_error_prev = i2cbus;
 297         u32 tsync;
 298         u32 af_delay_min, af_delay_max;
 299         u32 dnf_delay;
 300         u32 clk_min, clk_max;
 301         int sdadel_min, sdadel_max;
 302         int scldel_min;
 303         struct stm32f7_i2c_timings *v, *_v, *s;
 304         struct list_head solutions;
 305         u16 p, l, a, h;
 306         int ret = 0;
 307
 308         if (setup->speed >= STM32_I2C_SPEED_END) {
 309                 dev_err(i2c_dev->dev, "speed out of bound {%d/%d}\n",
 310                         setup->speed, STM32_I2C_SPEED_END - 1);
 311                 return -EINVAL;
 312         }
 313
 314         if ((setup->rise_time > i2c_specs[setup->speed].rise_max) ||
 315             (setup->fall_time > i2c_specs[setup->speed].fall_max)) {
 316                 dev_err(i2c_dev->dev,
 317                         "timings out of bound Rise{%d>%d}/Fall{%d>%d}\n",
 318                         setup->rise_time, i2c_specs[setup->speed].rise_max,
 319                         setup->fall_time, i2c_specs[setup->speed].fall_max);
 320                 return -EINVAL;
 321         }
 322
 323         if (setup->dnf > STM32F7_I2C_DNF_MAX) {
 324                 dev_err(i2c_dev->dev,
 325                         "DNF out of bound %d/%d\n",
 326                         setup->dnf, STM32F7_I2C_DNF_MAX);
 327                 return -EINVAL;
 328         }
 329
 330         if (setup->speed_freq > i2c_specs[setup->speed].rate) {
 331                 dev_err(i2c_dev->dev, "ERROR: Freq {%d/%d}\n",
 332                         setup->speed_freq, i2c_specs[setup->speed].rate);
 333                 return -EINVAL;
 334         }
 335
 336         /*  Analog and Digital Filters */
 337         af_delay_min =
 338                 (setup->analog_filter ?
 339                  STM32F7_I2C_ANALOG_FILTER_DELAY_MIN : 0);
 340         af_delay_max =
 341                 (setup->analog_filter ?
 342                  STM32F7_I2C_ANALOG_FILTER_DELAY_MAX : 0);
 343         dnf_delay = setup->dnf * i2cclk;
 344
 345         sdadel_min = i2c_specs[setup->speed].hddat_min + setup->fall_time -
 346                 af_delay_min - (setup->dnf + 3) * i2cclk;
 347
 348         sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time -
 349                 af_delay_max - (setup->dnf + 4) * i2cclk;
 350
 351         scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min;
 352
 353         if (sdadel_min < 0)
 354                 sdadel_min = 0;
 355         if (sdadel_max < 0)
 356                 sdadel_max = 0;
 357
 358         dev_dbg(i2c_dev->dev, "SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n",
 359                 sdadel_min, sdadel_max, scldel_min);
 360
 361         INIT_LIST_HEAD(&solutions);
 362         /* Compute possible values for PRESC, SCLDEL and SDADEL */
 363         for (p = 0; p < STM32F7_PRESC_MAX; p++) {
 364                 for (l = 0; l < STM32F7_SCLDEL_MAX; l++) {
 365                         u32 scldel = (l + 1) * (p + 1) * i2cclk;
 366
 367                         if (scldel < scldel_min)
 368                                 continue;
 369
 370                         for (a = 0; a < STM32F7_SDADEL_MAX; a++) {
 371                                 u32 sdadel = (a * (p + 1) + 1) * i2cclk;
 372
 373                                 if (((sdadel >= sdadel_min) &&
 374                                      (sdadel <= sdadel_max)) &&
 375                                     (p != p_prev)) {
 376                                         v = kmalloc(sizeof(*v), GFP_KERNEL);
 377                                         if (!v) {
 378                                                 ret = -ENOMEM;
 379                                                 goto exit;
 380                                         }
 381
 382                                         v->presc = p;
 383                                         v->scldel = l;
 384                                         v->sdadel = a;
 385                                         p_prev = p;
 386
 387                                         list_add_tail(&v->node,
 388                                                       &solutions);
 389                                 }
 390                         }
 391                 }
 392         }
 393
 394         if (list_empty(&solutions)) {
 395                 dev_err(i2c_dev->dev, "no Prescaler solution\n");
 396                 ret = -EPERM;
 397                 goto exit;
 398         }
 399
 400         tsync = af_delay_min + dnf_delay + (2 * i2cclk);
 401         s = NULL;
 402         clk_max = NSEC_PER_SEC / i2c_specs[setup->speed].rate_min;
 403         clk_min = NSEC_PER_SEC / i2c_specs[setup->speed].rate_max;
 404
 405         /*
 406          * Among Prescaler possibilities discovered above figures out SCL Low
 407          * and High Period. Provided:
 408          * - SCL Low Period has to be higher than SCL Clock Low Period
 409          *   defined by I2C Specification. I2C Clock has to be lower than
 410          *   (SCL Low Period - Analog/Digital filters) / 4.
 411          * - SCL High Period has to be lower than SCL Clock High Period
 412          *   defined by I2C Specification
 413          * - I2C Clock has to be lower than SCL High Period
 414          */
 415         list_for_each_entry(v, &solutions, node) {
 416                 u32 prescaler = (v->presc + 1) * i2cclk;
 417
 418                 for (l = 0; l < STM32F7_SCLL_MAX; l++) {
 419                         u32 tscl_l = (l + 1) * prescaler + tsync;
 420
 421                         if ((tscl_l < i2c_specs[setup->speed].l_min) ||
 422                             (i2cclk >=
 423                              ((tscl_l - af_delay_min - dnf_delay) / 4))) {
 424                                 continue;
 425                         }
 426
 427                         for (h = 0; h < STM32F7_SCLH_MAX; h++) {
 428                                 u32 tscl_h = (h + 1) * prescaler + tsync;
 429                                 u32 tscl = tscl_l + tscl_h +
 430                                         setup->rise_time + setup->fall_time;
 431
 432                                 if ((tscl >= clk_min) && (tscl <= clk_max) &&
 433                                     (tscl_h >= i2c_specs[setup->speed].h_min) &&
 434                                     (i2cclk < tscl_h)) {
 435                                         int clk_error = tscl - i2cbus;
 436
 437                                         if (clk_error < 0)
 438                                                 clk_error = -clk_error;
 439
 440                                         if (clk_error < clk_error_prev) {
 441                                                 clk_error_prev = clk_error;
 442                                                 v->scll = l;
 443                                                 v->sclh = h;
 444                                                 s = v;
 445                                         }
 446                                 }
 447                         }
 448                 }
 449         }
 450
 451         if (!s) {
 452                 dev_err(i2c_dev->dev, "no solution at all\n");
 453                 ret = -EPERM;
 454                 goto exit;
 455         }
 456
 457         output->presc = s->presc;
 458         output->scldel = s->scldel;
 459         output->sdadel = s->sdadel;
 460         output->scll = s->scll;
 461         output->sclh = s->sclh;
 462
 463         dev_dbg(i2c_dev->dev,
 464                 "Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n",
 465                 output->presc,
 466                 output->scldel, output->sdadel,
 467                 output->scll, output->sclh);
 468
 469 exit:
 470         /* Release list and memory */
 471         list_for_each_entry_safe(v, _v, &solutions, node) {
 472                 list_del(&v->node);
 473                 kfree(v);
 474         }
 475
 476         return ret;
 477 }
 478
 479 static int stm32f7_i2c_setup_timing(struct stm32f7_i2c_dev *i2c_dev,
 480                                     struct stm32f7_i2c_setup *setup)
 481 {
 482         int ret = 0;
 483
 484         setup->speed = i2c_dev->speed;
 485         setup->speed_freq = i2c_specs[setup->speed].rate;
 486         setup->clock_src = clk_get_rate(i2c_dev->clk);
 487
 488         if (!setup->clock_src) {
 489                 dev_err(i2c_dev->dev, "clock rate is 0\n");
 490                 return -EINVAL;
 491         }
 492
 493         do {
 494                 ret = stm32f7_i2c_compute_timing(i2c_dev, setup,
 495                                                  &i2c_dev->timing);
 496                 if (ret) {
 497                         dev_err(i2c_dev->dev,
 498                                 "failed to compute I2C timings.\n");
 499                         if (i2c_dev->speed > STM32_I2C_SPEED_STANDARD) {
 500                                 i2c_dev->speed--;
 501                                 setup->speed = i2c_dev->speed;
 502                                 setup->speed_freq =
 503                                         i2c_specs[setup->speed].rate;
 504                                 dev_warn(i2c_dev->dev,
 505                                          "downgrade I2C Speed Freq to (%i)\n",
 506                                          i2c_specs[setup->speed].rate);
 507                         } else {
 508                                 break;
 509                         }
 510                 }
 511         } while (ret);
 512
 513         if (ret) {
 514                 dev_err(i2c_dev->dev, "Impossible to compute I2C timings.\n");
 515                 return ret;
 516         }
 517
 518         dev_dbg(i2c_dev->dev, "I2C Speed(%i), Freq(%i), Clk Source(%i)\n",
 519                 setup->speed, setup->speed_freq, setup->clock_src);
 520         dev_dbg(i2c_dev->dev, "I2C Rise(%i) and Fall(%i) Time\n",
 521                 setup->rise_time, setup->fall_time);
 522         dev_dbg(i2c_dev->dev, "I2C Analog Filter(%s), DNF(%i)\n",
 523                 (setup->analog_filter ? "On" : "Off"), setup->dnf);
 524
 525         return 0;
 526 }
 527
 528 static void stm32f7_i2c_hw_config(struct stm32f7_i2c_dev *i2c_dev)
 529 {
 530         struct stm32f7_i2c_timings *t = &i2c_dev->timing;
 531         u32 timing = 0;
 532
 533         /* Timing settings */
 534         timing |= STM32F7_I2C_TIMINGR_PRESC(t->presc);
 535         timing |= STM32F7_I2C_TIMINGR_SCLDEL(t->scldel);
 536         timing |= STM32F7_I2C_TIMINGR_SDADEL(t->sdadel);
 537         timing |= STM32F7_I2C_TIMINGR_SCLH(t->sclh);
 538         timing |= STM32F7_I2C_TIMINGR_SCLL(t->scll);
 539         writel_relaxed(timing, i2c_dev->base + STM32F7_I2C_TIMINGR);
 540
 541         /* Enable I2C */
 542         if (i2c_dev->setup.analog_filter)
 543                 stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 544                                      STM32F7_I2C_CR1_ANFOFF);
 545         else
 546                 stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 547                                      STM32F7_I2C_CR1_ANFOFF);
 548
 549         /* Program the Digital Filter */
 550         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1,
 551                              STM32F7_I2C_CR1_DNF_MASK);
 552         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 553                              STM32F7_I2C_CR1_DNF(i2c_dev->setup.dnf));
 554
 555         stm32f7_i2c_set_bits(i2c_dev->base + STM32F7_I2C_CR1,
 556                              STM32F7_I2C_CR1_PE);
 557 }
 558
 559 static void stm32f7_i2c_write_tx_data(struct stm32f7_i2c_dev *i2c_dev)
 560 {
 561         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 562         void __iomem *base = i2c_dev->base;
 563
 564         if (f7_msg->count) {
 565                 writeb_relaxed(*f7_msg->buf++, base + STM32F7_I2C_TXDR);
 566                 f7_msg->count--;
 567         }
 568 }
 569
 570 static void stm32f7_i2c_read_rx_data(struct stm32f7_i2c_dev *i2c_dev)
 571 {
 572         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 573         void __iomem *base = i2c_dev->base;
 574
 575         if (f7_msg->count) {
 576                 *f7_msg->buf++ = readb_relaxed(base + STM32F7_I2C_RXDR);
 577                 f7_msg->count--;
 578         }
 579 }
 580
 581 static void stm32f7_i2c_reload(struct stm32f7_i2c_dev *i2c_dev)
 582 {
 583         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 584         u32 cr2;
 585
 586         cr2 = readl_relaxed(i2c_dev->base + STM32F7_I2C_CR2);
 587
 588         cr2 &= ~STM32F7_I2C_CR2_NBYTES_MASK;
 589         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 590                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 591         } else {
 592                 cr2 &= ~STM32F7_I2C_CR2_RELOAD;
 593                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 594         }
 595
 596         writel_relaxed(cr2, i2c_dev->base + STM32F7_I2C_CR2);
 597 }
 598
 599 static int stm32f7_i2c_wait_free_bus(struct stm32f7_i2c_dev *i2c_dev)
 600 {
 601         u32 status;
 602         int ret;
 603
 604         ret = readl_relaxed_poll_timeout(i2c_dev->base + STM32F7_I2C_ISR,
 605                                          status,
 606                                          !(status & STM32F7_I2C_ISR_BUSY),
 607                                          10, 1000);
 608         if (ret) {
 609                 dev_dbg(i2c_dev->dev, "bus busy\n");
 610                 ret = -EBUSY;
 611         }
 612
 613         return ret;
 614 }
 615
 616 static void stm32f7_i2c_xfer_msg(struct stm32f7_i2c_dev *i2c_dev,
 617                                  struct i2c_msg *msg)
 618 {
 619         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 620         void __iomem *base = i2c_dev->base;
 621         u32 cr1, cr2;
 622
 623         f7_msg->addr = msg->addr;
 624         f7_msg->buf = msg->buf;
 625         f7_msg->count = msg->len;
 626         f7_msg->result = 0;
 627         f7_msg->stop = (i2c_dev->msg_id >= i2c_dev->msg_num - 1);
 628
 629         reinit_completion(&i2c_dev->complete);
 630
 631         cr1 = readl_relaxed(base + STM32F7_I2C_CR1);
 632         cr2 = readl_relaxed(base + STM32F7_I2C_CR2);
 633
 634         /* Set transfer direction */
 635         cr2 &= ~STM32F7_I2C_CR2_RD_WRN;
 636         if (msg->flags & I2C_M_RD)
 637                 cr2 |= STM32F7_I2C_CR2_RD_WRN;
 638
 639         /* Set slave address */
 640         cr2 &= ~STM32F7_I2C_CR2_SADD7_MASK;
 641         cr2 |= STM32F7_I2C_CR2_SADD7(f7_msg->addr);
 642
 643         /* Set nb bytes to transfer and reload if needed */
 644         cr2 &= ~(STM32F7_I2C_CR2_NBYTES_MASK | STM32F7_I2C_CR2_RELOAD);
 645         if (f7_msg->count > STM32F7_I2C_MAX_LEN) {
 646                 cr2 |= STM32F7_I2C_CR2_NBYTES(STM32F7_I2C_MAX_LEN);
 647                 cr2 |= STM32F7_I2C_CR2_RELOAD;
 648         } else {
 649                 cr2 |= STM32F7_I2C_CR2_NBYTES(f7_msg->count);
 650         }
 651
 652         /* Enable NACK, STOP, error and transfer complete interrupts */
 653         cr1 |= STM32F7_I2C_CR1_ERRIE | STM32F7_I2C_CR1_TCIE |
 654                 STM32F7_I2C_CR1_STOPIE | STM32F7_I2C_CR1_NACKIE;
 655
 656         /* Clear TX/RX interrupt */
 657         cr1 &= ~(STM32F7_I2C_CR1_RXIE | STM32F7_I2C_CR1_TXIE);
 658
 659         /* Enable RX/TX interrupt according to msg direction */
 660         if (msg->flags & I2C_M_RD)
 661                 cr1 |= STM32F7_I2C_CR1_RXIE;
 662         else
 663                 cr1 |= STM32F7_I2C_CR1_TXIE;
 664
 665         /* Configure Start/Repeated Start */
 666         cr2 |= STM32F7_I2C_CR2_START;
 667
 668         /* Write configurations registers */
 669         writel_relaxed(cr1, base + STM32F7_I2C_CR1);
 670         writel_relaxed(cr2, base + STM32F7_I2C_CR2);
 671 }
 672
 673 static void stm32f7_i2c_disable_irq(struct stm32f7_i2c_dev *i2c_dev, u32 mask)
 674 {
 675         stm32f7_i2c_clr_bits(i2c_dev->base + STM32F7_I2C_CR1, mask);
 676 }
 677
 678 static irqreturn_t stm32f7_i2c_isr_event(int irq, void *data)
 679 {
 680         struct stm32f7_i2c_dev *i2c_dev = data;
 681         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 682         void __iomem *base = i2c_dev->base;
 683         u32 status, mask;
 684
 685         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
 686
 687         /* Tx empty */
 688         if (status & STM32F7_I2C_ISR_TXIS)
 689                 stm32f7_i2c_write_tx_data(i2c_dev);
 690
 691         /* RX not empty */
 692         if (status & STM32F7_I2C_ISR_RXNE)
 693                 stm32f7_i2c_read_rx_data(i2c_dev);
 694
 695         /* NACK received */
 696         if (status & STM32F7_I2C_ISR_NACKF) {
 697                 dev_dbg(i2c_dev->dev, "<%s>: Receive NACK\n", __func__);
 698                 writel_relaxed(STM32F7_I2C_ICR_NACKCF, base + STM32F7_I2C_ICR);
 699                 f7_msg->result = -ENXIO;
 700         }
 701
 702         /* STOP detection flag */
 703         if (status & STM32F7_I2C_ISR_STOPF) {
 704                 /* Disable interrupts */
 705                 stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
 706
 707                 /* Clear STOP flag */
 708                 writel_relaxed(STM32F7_I2C_ICR_STOPCF, base + STM32F7_I2C_ICR);
 709
 710                 complete(&i2c_dev->complete);
 711         }
 712
 713         /* Transfer complete */
 714         if (status & STM32F7_I2C_ISR_TC) {
 715                 if (f7_msg->stop) {
 716                         mask = STM32F7_I2C_CR2_STOP;
 717                         stm32f7_i2c_set_bits(base + STM32F7_I2C_CR2, mask);
 718                 } else {
 719                         i2c_dev->msg_id++;
 720                         i2c_dev->msg++;
 721                         stm32f7_i2c_xfer_msg(i2c_dev, i2c_dev->msg);
 722                 }
 723         }
 724
 725         /*
 726          * Transfer Complete Reload: 255 data bytes have been transferred
 727          * We have to prepare the I2C controller to transfer the remaining
 728          * data.
 729          */
 730         if (status & STM32F7_I2C_ISR_TCR)
 731                 stm32f7_i2c_reload(i2c_dev);
 732
 733         return IRQ_HANDLED;
 734 }
 735
 736 static irqreturn_t stm32f7_i2c_isr_error(int irq, void *data)
 737 {
 738         struct stm32f7_i2c_dev *i2c_dev = data;
 739         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 740         void __iomem *base = i2c_dev->base;
 741         struct device *dev = i2c_dev->dev;
 742         u32 status;
 743
 744         status = readl_relaxed(i2c_dev->base + STM32F7_I2C_ISR);
 745
 746         /* Bus error */
 747         if (status & STM32F7_I2C_ISR_BERR) {
 748                 dev_err(dev, "<%s>: Bus error\n", __func__);
 749                 writel_relaxed(STM32F7_I2C_ICR_BERRCF, base + STM32F7_I2C_ICR);
 750                 f7_msg->result = -EIO;
 751         }
 752
 753         /* Arbitration loss */
 754         if (status & STM32F7_I2C_ISR_ARLO) {
 755                 dev_dbg(dev, "<%s>: Arbitration loss\n", __func__);
 756                 writel_relaxed(STM32F7_I2C_ICR_ARLOCF, base + STM32F7_I2C_ICR);
 757                 f7_msg->result = -EAGAIN;
 758         }
 759
 760         stm32f7_i2c_disable_irq(i2c_dev, STM32F7_I2C_ALL_IRQ_MASK);
 761
 762         complete(&i2c_dev->complete);
 763
 764         return IRQ_HANDLED;
 765 }
 766
 767 static int stm32f7_i2c_xfer(struct i2c_adapter *i2c_adap,
 768                             struct i2c_msg msgs[], int num)
 769 {
 770         struct stm32f7_i2c_dev *i2c_dev = i2c_get_adapdata(i2c_adap);
 771         struct stm32f7_i2c_msg *f7_msg = &i2c_dev->f7_msg;
 772         unsigned long time_left;
 773         int ret;
 774
 775         i2c_dev->msg = msgs;
 776         i2c_dev->msg_num = num;
 777         i2c_dev->msg_id = 0;
 778
 779         ret = clk_enable(i2c_dev->clk);
 780         if (ret) {
 781                 dev_err(i2c_dev->dev, "Failed to enable clock\n");
 782                 return ret;
 783         }
 784
 785         ret = stm32f7_i2c_wait_free_bus(i2c_dev);
 786         if (ret)
 787                 goto clk_free;
 788
 789         stm32f7_i2c_xfer_msg(i2c_dev, msgs);
 790
 791         time_left = wait_for_completion_timeout(&i2c_dev->complete,
 792                                                 i2c_dev->adap.timeout);
 793         ret = f7_msg->result;
 794
 795         if (!time_left) {
 796                 dev_dbg(i2c_dev->dev, "Access to slave 0x%x timed out\n",
 797                         i2c_dev->msg->addr);
 798                 ret = -ETIMEDOUT;
 799         }
 800
 801 clk_free:
 802         clk_disable(i2c_dev->clk);
 803
 804         return (ret < 0) ? ret : num;
 805 }
 806
 807 static u32 stm32f7_i2c_func(struct i2c_adapter *adap)
 808 {
 809         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 810 }
 811
 812 static struct i2c_algorithm stm32f7_i2c_algo = {
 813         .master_xfer = stm32f7_i2c_xfer,
 814         .functionality = stm32f7_i2c_func,
 815 };
 816
 817 static int stm32f7_i2c_probe(struct platform_device *pdev)
 818 {
 819         struct device_node *np = pdev->dev.of_node;
 820         struct stm32f7_i2c_dev *i2c_dev;
 821         const struct stm32f7_i2c_setup *setup;
 822         struct resource *res;
 823         u32 irq_error, irq_event, clk_rate, rise_time, fall_time;
 824         struct i2c_adapter *adap;
 825         struct reset_control *rst;
 826         int ret;
 827
 828         i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
 829         if (!i2c_dev)
 830                 return -ENOMEM;
 831
 832         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 833         i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
 834         if (IS_ERR(i2c_dev->base))
 835                 return PTR_ERR(i2c_dev->base);
 836
 837         irq_event = irq_of_parse_and_map(np, 0);
 838         if (!irq_event) {
 839                 dev_err(&pdev->dev, "IRQ event missing or invalid\n");
 840                 return -EINVAL;
 841         }
 842
 843         irq_error = irq_of_parse_and_map(np, 1);
 844         if (!irq_error) {
 845                 dev_err(&pdev->dev, "IRQ error missing or invalid\n");
 846                 return -EINVAL;
 847         }
 848
 849         i2c_dev->clk = devm_clk_get(&pdev->dev, NULL);
 850         if (IS_ERR(i2c_dev->clk)) {
 851                 dev_err(&pdev->dev, "Error: Missing controller clock\n");
 852                 return PTR_ERR(i2c_dev->clk);
 853         }
 854         ret = clk_prepare_enable(i2c_dev->clk);
 855         if (ret) {
 856                 dev_err(&pdev->dev, "Failed to prepare_enable clock\n");
 857                 return ret;
 858         }
 859
 860         i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
 861         ret = device_property_read_u32(&pdev->dev, "clock-frequency",
 862                                        &clk_rate);
 863         if (!ret && clk_rate >= 1000000)
 864                 i2c_dev->speed = STM32_I2C_SPEED_FAST_PLUS;
 865         else if (!ret && clk_rate >= 400000)
 866                 i2c_dev->speed = STM32_I2C_SPEED_FAST;
 867         else if (!ret && clk_rate >= 100000)
 868                 i2c_dev->speed = STM32_I2C_SPEED_STANDARD;
 869
 870         rst = devm_reset_control_get(&pdev->dev, NULL);
 871         if (IS_ERR(rst)) {
 872                 dev_err(&pdev->dev, "Error: Missing controller reset\n");
 873                 ret = PTR_ERR(rst);
 874                 goto clk_free;
 875         }
 876         reset_control_assert(rst);
 877         udelay(2);
 878         reset_control_deassert(rst);
 879
 880         i2c_dev->dev = &pdev->dev;
 881
 882         ret = devm_request_irq(&pdev->dev, irq_event, stm32f7_i2c_isr_event, 0,
 883                                pdev->name, i2c_dev);
 884         if (ret) {
 885                 dev_err(&pdev->dev, "Failed to request irq event %i\n",
 886                         irq_event);
 887                 goto clk_free;
 888         }
 889
 890         ret = devm_request_irq(&pdev->dev, irq_error, stm32f7_i2c_isr_error, 0,
 891                                pdev->name, i2c_dev);
 892         if (ret) {
 893                 dev_err(&pdev->dev, "Failed to request irq error %i\n",
 894                         irq_error);
 895                 goto clk_free;
 896         }
 897
 898         setup = of_device_get_match_data(&pdev->dev);
 899         if (!setup) {
 900                 dev_err(&pdev->dev, "Can't get device data\n");
 901                 ret = -ENODEV;
 902                 goto clk_free;
 903         }
 904         i2c_dev->setup = *setup;
 905
 906         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-rising-time-ns",
 907                                        &rise_time);
 908         if (!ret)
 909                 i2c_dev->setup.rise_time = rise_time;
 910
 911         ret = device_property_read_u32(i2c_dev->dev, "i2c-scl-falling-time-ns",
 912                                        &fall_time);
 913         if (!ret)
 914                 i2c_dev->setup.fall_time = fall_time;
 915
 916         ret = stm32f7_i2c_setup_timing(i2c_dev, &i2c_dev->setup);
 917         if (ret)
 918                 goto clk_free;
 919
 920         stm32f7_i2c_hw_config(i2c_dev);
 921
 922         adap = &i2c_dev->adap;
 923         i2c_set_adapdata(adap, i2c_dev);
 924         snprintf(adap->name, sizeof(adap->name), "STM32F7 I2C(%pa)",
 925                  &res->start);
 926         adap->owner = THIS_MODULE;
 927         adap->timeout = 2 * HZ;
 928         adap->retries = 3;
 929         adap->algo = &stm32f7_i2c_algo;
 930         adap->dev.parent = &pdev->dev;
 931         adap->dev.of_node = pdev->dev.of_node;
 932
 933         init_completion(&i2c_dev->complete);
 934
 935         ret = i2c_add_adapter(adap);
 936         if (ret)
 937                 goto clk_free;
 938
 939         platform_set_drvdata(pdev, i2c_dev);
 940
 941         clk_disable(i2c_dev->clk);
 942
 943         dev_info(i2c_dev->dev, "STM32F7 I2C-%d bus adapter\n", adap->nr);
 944
 945         return 0;
 946
 947 clk_free:
 948         clk_disable_unprepare(i2c_dev->clk);
 949
 950         return ret;
 951 }
 952
 953 static int stm32f7_i2c_remove(struct platform_device *pdev)
 954 {
 955         struct stm32f7_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
 956
 957         i2c_del_adapter(&i2c_dev->adap);
 958
 959         clk_unprepare(i2c_dev->clk);
 960
 961         return 0;
 962 }
 963
 964 static const struct of_device_id stm32f7_i2c_match[] = {
 965         { .compatible = "st,stm32f7-i2c", .data = &stm32f7_setup},
 966         {},
 967 };
 968 MODULE_DEVICE_TABLE(of, stm32f7_i2c_match);
 969
 970 static struct platform_driver stm32f7_i2c_driver = {
 971         .driver = {
 972                 .name = "stm32f7-i2c",
 973                 .of_match_table = stm32f7_i2c_match,
 974         },
 975         .probe = stm32f7_i2c_probe,
 976         .remove = stm32f7_i2c_remove,
 977 };
 978
 979 module_platform_driver(stm32f7_i2c_driver);
 980
 981 MODULE_AUTHOR("M'boumba Cedric Madianga <cedric.madianga@gmail.com>");
 982 MODULE_DESCRIPTION("STMicroelectronics STM32F7 I2C driver");
 983 MODULE_LICENSE("GPL v2");