drivers/i2c/busses/i2c-sprd.c

   1 /*
   2  * Copyright (C) 2017 Spreadtrum Communications Inc.
   3  *
   4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/i2c.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/module.h>
  16 #include <linux/of.h>
  17 #include <linux/of_device.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/pm_runtime.h>
  20
  21 #define I2C_CTL                 0x00
  22 #define I2C_ADDR_CFG            0x04
  23 #define I2C_COUNT               0x08
  24 #define I2C_RX                  0x0c
  25 #define I2C_TX                  0x10
  26 #define I2C_STATUS              0x14
  27 #define I2C_HSMODE_CFG          0x18
  28 #define I2C_VERSION             0x1c
  29 #define ADDR_DVD0               0x20
  30 #define ADDR_DVD1               0x24
  31 #define ADDR_STA0_DVD           0x28
  32 #define ADDR_RST                0x2c
  33
  34 /* I2C_CTL */
  35 #define STP_EN                  BIT(20)
  36 #define FIFO_AF_LVL_MASK        GENMASK(19, 16)
  37 #define FIFO_AF_LVL             16
  38 #define FIFO_AE_LVL_MASK        GENMASK(15, 12)
  39 #define FIFO_AE_LVL             12
  40 #define I2C_DMA_EN              BIT(11)
  41 #define FULL_INTEN              BIT(10)
  42 #define EMPTY_INTEN             BIT(9)
  43 #define I2C_DVD_OPT             BIT(8)
  44 #define I2C_OUT_OPT             BIT(7)
  45 #define I2C_TRIM_OPT            BIT(6)
  46 #define I2C_HS_MODE             BIT(4)
  47 #define I2C_MODE                BIT(3)
  48 #define I2C_EN                  BIT(2)
  49 #define I2C_INT_EN              BIT(1)
  50 #define I2C_START               BIT(0)
  51
  52 /* I2C_STATUS */
  53 #define SDA_IN                  BIT(21)
  54 #define SCL_IN                  BIT(20)
  55 #define FIFO_FULL               BIT(4)
  56 #define FIFO_EMPTY              BIT(3)
  57 #define I2C_INT                 BIT(2)
  58 #define I2C_RX_ACK              BIT(1)
  59 #define I2C_BUSY                BIT(0)
  60
  61 /* ADDR_RST */
  62 #define I2C_RST                 BIT(0)
  63
  64 #define I2C_FIFO_DEEP           12
  65 #define I2C_FIFO_FULL_THLD      15
  66 #define I2C_FIFO_EMPTY_THLD     4
  67 #define I2C_DATA_STEP           8
  68 #define I2C_ADDR_DVD0_CALC(high, low)   \
  69         ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
  70 #define I2C_ADDR_DVD1_CALC(high, low)   \
  71         (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
  72
  73 /* timeout (ms) for pm runtime autosuspend */
  74 #define SPRD_I2C_PM_TIMEOUT     1000
  75 /* timeout (ms) for transfer message */
  76 #define I2C_XFER_TIMEOUT        1000
  77
  78 /* SPRD i2c data structure */
  79 struct sprd_i2c {
  80         struct i2c_adapter adap;
  81         struct device *dev;
  82         void __iomem *base;
  83         struct i2c_msg *msg;
  84         struct clk *clk;
  85         u32 src_clk;
  86         u32 bus_freq;
  87         struct completion complete;
  88         u8 *buf;
  89         u32 count;
  90         int irq;
  91         int err;
  92 };
  93
  94 static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
  95 {
  96         writel(count, i2c_dev->base + I2C_COUNT);
  97 }
  98
  99 static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
 100 {
 101         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 102
 103         if (stop)
 104                 writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
 105         else
 106                 writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
 107 }
 108
 109 static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
 110 {
 111         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 112
 113         writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
 114 }
 115
 116 static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
 117 {
 118         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
 119
 120         writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
 121 }
 122
 123 static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
 124 {
 125         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
 126
 127         writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
 128 }
 129
 130 static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
 131 {
 132         writel(I2C_RST, i2c_dev->base + ADDR_RST);
 133 }
 134
 135 static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
 136 {
 137         writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
 138 }
 139
 140 static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
 141 {
 142         u32 i;
 143
 144         for (i = 0; i < len; i++)
 145                 writeb(buf[i], i2c_dev->base + I2C_TX);
 146 }
 147
 148 static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
 149 {
 150         u32 i;
 151
 152         for (i = 0; i < len; i++)
 153                 buf[i] = readb(i2c_dev->base + I2C_RX);
 154 }
 155
 156 static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
 157 {
 158         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 159
 160         tmp &= ~FIFO_AF_LVL_MASK;
 161         tmp |= full_thld << FIFO_AF_LVL;
 162         writel(tmp, i2c_dev->base + I2C_CTL);
 163 };
 164
 165 static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
 166 {
 167         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 168
 169         tmp &= ~FIFO_AE_LVL_MASK;
 170         tmp |= empty_thld << FIFO_AE_LVL;
 171         writel(tmp, i2c_dev->base + I2C_CTL);
 172 };
 173
 174 static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
 175 {
 176         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 177
 178         if (enable)
 179                 tmp |= FULL_INTEN;
 180         else
 181                 tmp &= ~FULL_INTEN;
 182
 183         writel(tmp, i2c_dev->base + I2C_CTL);
 184 };
 185
 186 static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
 187 {
 188         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 189
 190         if (enable)
 191                 tmp |= EMPTY_INTEN;
 192         else
 193                 tmp &= ~EMPTY_INTEN;
 194
 195         writel(tmp, i2c_dev->base + I2C_CTL);
 196 };
 197
 198 static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
 199 {
 200         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 201
 202         writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
 203 }
 204
 205 static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
 206 {
 207         u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
 208
 209         writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
 210 }
 211
 212 static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
 213 {
 214         u32 i2c_count = i2c_dev->count;
 215         u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
 216         struct i2c_msg *msg = i2c_dev->msg;
 217
 218         if (msg->flags & I2C_M_RD) {
 219                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
 220                 i2c_dev->count -= I2C_FIFO_FULL_THLD;
 221                 i2c_dev->buf += I2C_FIFO_FULL_THLD;
 222
 223                 /*
 224                  * If the read data count is larger than rx fifo full threshold,
 225                  * we should enable the rx fifo full interrupt to read data
 226                  * again.
 227                  */
 228                 if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
 229                         sprd_i2c_set_fifo_full_int(i2c_dev, 1);
 230         } else {
 231                 sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
 232                 i2c_dev->buf += need_tran;
 233                 i2c_dev->count -= need_tran;
 234
 235                 /*
 236                  * If the write data count is arger than tx fifo depth which
 237                  * means we can not write all data in one time, then we should
 238                  * enable the tx fifo empty interrupt to write again.
 239                  */
 240                 if (i2c_count > I2C_FIFO_DEEP)
 241                         sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
 242         }
 243 }
 244
 245 static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
 246                                struct i2c_msg *msg, bool is_last_msg)
 247 {
 248         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
 249         unsigned long time_left;
 250
 251         i2c_dev->msg = msg;
 252         i2c_dev->buf = msg->buf;
 253         i2c_dev->count = msg->len;
 254
 255         reinit_completion(&i2c_dev->complete);
 256         sprd_i2c_reset_fifo(i2c_dev);
 257         sprd_i2c_set_devaddr(i2c_dev, msg);
 258         sprd_i2c_set_count(i2c_dev, msg->len);
 259
 260         if (msg->flags & I2C_M_RD) {
 261                 sprd_i2c_opt_mode(i2c_dev, 1);
 262                 sprd_i2c_send_stop(i2c_dev, 1);
 263         } else {
 264                 sprd_i2c_opt_mode(i2c_dev, 0);
 265                 sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
 266         }
 267
 268         /*
 269          * We should enable rx fifo full interrupt to get data when receiving
 270          * full data.
 271          */
 272         if (msg->flags & I2C_M_RD)
 273                 sprd_i2c_set_fifo_full_int(i2c_dev, 1);
 274         else
 275                 sprd_i2c_data_transfer(i2c_dev);
 276
 277         sprd_i2c_opt_start(i2c_dev);
 278
 279         time_left = wait_for_completion_timeout(&i2c_dev->complete,
 280                                 msecs_to_jiffies(I2C_XFER_TIMEOUT));
 281         if (!time_left)
 282                 return -ETIMEDOUT;
 283
 284         return i2c_dev->err;
 285 }
 286
 287 static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
 288                                 struct i2c_msg *msgs, int num)
 289 {
 290         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
 291         int im, ret;
 292
 293         ret = pm_runtime_resume_and_get(i2c_dev->dev);
 294         if (ret < 0)
 295                 return ret;
 296
 297         for (im = 0; im < num - 1; im++) {
 298                 ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
 299                 if (ret)
 300                         goto err_msg;
 301         }
 302
 303         ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
 304
 305 err_msg:
 306         pm_runtime_mark_last_busy(i2c_dev->dev);
 307         pm_runtime_put_autosuspend(i2c_dev->dev);
 308
 309         return ret < 0 ? ret : im;
 310 }
 311
 312 static u32 sprd_i2c_func(struct i2c_adapter *adap)
 313 {
 314         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 315 }
 316
 317 static const struct i2c_algorithm sprd_i2c_algo = {
 318         .master_xfer = sprd_i2c_master_xfer,
 319         .functionality = sprd_i2c_func,
 320 };
 321
 322 static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
 323 {
 324         u32 apb_clk = i2c_dev->src_clk;
 325         /*
 326          * From I2C databook, the prescale calculation formula:
 327          * prescale = freq_i2c / (4 * freq_scl) - 1;
 328          */
 329         u32 i2c_dvd = apb_clk / (4 * freq) - 1;
 330         /*
 331          * From I2C databook, the high period of SCL clock is recommended as
 332          * 40% (2/5), and the low period of SCL clock is recommended as 60%
 333          * (3/5), then the formula should be:
 334          * high = (prescale * 2 * 2) / 5
 335          * low = (prescale * 2 * 3) / 5
 336          */
 337         u32 high = ((i2c_dvd << 1) * 2) / 5;
 338         u32 low = ((i2c_dvd << 1) * 3) / 5;
 339         u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
 340         u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
 341
 342         writel(div0, i2c_dev->base + ADDR_DVD0);
 343         writel(div1, i2c_dev->base + ADDR_DVD1);
 344
 345         /* Start hold timing = hold time(us) * source clock */
 346         if (freq == I2C_MAX_FAST_MODE_FREQ)
 347                 writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
 348         else if (freq == I2C_MAX_STANDARD_MODE_FREQ)
 349                 writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
 350 }
 351
 352 static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
 353 {
 354         u32 tmp = I2C_DVD_OPT;
 355
 356         writel(tmp, i2c_dev->base + I2C_CTL);
 357
 358         sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
 359         sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
 360
 361         sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
 362         sprd_i2c_reset_fifo(i2c_dev);
 363         sprd_i2c_clear_irq(i2c_dev);
 364
 365         tmp = readl(i2c_dev->base + I2C_CTL);
 366         writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
 367 }
 368
 369 static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
 370 {
 371         struct sprd_i2c *i2c_dev = dev_id;
 372         struct i2c_msg *msg = i2c_dev->msg;
 373         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
 374         u32 i2c_tran;
 375
 376         if (msg->flags & I2C_M_RD)
 377                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
 378         else
 379                 i2c_tran = i2c_dev->count;
 380
 381         /*
 382          * If we got one ACK from slave when writing data, and we did not
 383          * finish this transmission (i2c_tran is not zero), then we should
 384          * continue to write data.
 385          *
 386          * For reading data, ack is always true, if i2c_tran is not 0 which
 387          * means we still need to contine to read data from slave.
 388          */
 389         if (i2c_tran && ack) {
 390                 sprd_i2c_data_transfer(i2c_dev);
 391                 return IRQ_HANDLED;
 392         }
 393
 394         i2c_dev->err = 0;
 395
 396         /*
 397          * If we did not get one ACK from slave when writing data, we should
 398          * return -EIO to notify users.
 399          */
 400         if (!ack)
 401                 i2c_dev->err = -EIO;
 402         else if (msg->flags & I2C_M_RD && i2c_dev->count)
 403                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
 404
 405         /* Transmission is done and clear ack and start operation */
 406         sprd_i2c_clear_ack(i2c_dev);
 407         sprd_i2c_clear_start(i2c_dev);
 408         complete(&i2c_dev->complete);
 409
 410         return IRQ_HANDLED;
 411 }
 412
 413 static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
 414 {
 415         struct sprd_i2c *i2c_dev = dev_id;
 416         struct i2c_msg *msg = i2c_dev->msg;
 417         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
 418         u32 i2c_tran;
 419
 420         if (msg->flags & I2C_M_RD)
 421                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
 422         else
 423                 i2c_tran = i2c_dev->count;
 424
 425         /*
 426          * If we did not get one ACK from slave when writing data, then we
 427          * should finish this transmission since we got some errors.
 428          *
 429          * When writing data, if i2c_tran == 0 which means we have writen
 430          * done all data, then we can finish this transmission.
 431          *
 432          * When reading data, if conut < rx fifo full threshold, which
 433          * means we can read all data in one time, then we can finish this
 434          * transmission too.
 435          */
 436         if (!i2c_tran || !ack) {
 437                 sprd_i2c_clear_start(i2c_dev);
 438                 sprd_i2c_clear_irq(i2c_dev);
 439         }
 440
 441         sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
 442         sprd_i2c_set_fifo_full_int(i2c_dev, 0);
 443
 444         return IRQ_WAKE_THREAD;
 445 }
 446
 447 static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
 448 {
 449         struct clk *clk_i2c, *clk_parent;
 450
 451         clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
 452         if (IS_ERR(clk_i2c)) {
 453                 dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
 454                          i2c_dev->adap.nr);
 455                 clk_i2c = NULL;
 456         }
 457
 458         clk_parent = devm_clk_get(i2c_dev->dev, "source");
 459         if (IS_ERR(clk_parent)) {
 460                 dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
 461                          i2c_dev->adap.nr);
 462                 clk_parent = NULL;
 463         }
 464
 465         if (clk_set_parent(clk_i2c, clk_parent))
 466                 i2c_dev->src_clk = clk_get_rate(clk_i2c);
 467         else
 468                 i2c_dev->src_clk = 26000000;
 469
 470         dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
 471                 i2c_dev->adap.nr, i2c_dev->src_clk);
 472
 473         i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
 474         if (IS_ERR(i2c_dev->clk)) {
 475                 dev_err(i2c_dev->dev, "i2c%d can't get the enable clock\n",
 476                         i2c_dev->adap.nr);
 477                 return PTR_ERR(i2c_dev->clk);
 478         }
 479
 480         return 0;
 481 }
 482
 483 static int sprd_i2c_probe(struct platform_device *pdev)
 484 {
 485         struct device *dev = &pdev->dev;
 486         struct sprd_i2c *i2c_dev;
 487         u32 prop;
 488         int ret;
 489
 490         pdev->id = of_alias_get_id(dev->of_node, "i2c");
 491
 492         i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
 493         if (!i2c_dev)
 494                 return -ENOMEM;
 495
 496         i2c_dev->base = devm_platform_ioremap_resource(pdev, 0);
 497         if (IS_ERR(i2c_dev->base))
 498                 return PTR_ERR(i2c_dev->base);
 499
 500         i2c_dev->irq = platform_get_irq(pdev, 0);
 501         if (i2c_dev->irq < 0)
 502                 return i2c_dev->irq;
 503
 504         i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
 505         init_completion(&i2c_dev->complete);
 506         snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
 507                  "%s", "sprd-i2c");
 508
 509         i2c_dev->bus_freq = I2C_MAX_STANDARD_MODE_FREQ;
 510         i2c_dev->adap.owner = THIS_MODULE;
 511         i2c_dev->dev = dev;
 512         i2c_dev->adap.retries = 3;
 513         i2c_dev->adap.algo = &sprd_i2c_algo;
 514         i2c_dev->adap.algo_data = i2c_dev;
 515         i2c_dev->adap.dev.parent = dev;
 516         i2c_dev->adap.nr = pdev->id;
 517         i2c_dev->adap.dev.of_node = dev->of_node;
 518
 519         if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
 520                 i2c_dev->bus_freq = prop;
 521
 522         /* We only support 100k and 400k now, otherwise will return error. */
 523         if (i2c_dev->bus_freq != I2C_MAX_STANDARD_MODE_FREQ &&
 524             i2c_dev->bus_freq != I2C_MAX_FAST_MODE_FREQ)
 525                 return -EINVAL;
 526
 527         ret = sprd_i2c_clk_init(i2c_dev);
 528         if (ret)
 529                 return ret;
 530
 531         platform_set_drvdata(pdev, i2c_dev);
 532
 533         ret = clk_prepare_enable(i2c_dev->clk);
 534         if (ret)
 535                 return ret;
 536
 537         sprd_i2c_enable(i2c_dev);
 538
 539         pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
 540         pm_runtime_use_autosuspend(i2c_dev->dev);
 541         pm_runtime_set_active(i2c_dev->dev);
 542         pm_runtime_enable(i2c_dev->dev);
 543
 544         ret = pm_runtime_get_sync(i2c_dev->dev);
 545         if (ret < 0)
 546                 goto err_rpm_put;
 547
 548         ret = devm_request_threaded_irq(dev, i2c_dev->irq,
 549                 sprd_i2c_isr, sprd_i2c_isr_thread,
 550                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
 551                 pdev->name, i2c_dev);
 552         if (ret) {
 553                 dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
 554                 goto err_rpm_put;
 555         }
 556
 557         ret = i2c_add_numbered_adapter(&i2c_dev->adap);
 558         if (ret) {
 559                 dev_err(&pdev->dev, "add adapter failed\n");
 560                 goto err_rpm_put;
 561         }
 562
 563         pm_runtime_mark_last_busy(i2c_dev->dev);
 564         pm_runtime_put_autosuspend(i2c_dev->dev);
 565         return 0;
 566
 567 err_rpm_put:
 568         pm_runtime_put_noidle(i2c_dev->dev);
 569         pm_runtime_disable(i2c_dev->dev);
 570         clk_disable_unprepare(i2c_dev->clk);
 571         return ret;
 572 }
 573
 574 static int sprd_i2c_remove(struct platform_device *pdev)
 575 {
 576         struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
 577         int ret;
 578
 579         ret = pm_runtime_get_sync(i2c_dev->dev);
 580         if (ret < 0)
 581                 dev_err(&pdev->dev, "Failed to resume device (%pe)\n", ERR_PTR(ret));
 582
 583         i2c_del_adapter(&i2c_dev->adap);
 584
 585         if (ret >= 0)
 586                 clk_disable_unprepare(i2c_dev->clk);
 587
 588         pm_runtime_put_noidle(i2c_dev->dev);
 589         pm_runtime_disable(i2c_dev->dev);
 590
 591         return 0;
 592 }
 593
 594 static int __maybe_unused sprd_i2c_suspend_noirq(struct device *dev)
 595 {
 596         struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
 597
 598         i2c_mark_adapter_suspended(&i2c_dev->adap);
 599         return pm_runtime_force_suspend(dev);
 600 }
 601
 602 static int __maybe_unused sprd_i2c_resume_noirq(struct device *dev)
 603 {
 604         struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
 605
 606         i2c_mark_adapter_resumed(&i2c_dev->adap);
 607         return pm_runtime_force_resume(dev);
 608 }
 609
 610 static int __maybe_unused sprd_i2c_runtime_suspend(struct device *dev)
 611 {
 612         struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
 613
 614         clk_disable_unprepare(i2c_dev->clk);
 615
 616         return 0;
 617 }
 618
 619 static int __maybe_unused sprd_i2c_runtime_resume(struct device *dev)
 620 {
 621         struct sprd_i2c *i2c_dev = dev_get_drvdata(dev);
 622         int ret;
 623
 624         ret = clk_prepare_enable(i2c_dev->clk);
 625         if (ret)
 626                 return ret;
 627
 628         sprd_i2c_enable(i2c_dev);
 629
 630         return 0;
 631 }
 632
 633 static const struct dev_pm_ops sprd_i2c_pm_ops = {
 634         SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
 635                            sprd_i2c_runtime_resume, NULL)
 636
 637         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
 638                                       sprd_i2c_resume_noirq)
 639 };
 640
 641 static const struct of_device_id sprd_i2c_of_match[] = {
 642         { .compatible = "sprd,sc9860-i2c", },
 643         {},
 644 };
 645
 646 static struct platform_driver sprd_i2c_driver = {
 647         .probe = sprd_i2c_probe,
 648         .remove = sprd_i2c_remove,
 649         .driver = {
 650                    .name = "sprd-i2c",
 651                    .of_match_table = sprd_i2c_of_match,
 652                    .pm = &sprd_i2c_pm_ops,
 653         },
 654 };
 655
 656 module_platform_driver(sprd_i2c_driver);
 657
 658 MODULE_DESCRIPTION("Spreadtrum I2C master controller driver");
 659 MODULE_LICENSE("GPL v2");