drivers/i2c/busses/i2c-sprd.c

   1 /*
   2  * Copyright (C) 2017 Spreadtrum Communications Inc.
   3  *
   4  * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   5  */
   6
   7 #include <linux/clk.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/i2c.h>
  12 #include <linux/init.h>
  13 #include <linux/interrupt.h>
  14 #include <linux/kernel.h>
  15 #include <linux/of.h>
  16 #include <linux/of_device.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19
  20 #define I2C_CTL                 0x00
  21 #define I2C_ADDR_CFG            0x04
  22 #define I2C_COUNT               0x08
  23 #define I2C_RX                  0x0c
  24 #define I2C_TX                  0x10
  25 #define I2C_STATUS              0x14
  26 #define I2C_HSMODE_CFG          0x18
  27 #define I2C_VERSION             0x1c
  28 #define ADDR_DVD0               0x20
  29 #define ADDR_DVD1               0x24
  30 #define ADDR_STA0_DVD           0x28
  31 #define ADDR_RST                0x2c
  32
  33 /* I2C_CTL */
  34 #define STP_EN                  BIT(20)
  35 #define FIFO_AF_LVL_MASK        GENMASK(19, 16)
  36 #define FIFO_AF_LVL             16
  37 #define FIFO_AE_LVL_MASK        GENMASK(15, 12)
  38 #define FIFO_AE_LVL             12
  39 #define I2C_DMA_EN              BIT(11)
  40 #define FULL_INTEN              BIT(10)
  41 #define EMPTY_INTEN             BIT(9)
  42 #define I2C_DVD_OPT             BIT(8)
  43 #define I2C_OUT_OPT             BIT(7)
  44 #define I2C_TRIM_OPT            BIT(6)
  45 #define I2C_HS_MODE             BIT(4)
  46 #define I2C_MODE                BIT(3)
  47 #define I2C_EN                  BIT(2)
  48 #define I2C_INT_EN              BIT(1)
  49 #define I2C_START               BIT(0)
  50
  51 /* I2C_STATUS */
  52 #define SDA_IN                  BIT(21)
  53 #define SCL_IN                  BIT(20)
  54 #define FIFO_FULL               BIT(4)
  55 #define FIFO_EMPTY              BIT(3)
  56 #define I2C_INT                 BIT(2)
  57 #define I2C_RX_ACK              BIT(1)
  58 #define I2C_BUSY                BIT(0)
  59
  60 /* ADDR_RST */
  61 #define I2C_RST                 BIT(0)
  62
  63 #define I2C_FIFO_DEEP           12
  64 #define I2C_FIFO_FULL_THLD      15
  65 #define I2C_FIFO_EMPTY_THLD     4
  66 #define I2C_DATA_STEP           8
  67 #define I2C_ADDR_DVD0_CALC(high, low)   \
  68         ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
  69 #define I2C_ADDR_DVD1_CALC(high, low)   \
  70         (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
  71
  72 /* timeout (ms) for pm runtime autosuspend */
  73 #define SPRD_I2C_PM_TIMEOUT     1000
  74 /* timeout (ms) for transfer message */
  75 #define I2C_XFER_TIMEOUT        1000
  76
  77 /* SPRD i2c data structure */
  78 struct sprd_i2c {
  79         struct i2c_adapter adap;
  80         struct device *dev;
  81         void __iomem *base;
  82         struct i2c_msg *msg;
  83         struct clk *clk;
  84         u32 src_clk;
  85         u32 bus_freq;
  86         struct completion complete;
  87         u8 *buf;
  88         u32 count;
  89         int irq;
  90         int err;
  91         bool is_suspended;
  92 };
  93
  94 static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
  95 {
  96         writel(count, i2c_dev->base + I2C_COUNT);
  97 }
  98
  99 static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
 100 {
 101         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 102
 103         if (stop)
 104                 writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
 105         else
 106                 writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
 107 }
 108
 109 static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
 110 {
 111         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 112
 113         writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
 114 }
 115
 116 static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
 117 {
 118         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
 119
 120         writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
 121 }
 122
 123 static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
 124 {
 125         u32 tmp = readl(i2c_dev->base + I2C_STATUS);
 126
 127         writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
 128 }
 129
 130 static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
 131 {
 132         writel(I2C_RST, i2c_dev->base + ADDR_RST);
 133 }
 134
 135 static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
 136 {
 137         writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
 138 }
 139
 140 static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
 141 {
 142         u32 i;
 143
 144         for (i = 0; i < len; i++)
 145                 writeb(buf[i], i2c_dev->base + I2C_TX);
 146 }
 147
 148 static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
 149 {
 150         u32 i;
 151
 152         for (i = 0; i < len; i++)
 153                 buf[i] = readb(i2c_dev->base + I2C_RX);
 154 }
 155
 156 static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
 157 {
 158         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 159
 160         tmp &= ~FIFO_AF_LVL_MASK;
 161         tmp |= full_thld << FIFO_AF_LVL;
 162         writel(tmp, i2c_dev->base + I2C_CTL);
 163 };
 164
 165 static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
 166 {
 167         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 168
 169         tmp &= ~FIFO_AE_LVL_MASK;
 170         tmp |= empty_thld << FIFO_AE_LVL;
 171         writel(tmp, i2c_dev->base + I2C_CTL);
 172 };
 173
 174 static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
 175 {
 176         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 177
 178         if (enable)
 179                 tmp |= FULL_INTEN;
 180         else
 181                 tmp &= ~FULL_INTEN;
 182
 183         writel(tmp, i2c_dev->base + I2C_CTL);
 184 };
 185
 186 static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
 187 {
 188         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 189
 190         if (enable)
 191                 tmp |= EMPTY_INTEN;
 192         else
 193                 tmp &= ~EMPTY_INTEN;
 194
 195         writel(tmp, i2c_dev->base + I2C_CTL);
 196 };
 197
 198 static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
 199 {
 200         u32 tmp = readl(i2c_dev->base + I2C_CTL);
 201
 202         writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
 203 }
 204
 205 static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
 206 {
 207         u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
 208
 209         writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
 210 }
 211
 212 static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
 213 {
 214         u32 i2c_count = i2c_dev->count;
 215         u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
 216         struct i2c_msg *msg = i2c_dev->msg;
 217
 218         if (msg->flags & I2C_M_RD) {
 219                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
 220                 i2c_dev->count -= I2C_FIFO_FULL_THLD;
 221                 i2c_dev->buf += I2C_FIFO_FULL_THLD;
 222
 223                 /*
 224                  * If the read data count is larger than rx fifo full threshold,
 225                  * we should enable the rx fifo full interrupt to read data
 226                  * again.
 227                  */
 228                 if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
 229                         sprd_i2c_set_fifo_full_int(i2c_dev, 1);
 230         } else {
 231                 sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
 232                 i2c_dev->buf += need_tran;
 233                 i2c_dev->count -= need_tran;
 234
 235                 /*
 236                  * If the write data count is arger than tx fifo depth which
 237                  * means we can not write all data in one time, then we should
 238                  * enable the tx fifo empty interrupt to write again.
 239                  */
 240                 if (i2c_count > I2C_FIFO_DEEP)
 241                         sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
 242         }
 243 }
 244
 245 static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
 246                                struct i2c_msg *msg, bool is_last_msg)
 247 {
 248         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
 249         unsigned long time_left;
 250
 251         i2c_dev->msg = msg;
 252         i2c_dev->buf = msg->buf;
 253         i2c_dev->count = msg->len;
 254
 255         reinit_completion(&i2c_dev->complete);
 256         sprd_i2c_reset_fifo(i2c_dev);
 257         sprd_i2c_set_devaddr(i2c_dev, msg);
 258         sprd_i2c_set_count(i2c_dev, msg->len);
 259
 260         if (msg->flags & I2C_M_RD) {
 261                 sprd_i2c_opt_mode(i2c_dev, 1);
 262                 sprd_i2c_send_stop(i2c_dev, 1);
 263         } else {
 264                 sprd_i2c_opt_mode(i2c_dev, 0);
 265                 sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
 266         }
 267
 268         /*
 269          * We should enable rx fifo full interrupt to get data when receiving
 270          * full data.
 271          */
 272         if (msg->flags & I2C_M_RD)
 273                 sprd_i2c_set_fifo_full_int(i2c_dev, 1);
 274         else
 275                 sprd_i2c_data_transfer(i2c_dev);
 276
 277         sprd_i2c_opt_start(i2c_dev);
 278
 279         time_left = wait_for_completion_timeout(&i2c_dev->complete,
 280                                 msecs_to_jiffies(I2C_XFER_TIMEOUT));
 281         if (!time_left)
 282                 return -ETIMEDOUT;
 283
 284         return i2c_dev->err;
 285 }
 286
 287 static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
 288                                 struct i2c_msg *msgs, int num)
 289 {
 290         struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
 291         int im, ret;
 292
 293         if (i2c_dev->is_suspended)
 294                 return -EBUSY;
 295
 296         ret = pm_runtime_get_sync(i2c_dev->dev);
 297         if (ret < 0)
 298                 return ret;
 299
 300         for (im = 0; im < num - 1; im++) {
 301                 ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
 302                 if (ret)
 303                         goto err_msg;
 304         }
 305
 306         ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
 307
 308 err_msg:
 309         pm_runtime_mark_last_busy(i2c_dev->dev);
 310         pm_runtime_put_autosuspend(i2c_dev->dev);
 311
 312         return ret < 0 ? ret : im;
 313 }
 314
 315 static u32 sprd_i2c_func(struct i2c_adapter *adap)
 316 {
 317         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 318 }
 319
 320 static const struct i2c_algorithm sprd_i2c_algo = {
 321         .master_xfer = sprd_i2c_master_xfer,
 322         .functionality = sprd_i2c_func,
 323 };
 324
 325 static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
 326 {
 327         u32 apb_clk = i2c_dev->src_clk;
 328         /*
 329          * From I2C databook, the prescale calculation formula:
 330          * prescale = freq_i2c / (4 * freq_scl) - 1;
 331          */
 332         u32 i2c_dvd = apb_clk / (4 * freq) - 1;
 333         /*
 334          * From I2C databook, the high period of SCL clock is recommended as
 335          * 40% (2/5), and the low period of SCL clock is recommended as 60%
 336          * (3/5), then the formula should be:
 337          * high = (prescale * 2 * 2) / 5
 338          * low = (prescale * 2 * 3) / 5
 339          */
 340         u32 high = ((i2c_dvd << 1) * 2) / 5;
 341         u32 low = ((i2c_dvd << 1) * 3) / 5;
 342         u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
 343         u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
 344
 345         writel(div0, i2c_dev->base + ADDR_DVD0);
 346         writel(div1, i2c_dev->base + ADDR_DVD1);
 347
 348         /* Start hold timing = hold time(us) * source clock */
 349         if (freq == 400000)
 350                 writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
 351         else if (freq == 100000)
 352                 writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
 353 }
 354
 355 static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
 356 {
 357         u32 tmp = I2C_DVD_OPT;
 358
 359         writel(tmp, i2c_dev->base + I2C_CTL);
 360
 361         sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
 362         sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
 363
 364         sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
 365         sprd_i2c_reset_fifo(i2c_dev);
 366         sprd_i2c_clear_irq(i2c_dev);
 367
 368         tmp = readl(i2c_dev->base + I2C_CTL);
 369         writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
 370 }
 371
 372 static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
 373 {
 374         struct sprd_i2c *i2c_dev = dev_id;
 375         struct i2c_msg *msg = i2c_dev->msg;
 376         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
 377         u32 i2c_tran;
 378
 379         if (msg->flags & I2C_M_RD)
 380                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
 381         else
 382                 i2c_tran = i2c_dev->count;
 383
 384         /*
 385          * If we got one ACK from slave when writing data, and we did not
 386          * finish this transmission (i2c_tran is not zero), then we should
 387          * continue to write data.
 388          *
 389          * For reading data, ack is always true, if i2c_tran is not 0 which
 390          * means we still need to contine to read data from slave.
 391          */
 392         if (i2c_tran && ack) {
 393                 sprd_i2c_data_transfer(i2c_dev);
 394                 return IRQ_HANDLED;
 395         }
 396
 397         i2c_dev->err = 0;
 398
 399         /*
 400          * If we did not get one ACK from slave when writing data, we should
 401          * return -EIO to notify users.
 402          */
 403         if (!ack)
 404                 i2c_dev->err = -EIO;
 405         else if (msg->flags & I2C_M_RD && i2c_dev->count)
 406                 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
 407
 408         /* Transmission is done and clear ack and start operation */
 409         sprd_i2c_clear_ack(i2c_dev);
 410         sprd_i2c_clear_start(i2c_dev);
 411         complete(&i2c_dev->complete);
 412
 413         return IRQ_HANDLED;
 414 }
 415
 416 static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
 417 {
 418         struct sprd_i2c *i2c_dev = dev_id;
 419         struct i2c_msg *msg = i2c_dev->msg;
 420         bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
 421         u32 i2c_tran;
 422
 423         if (msg->flags & I2C_M_RD)
 424                 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
 425         else
 426                 i2c_tran = i2c_dev->count;
 427
 428         /*
 429          * If we did not get one ACK from slave when writing data, then we
 430          * should finish this transmission since we got some errors.
 431          *
 432          * When writing data, if i2c_tran == 0 which means we have writen
 433          * done all data, then we can finish this transmission.
 434          *
 435          * When reading data, if conut < rx fifo full threshold, which
 436          * means we can read all data in one time, then we can finish this
 437          * transmission too.
 438          */
 439         if (!i2c_tran || !ack) {
 440                 sprd_i2c_clear_start(i2c_dev);
 441                 sprd_i2c_clear_irq(i2c_dev);
 442         }
 443
 444         sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
 445         sprd_i2c_set_fifo_full_int(i2c_dev, 0);
 446
 447         return IRQ_WAKE_THREAD;
 448 }
 449
 450 static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
 451 {
 452         struct clk *clk_i2c, *clk_parent;
 453
 454         clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
 455         if (IS_ERR(clk_i2c)) {
 456                 dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
 457                          i2c_dev->adap.nr);
 458                 clk_i2c = NULL;
 459         }
 460
 461         clk_parent = devm_clk_get(i2c_dev->dev, "source");
 462         if (IS_ERR(clk_parent)) {
 463                 dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
 464                          i2c_dev->adap.nr);
 465                 clk_parent = NULL;
 466         }
 467
 468         if (clk_set_parent(clk_i2c, clk_parent))
 469                 i2c_dev->src_clk = clk_get_rate(clk_i2c);
 470         else
 471                 i2c_dev->src_clk = 26000000;
 472
 473         dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
 474                 i2c_dev->adap.nr, i2c_dev->src_clk);
 475
 476         i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
 477         if (IS_ERR(i2c_dev->clk)) {
 478                 dev_warn(i2c_dev->dev, "i2c%d can't get the enable clock\n",
 479                          i2c_dev->adap.nr);
 480                 i2c_dev->clk = NULL;
 481         }
 482
 483         return 0;
 484 }
 485
 486 static int sprd_i2c_probe(struct platform_device *pdev)
 487 {
 488         struct device *dev = &pdev->dev;
 489         struct sprd_i2c *i2c_dev;
 490         struct resource *res;
 491         u32 prop;
 492         int ret;
 493
 494         pdev->id = of_alias_get_id(dev->of_node, "i2c");
 495
 496         i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
 497         if (!i2c_dev)
 498                 return -ENOMEM;
 499
 500         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 501         i2c_dev->base = devm_ioremap_resource(dev, res);
 502         if (IS_ERR(i2c_dev->base))
 503                 return PTR_ERR(i2c_dev->base);
 504
 505         i2c_dev->irq = platform_get_irq(pdev, 0);
 506         if (i2c_dev->irq < 0) {
 507                 dev_err(&pdev->dev, "failed to get irq resource\n");
 508                 return i2c_dev->irq;
 509         }
 510
 511         i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
 512         init_completion(&i2c_dev->complete);
 513         snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
 514                  "%s", "sprd-i2c");
 515
 516         i2c_dev->bus_freq = 100000;
 517         i2c_dev->adap.owner = THIS_MODULE;
 518         i2c_dev->dev = dev;
 519         i2c_dev->adap.retries = 3;
 520         i2c_dev->adap.algo = &sprd_i2c_algo;
 521         i2c_dev->adap.algo_data = i2c_dev;
 522         i2c_dev->adap.dev.parent = dev;
 523         i2c_dev->adap.nr = pdev->id;
 524         i2c_dev->adap.dev.of_node = dev->of_node;
 525
 526         if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
 527                 i2c_dev->bus_freq = prop;
 528
 529         /* We only support 100k and 400k now, otherwise will return error. */
 530         if (i2c_dev->bus_freq != 100000 && i2c_dev->bus_freq != 400000)
 531                 return -EINVAL;
 532
 533         sprd_i2c_clk_init(i2c_dev);
 534         platform_set_drvdata(pdev, i2c_dev);
 535
 536         ret = clk_prepare_enable(i2c_dev->clk);
 537         if (ret)
 538                 return ret;
 539
 540         sprd_i2c_enable(i2c_dev);
 541
 542         pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
 543         pm_runtime_use_autosuspend(i2c_dev->dev);
 544         pm_runtime_set_active(i2c_dev->dev);
 545         pm_runtime_enable(i2c_dev->dev);
 546
 547         ret = pm_runtime_get_sync(i2c_dev->dev);
 548         if (ret < 0)
 549                 goto err_rpm_put;
 550
 551         ret = devm_request_threaded_irq(dev, i2c_dev->irq,
 552                 sprd_i2c_isr, sprd_i2c_isr_thread,
 553                 IRQF_NO_SUSPEND | IRQF_ONESHOT,
 554                 pdev->name, i2c_dev);
 555         if (ret) {
 556                 dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
 557                 goto err_rpm_put;
 558         }
 559
 560         ret = i2c_add_numbered_adapter(&i2c_dev->adap);
 561         if (ret) {
 562                 dev_err(&pdev->dev, "add adapter failed\n");
 563                 goto err_rpm_put;
 564         }
 565
 566         pm_runtime_mark_last_busy(i2c_dev->dev);
 567         pm_runtime_put_autosuspend(i2c_dev->dev);
 568         return 0;
 569
 570 err_rpm_put:
 571         pm_runtime_put_noidle(i2c_dev->dev);
 572         pm_runtime_disable(i2c_dev->dev);
 573         clk_disable_unprepare(i2c_dev->clk);
 574         return ret;
 575 }
 576
 577 static int sprd_i2c_remove(struct platform_device *pdev)
 578 {
 579         struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
 580         int ret;
 581
 582         ret = pm_runtime_get_sync(i2c_dev->dev);
 583         if (ret < 0)
 584                 return ret;
 585
 586         i2c_del_adapter(&i2c_dev->adap);
 587         clk_disable_unprepare(i2c_dev->clk);
 588
 589         pm_runtime_put_noidle(i2c_dev->dev);
 590         pm_runtime_disable(i2c_dev->dev);
 591
 592         return 0;
 593 }
 594
 595 static int __maybe_unused sprd_i2c_suspend_noirq(struct device *pdev)
 596 {
 597         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 598
 599         i2c_lock_adapter(&i2c_dev->adap);
 600         i2c_dev->is_suspended = true;
 601         i2c_unlock_adapter(&i2c_dev->adap);
 602
 603         return pm_runtime_force_suspend(pdev);
 604 }
 605
 606 static int __maybe_unused sprd_i2c_resume_noirq(struct device *pdev)
 607 {
 608         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 609
 610         i2c_lock_adapter(&i2c_dev->adap);
 611         i2c_dev->is_suspended = false;
 612         i2c_unlock_adapter(&i2c_dev->adap);
 613
 614         return pm_runtime_force_resume(pdev);
 615 }
 616
 617 static int __maybe_unused sprd_i2c_runtime_suspend(struct device *pdev)
 618 {
 619         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 620
 621         clk_disable_unprepare(i2c_dev->clk);
 622
 623         return 0;
 624 }
 625
 626 static int __maybe_unused sprd_i2c_runtime_resume(struct device *pdev)
 627 {
 628         struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
 629         int ret;
 630
 631         ret = clk_prepare_enable(i2c_dev->clk);
 632         if (ret)
 633                 return ret;
 634
 635         sprd_i2c_enable(i2c_dev);
 636
 637         return 0;
 638 }
 639
 640 static const struct dev_pm_ops sprd_i2c_pm_ops = {
 641         SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
 642                            sprd_i2c_runtime_resume, NULL)
 643
 644         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
 645                                       sprd_i2c_resume_noirq)
 646 };
 647
 648 static const struct of_device_id sprd_i2c_of_match[] = {
 649         { .compatible = "sprd,sc9860-i2c", },
 650         {},
 651 };
 652
 653 static struct platform_driver sprd_i2c_driver = {
 654         .probe = sprd_i2c_probe,
 655         .remove = sprd_i2c_remove,
 656         .driver = {
 657                    .name = "sprd-i2c",
 658                    .of_match_table = sprd_i2c_of_match,
 659                    .pm = &sprd_i2c_pm_ops,
 660         },
 661 };
 662
 663 static int sprd_i2c_init(void)
 664 {
 665         return platform_driver_register(&sprd_i2c_driver);
 666 }
 667 arch_initcall_sync(sprd_i2c_init);