2 * Copyright (C) 2017 Spreadtrum Communications Inc.
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <linux/delay.h>
11 #include <linux/i2c.h>
12 #include <linux/init.h>
13 #include <linux/interrupt.h>
14 #include <linux/kernel.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
21 #define I2C_ADDR_CFG 0x04
22 #define I2C_COUNT 0x08
25 #define I2C_STATUS 0x14
26 #define I2C_HSMODE_CFG 0x18
27 #define I2C_VERSION 0x1c
28 #define ADDR_DVD0 0x20
29 #define ADDR_DVD1 0x24
30 #define ADDR_STA0_DVD 0x28
34 #define STP_EN BIT(20)
35 #define FIFO_AF_LVL_MASK GENMASK(19, 16)
36 #define FIFO_AF_LVL 16
37 #define FIFO_AE_LVL_MASK GENMASK(15, 12)
38 #define FIFO_AE_LVL 12
39 #define I2C_DMA_EN BIT(11)
40 #define FULL_INTEN BIT(10)
41 #define EMPTY_INTEN BIT(9)
42 #define I2C_DVD_OPT BIT(8)
43 #define I2C_OUT_OPT BIT(7)
44 #define I2C_TRIM_OPT BIT(6)
45 #define I2C_HS_MODE BIT(4)
46 #define I2C_MODE BIT(3)
48 #define I2C_INT_EN BIT(1)
49 #define I2C_START BIT(0)
52 #define SDA_IN BIT(21)
53 #define SCL_IN BIT(20)
54 #define FIFO_FULL BIT(4)
55 #define FIFO_EMPTY BIT(3)
56 #define I2C_INT BIT(2)
57 #define I2C_RX_ACK BIT(1)
58 #define I2C_BUSY BIT(0)
61 #define I2C_RST BIT(0)
63 #define I2C_FIFO_DEEP 12
64 #define I2C_FIFO_FULL_THLD 15
65 #define I2C_FIFO_EMPTY_THLD 4
66 #define I2C_DATA_STEP 8
67 #define I2C_ADDR_DVD0_CALC(high, low) \
68 ((((high) & GENMASK(15, 0)) << 16) | ((low) & GENMASK(15, 0)))
69 #define I2C_ADDR_DVD1_CALC(high, low) \
70 (((high) & GENMASK(31, 16)) | (((low) & GENMASK(31, 16)) >> 16))
72 /* timeout (ms) for pm runtime autosuspend */
73 #define SPRD_I2C_PM_TIMEOUT 1000
74 /* timeout (ms) for transfer message */
75 #define I2C_XFER_TIMEOUT 1000
77 /* SPRD i2c data structure */
79 struct i2c_adapter adap;
86 struct completion complete;
94 static void sprd_i2c_set_count(struct sprd_i2c *i2c_dev, u32 count)
96 writel(count, i2c_dev->base + I2C_COUNT);
99 static void sprd_i2c_send_stop(struct sprd_i2c *i2c_dev, int stop)
101 u32 tmp = readl(i2c_dev->base + I2C_CTL);
104 writel(tmp & ~STP_EN, i2c_dev->base + I2C_CTL);
106 writel(tmp | STP_EN, i2c_dev->base + I2C_CTL);
109 static void sprd_i2c_clear_start(struct sprd_i2c *i2c_dev)
111 u32 tmp = readl(i2c_dev->base + I2C_CTL);
113 writel(tmp & ~I2C_START, i2c_dev->base + I2C_CTL);
116 static void sprd_i2c_clear_ack(struct sprd_i2c *i2c_dev)
118 u32 tmp = readl(i2c_dev->base + I2C_STATUS);
120 writel(tmp & ~I2C_RX_ACK, i2c_dev->base + I2C_STATUS);
123 static void sprd_i2c_clear_irq(struct sprd_i2c *i2c_dev)
125 u32 tmp = readl(i2c_dev->base + I2C_STATUS);
127 writel(tmp & ~I2C_INT, i2c_dev->base + I2C_STATUS);
130 static void sprd_i2c_reset_fifo(struct sprd_i2c *i2c_dev)
132 writel(I2C_RST, i2c_dev->base + ADDR_RST);
135 static void sprd_i2c_set_devaddr(struct sprd_i2c *i2c_dev, struct i2c_msg *m)
137 writel(m->addr << 1, i2c_dev->base + I2C_ADDR_CFG);
140 static void sprd_i2c_write_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
144 for (i = 0; i < len; i++)
145 writeb(buf[i], i2c_dev->base + I2C_TX);
148 static void sprd_i2c_read_bytes(struct sprd_i2c *i2c_dev, u8 *buf, u32 len)
152 for (i = 0; i < len; i++)
153 buf[i] = readb(i2c_dev->base + I2C_RX);
156 static void sprd_i2c_set_full_thld(struct sprd_i2c *i2c_dev, u32 full_thld)
158 u32 tmp = readl(i2c_dev->base + I2C_CTL);
160 tmp &= ~FIFO_AF_LVL_MASK;
161 tmp |= full_thld << FIFO_AF_LVL;
162 writel(tmp, i2c_dev->base + I2C_CTL);
165 static void sprd_i2c_set_empty_thld(struct sprd_i2c *i2c_dev, u32 empty_thld)
167 u32 tmp = readl(i2c_dev->base + I2C_CTL);
169 tmp &= ~FIFO_AE_LVL_MASK;
170 tmp |= empty_thld << FIFO_AE_LVL;
171 writel(tmp, i2c_dev->base + I2C_CTL);
174 static void sprd_i2c_set_fifo_full_int(struct sprd_i2c *i2c_dev, int enable)
176 u32 tmp = readl(i2c_dev->base + I2C_CTL);
183 writel(tmp, i2c_dev->base + I2C_CTL);
186 static void sprd_i2c_set_fifo_empty_int(struct sprd_i2c *i2c_dev, int enable)
188 u32 tmp = readl(i2c_dev->base + I2C_CTL);
195 writel(tmp, i2c_dev->base + I2C_CTL);
198 static void sprd_i2c_opt_start(struct sprd_i2c *i2c_dev)
200 u32 tmp = readl(i2c_dev->base + I2C_CTL);
202 writel(tmp | I2C_START, i2c_dev->base + I2C_CTL);
205 static void sprd_i2c_opt_mode(struct sprd_i2c *i2c_dev, int rw)
207 u32 cmd = readl(i2c_dev->base + I2C_CTL) & ~I2C_MODE;
209 writel(cmd | rw << 3, i2c_dev->base + I2C_CTL);
212 static void sprd_i2c_data_transfer(struct sprd_i2c *i2c_dev)
214 u32 i2c_count = i2c_dev->count;
215 u32 need_tran = i2c_count <= I2C_FIFO_DEEP ? i2c_count : I2C_FIFO_DEEP;
216 struct i2c_msg *msg = i2c_dev->msg;
218 if (msg->flags & I2C_M_RD) {
219 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, I2C_FIFO_FULL_THLD);
220 i2c_dev->count -= I2C_FIFO_FULL_THLD;
221 i2c_dev->buf += I2C_FIFO_FULL_THLD;
224 * If the read data count is larger than rx fifo full threshold,
225 * we should enable the rx fifo full interrupt to read data
228 if (i2c_dev->count >= I2C_FIFO_FULL_THLD)
229 sprd_i2c_set_fifo_full_int(i2c_dev, 1);
231 sprd_i2c_write_bytes(i2c_dev, i2c_dev->buf, need_tran);
232 i2c_dev->buf += need_tran;
233 i2c_dev->count -= need_tran;
236 * If the write data count is arger than tx fifo depth which
237 * means we can not write all data in one time, then we should
238 * enable the tx fifo empty interrupt to write again.
240 if (i2c_count > I2C_FIFO_DEEP)
241 sprd_i2c_set_fifo_empty_int(i2c_dev, 1);
245 static int sprd_i2c_handle_msg(struct i2c_adapter *i2c_adap,
246 struct i2c_msg *msg, bool is_last_msg)
248 struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
249 unsigned long time_left;
252 i2c_dev->buf = msg->buf;
253 i2c_dev->count = msg->len;
255 reinit_completion(&i2c_dev->complete);
256 sprd_i2c_reset_fifo(i2c_dev);
257 sprd_i2c_set_devaddr(i2c_dev, msg);
258 sprd_i2c_set_count(i2c_dev, msg->len);
260 if (msg->flags & I2C_M_RD) {
261 sprd_i2c_opt_mode(i2c_dev, 1);
262 sprd_i2c_send_stop(i2c_dev, 1);
264 sprd_i2c_opt_mode(i2c_dev, 0);
265 sprd_i2c_send_stop(i2c_dev, !!is_last_msg);
269 * We should enable rx fifo full interrupt to get data when receiving
272 if (msg->flags & I2C_M_RD)
273 sprd_i2c_set_fifo_full_int(i2c_dev, 1);
275 sprd_i2c_data_transfer(i2c_dev);
277 sprd_i2c_opt_start(i2c_dev);
279 time_left = wait_for_completion_timeout(&i2c_dev->complete,
280 msecs_to_jiffies(I2C_XFER_TIMEOUT));
287 static int sprd_i2c_master_xfer(struct i2c_adapter *i2c_adap,
288 struct i2c_msg *msgs, int num)
290 struct sprd_i2c *i2c_dev = i2c_adap->algo_data;
293 if (i2c_dev->is_suspended)
296 ret = pm_runtime_get_sync(i2c_dev->dev);
300 for (im = 0; im < num - 1; im++) {
301 ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im], 0);
306 ret = sprd_i2c_handle_msg(i2c_adap, &msgs[im++], 1);
309 pm_runtime_mark_last_busy(i2c_dev->dev);
310 pm_runtime_put_autosuspend(i2c_dev->dev);
312 return ret < 0 ? ret : im;
315 static u32 sprd_i2c_func(struct i2c_adapter *adap)
317 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
320 static const struct i2c_algorithm sprd_i2c_algo = {
321 .master_xfer = sprd_i2c_master_xfer,
322 .functionality = sprd_i2c_func,
325 static void sprd_i2c_set_clk(struct sprd_i2c *i2c_dev, u32 freq)
327 u32 apb_clk = i2c_dev->src_clk;
329 * From I2C databook, the prescale calculation formula:
330 * prescale = freq_i2c / (4 * freq_scl) - 1;
332 u32 i2c_dvd = apb_clk / (4 * freq) - 1;
334 * From I2C databook, the high period of SCL clock is recommended as
335 * 40% (2/5), and the low period of SCL clock is recommended as 60%
336 * (3/5), then the formula should be:
337 * high = (prescale * 2 * 2) / 5
338 * low = (prescale * 2 * 3) / 5
340 u32 high = ((i2c_dvd << 1) * 2) / 5;
341 u32 low = ((i2c_dvd << 1) * 3) / 5;
342 u32 div0 = I2C_ADDR_DVD0_CALC(high, low);
343 u32 div1 = I2C_ADDR_DVD1_CALC(high, low);
345 writel(div0, i2c_dev->base + ADDR_DVD0);
346 writel(div1, i2c_dev->base + ADDR_DVD1);
348 /* Start hold timing = hold time(us) * source clock */
350 writel((6 * apb_clk) / 10000000, i2c_dev->base + ADDR_STA0_DVD);
351 else if (freq == 100000)
352 writel((4 * apb_clk) / 1000000, i2c_dev->base + ADDR_STA0_DVD);
355 static void sprd_i2c_enable(struct sprd_i2c *i2c_dev)
357 u32 tmp = I2C_DVD_OPT;
359 writel(tmp, i2c_dev->base + I2C_CTL);
361 sprd_i2c_set_full_thld(i2c_dev, I2C_FIFO_FULL_THLD);
362 sprd_i2c_set_empty_thld(i2c_dev, I2C_FIFO_EMPTY_THLD);
364 sprd_i2c_set_clk(i2c_dev, i2c_dev->bus_freq);
365 sprd_i2c_reset_fifo(i2c_dev);
366 sprd_i2c_clear_irq(i2c_dev);
368 tmp = readl(i2c_dev->base + I2C_CTL);
369 writel(tmp | I2C_EN | I2C_INT_EN, i2c_dev->base + I2C_CTL);
372 static irqreturn_t sprd_i2c_isr_thread(int irq, void *dev_id)
374 struct sprd_i2c *i2c_dev = dev_id;
375 struct i2c_msg *msg = i2c_dev->msg;
376 bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
379 if (msg->flags & I2C_M_RD)
380 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
382 i2c_tran = i2c_dev->count;
385 * If we got one ACK from slave when writing data, and we did not
386 * finish this transmission (i2c_tran is not zero), then we should
387 * continue to write data.
389 * For reading data, ack is always true, if i2c_tran is not 0 which
390 * means we still need to contine to read data from slave.
392 if (i2c_tran && ack) {
393 sprd_i2c_data_transfer(i2c_dev);
400 * If we did not get one ACK from slave when writing data, we should
401 * return -EIO to notify users.
405 else if (msg->flags & I2C_M_RD && i2c_dev->count)
406 sprd_i2c_read_bytes(i2c_dev, i2c_dev->buf, i2c_dev->count);
408 /* Transmission is done and clear ack and start operation */
409 sprd_i2c_clear_ack(i2c_dev);
410 sprd_i2c_clear_start(i2c_dev);
411 complete(&i2c_dev->complete);
416 static irqreturn_t sprd_i2c_isr(int irq, void *dev_id)
418 struct sprd_i2c *i2c_dev = dev_id;
419 struct i2c_msg *msg = i2c_dev->msg;
420 bool ack = !(readl(i2c_dev->base + I2C_STATUS) & I2C_RX_ACK);
423 if (msg->flags & I2C_M_RD)
424 i2c_tran = i2c_dev->count >= I2C_FIFO_FULL_THLD;
426 i2c_tran = i2c_dev->count;
429 * If we did not get one ACK from slave when writing data, then we
430 * should finish this transmission since we got some errors.
432 * When writing data, if i2c_tran == 0 which means we have writen
433 * done all data, then we can finish this transmission.
435 * When reading data, if conut < rx fifo full threshold, which
436 * means we can read all data in one time, then we can finish this
439 if (!i2c_tran || !ack) {
440 sprd_i2c_clear_start(i2c_dev);
441 sprd_i2c_clear_irq(i2c_dev);
444 sprd_i2c_set_fifo_empty_int(i2c_dev, 0);
445 sprd_i2c_set_fifo_full_int(i2c_dev, 0);
447 return IRQ_WAKE_THREAD;
450 static int sprd_i2c_clk_init(struct sprd_i2c *i2c_dev)
452 struct clk *clk_i2c, *clk_parent;
454 clk_i2c = devm_clk_get(i2c_dev->dev, "i2c");
455 if (IS_ERR(clk_i2c)) {
456 dev_warn(i2c_dev->dev, "i2c%d can't get the i2c clock\n",
461 clk_parent = devm_clk_get(i2c_dev->dev, "source");
462 if (IS_ERR(clk_parent)) {
463 dev_warn(i2c_dev->dev, "i2c%d can't get the source clock\n",
468 if (clk_set_parent(clk_i2c, clk_parent))
469 i2c_dev->src_clk = clk_get_rate(clk_i2c);
471 i2c_dev->src_clk = 26000000;
473 dev_dbg(i2c_dev->dev, "i2c%d set source clock is %d\n",
474 i2c_dev->adap.nr, i2c_dev->src_clk);
476 i2c_dev->clk = devm_clk_get(i2c_dev->dev, "enable");
477 if (IS_ERR(i2c_dev->clk)) {
478 dev_warn(i2c_dev->dev, "i2c%d can't get the enable clock\n",
486 static int sprd_i2c_probe(struct platform_device *pdev)
488 struct device *dev = &pdev->dev;
489 struct sprd_i2c *i2c_dev;
490 struct resource *res;
494 pdev->id = of_alias_get_id(dev->of_node, "i2c");
496 i2c_dev = devm_kzalloc(dev, sizeof(struct sprd_i2c), GFP_KERNEL);
500 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
501 i2c_dev->base = devm_ioremap_resource(dev, res);
502 if (IS_ERR(i2c_dev->base))
503 return PTR_ERR(i2c_dev->base);
505 i2c_dev->irq = platform_get_irq(pdev, 0);
506 if (i2c_dev->irq < 0) {
507 dev_err(&pdev->dev, "failed to get irq resource\n");
511 i2c_set_adapdata(&i2c_dev->adap, i2c_dev);
512 init_completion(&i2c_dev->complete);
513 snprintf(i2c_dev->adap.name, sizeof(i2c_dev->adap.name),
516 i2c_dev->bus_freq = 100000;
517 i2c_dev->adap.owner = THIS_MODULE;
519 i2c_dev->adap.retries = 3;
520 i2c_dev->adap.algo = &sprd_i2c_algo;
521 i2c_dev->adap.algo_data = i2c_dev;
522 i2c_dev->adap.dev.parent = dev;
523 i2c_dev->adap.nr = pdev->id;
524 i2c_dev->adap.dev.of_node = dev->of_node;
526 if (!of_property_read_u32(dev->of_node, "clock-frequency", &prop))
527 i2c_dev->bus_freq = prop;
529 /* We only support 100k and 400k now, otherwise will return error. */
530 if (i2c_dev->bus_freq != 100000 && i2c_dev->bus_freq != 400000)
533 sprd_i2c_clk_init(i2c_dev);
534 platform_set_drvdata(pdev, i2c_dev);
536 ret = clk_prepare_enable(i2c_dev->clk);
540 sprd_i2c_enable(i2c_dev);
542 pm_runtime_set_autosuspend_delay(i2c_dev->dev, SPRD_I2C_PM_TIMEOUT);
543 pm_runtime_use_autosuspend(i2c_dev->dev);
544 pm_runtime_set_active(i2c_dev->dev);
545 pm_runtime_enable(i2c_dev->dev);
547 ret = pm_runtime_get_sync(i2c_dev->dev);
551 ret = devm_request_threaded_irq(dev, i2c_dev->irq,
552 sprd_i2c_isr, sprd_i2c_isr_thread,
553 IRQF_NO_SUSPEND | IRQF_ONESHOT,
554 pdev->name, i2c_dev);
556 dev_err(&pdev->dev, "failed to request irq %d\n", i2c_dev->irq);
560 ret = i2c_add_numbered_adapter(&i2c_dev->adap);
562 dev_err(&pdev->dev, "add adapter failed\n");
566 pm_runtime_mark_last_busy(i2c_dev->dev);
567 pm_runtime_put_autosuspend(i2c_dev->dev);
571 pm_runtime_put_noidle(i2c_dev->dev);
572 pm_runtime_disable(i2c_dev->dev);
573 clk_disable_unprepare(i2c_dev->clk);
577 static int sprd_i2c_remove(struct platform_device *pdev)
579 struct sprd_i2c *i2c_dev = platform_get_drvdata(pdev);
582 ret = pm_runtime_get_sync(i2c_dev->dev);
586 i2c_del_adapter(&i2c_dev->adap);
587 clk_disable_unprepare(i2c_dev->clk);
589 pm_runtime_put_noidle(i2c_dev->dev);
590 pm_runtime_disable(i2c_dev->dev);
595 static int __maybe_unused sprd_i2c_suspend_noirq(struct device *pdev)
597 struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
599 i2c_lock_adapter(&i2c_dev->adap);
600 i2c_dev->is_suspended = true;
601 i2c_unlock_adapter(&i2c_dev->adap);
603 return pm_runtime_force_suspend(pdev);
606 static int __maybe_unused sprd_i2c_resume_noirq(struct device *pdev)
608 struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
610 i2c_lock_adapter(&i2c_dev->adap);
611 i2c_dev->is_suspended = false;
612 i2c_unlock_adapter(&i2c_dev->adap);
614 return pm_runtime_force_resume(pdev);
617 static int __maybe_unused sprd_i2c_runtime_suspend(struct device *pdev)
619 struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
621 clk_disable_unprepare(i2c_dev->clk);
626 static int __maybe_unused sprd_i2c_runtime_resume(struct device *pdev)
628 struct sprd_i2c *i2c_dev = dev_get_drvdata(pdev);
631 ret = clk_prepare_enable(i2c_dev->clk);
635 sprd_i2c_enable(i2c_dev);
640 static const struct dev_pm_ops sprd_i2c_pm_ops = {
641 SET_RUNTIME_PM_OPS(sprd_i2c_runtime_suspend,
642 sprd_i2c_runtime_resume, NULL)
644 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(sprd_i2c_suspend_noirq,
645 sprd_i2c_resume_noirq)
648 static const struct of_device_id sprd_i2c_of_match[] = {
649 { .compatible = "sprd,sc9860-i2c", },
653 static struct platform_driver sprd_i2c_driver = {
654 .probe = sprd_i2c_probe,
655 .remove = sprd_i2c_remove,
658 .of_match_table = sprd_i2c_of_match,
659 .pm = &sprd_i2c_pm_ops,
663 static int sprd_i2c_init(void)
665 return platform_driver_register(&sprd_i2c_driver);
667 arch_initcall_sync(sprd_i2c_init);