drivers/i2c/busses/i2c-s3c2410.c

   1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
   2  *
   3  * Copyright (C) 2004,2005,2009 Simtec Electronics
   4  *      Ben Dooks <ben@simtec.co.uk>
   5  *
   6  * S3C2410 I2C Controller
   7  *
   8  * This program is free software; you can redistribute it and/or modify
   9  * it under the terms of the GNU General Public License as published by
  10  * the Free Software Foundation; either version 2 of the License, or
  11  * (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17 */
  18
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21
  22 #include <linux/i2c.h>
  23 #include <linux/init.h>
  24 #include <linux/time.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/err.h>
  29 #include <linux/platform_device.h>
  30 #include <linux/pm_runtime.h>
  31 #include <linux/clk.h>
  32 #include <linux/cpufreq.h>
  33 #include <linux/slab.h>
  34 #include <linux/io.h>
  35 #include <linux/of.h>
  36 #include <linux/of_gpio.h>
  37 #include <linux/pinctrl/consumer.h>
  38 #include <linux/mfd/syscon.h>
  39 #include <linux/regmap.h>
  40
  41 #include <asm/irq.h>
  42
  43 #include <linux/platform_data/i2c-s3c2410.h>
  44
  45 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
  46
  47 #define S3C2410_IICCON                  0x00
  48 #define S3C2410_IICSTAT                 0x04
  49 #define S3C2410_IICADD                  0x08
  50 #define S3C2410_IICDS                   0x0C
  51 #define S3C2440_IICLC                   0x10
  52
  53 #define S3C2410_IICCON_ACKEN            (1 << 7)
  54 #define S3C2410_IICCON_TXDIV_16         (0 << 6)
  55 #define S3C2410_IICCON_TXDIV_512        (1 << 6)
  56 #define S3C2410_IICCON_IRQEN            (1 << 5)
  57 #define S3C2410_IICCON_IRQPEND          (1 << 4)
  58 #define S3C2410_IICCON_SCALE(x)         ((x) & 0xf)
  59 #define S3C2410_IICCON_SCALEMASK        (0xf)
  60
  61 #define S3C2410_IICSTAT_MASTER_RX       (2 << 6)
  62 #define S3C2410_IICSTAT_MASTER_TX       (3 << 6)
  63 #define S3C2410_IICSTAT_SLAVE_RX        (0 << 6)
  64 #define S3C2410_IICSTAT_SLAVE_TX        (1 << 6)
  65 #define S3C2410_IICSTAT_MODEMASK        (3 << 6)
  66
  67 #define S3C2410_IICSTAT_START           (1 << 5)
  68 #define S3C2410_IICSTAT_BUSBUSY         (1 << 5)
  69 #define S3C2410_IICSTAT_TXRXEN          (1 << 4)
  70 #define S3C2410_IICSTAT_ARBITR          (1 << 3)
  71 #define S3C2410_IICSTAT_ASSLAVE         (1 << 2)
  72 #define S3C2410_IICSTAT_ADDR0           (1 << 1)
  73 #define S3C2410_IICSTAT_LASTBIT         (1 << 0)
  74
  75 #define S3C2410_IICLC_SDA_DELAY0        (0 << 0)
  76 #define S3C2410_IICLC_SDA_DELAY5        (1 << 0)
  77 #define S3C2410_IICLC_SDA_DELAY10       (2 << 0)
  78 #define S3C2410_IICLC_SDA_DELAY15       (3 << 0)
  79 #define S3C2410_IICLC_SDA_DELAY_MASK    (3 << 0)
  80
  81 #define S3C2410_IICLC_FILTER_ON         (1 << 2)
  82
  83 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
  84 #define QUIRK_S3C2440           (1 << 0)
  85 #define QUIRK_HDMIPHY           (1 << 1)
  86 #define QUIRK_NO_GPIO           (1 << 2)
  87 #define QUIRK_POLL              (1 << 3)
  88
  89 /* Max time to wait for bus to become idle after a xfer (in us) */
  90 #define S3C2410_IDLE_TIMEOUT    5000
  91
  92 /* Exynos5 Sysreg offset */
  93 #define EXYNOS5_SYS_I2C_CFG     0x0234
  94
  95 /* i2c controller state */
  96 enum s3c24xx_i2c_state {
  97         STATE_IDLE,
  98         STATE_START,
  99         STATE_READ,
 100         STATE_WRITE,
 101         STATE_STOP
 102 };
 103
 104 struct s3c24xx_i2c {
 105         wait_queue_head_t       wait;
 106         kernel_ulong_t          quirks;
 107         unsigned int            suspended:1;
 108
 109         struct i2c_msg          *msg;
 110         unsigned int            msg_num;
 111         unsigned int            msg_idx;
 112         unsigned int            msg_ptr;
 113
 114         unsigned int            tx_setup;
 115         unsigned int            irq;
 116
 117         enum s3c24xx_i2c_state  state;
 118         unsigned long           clkrate;
 119
 120         void __iomem            *regs;
 121         struct clk              *clk;
 122         struct device           *dev;
 123         struct i2c_adapter      adap;
 124
 125         struct s3c2410_platform_i2c     *pdata;
 126         int                     gpios[2];
 127         struct pinctrl          *pctrl;
 128 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 129         struct notifier_block   freq_transition;
 130 #endif
 131         struct regmap           *sysreg;
 132         unsigned int            sys_i2c_cfg;
 133 };
 134
 135 static const struct platform_device_id s3c24xx_driver_ids[] = {
 136         {
 137                 .name           = "s3c2410-i2c",
 138                 .driver_data    = 0,
 139         }, {
 140                 .name           = "s3c2440-i2c",
 141                 .driver_data    = QUIRK_S3C2440,
 142         }, {
 143                 .name           = "s3c2440-hdmiphy-i2c",
 144                 .driver_data    = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
 145         }, { },
 146 };
 147 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
 148
 149 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
 150
 151 #ifdef CONFIG_OF
 152 static const struct of_device_id s3c24xx_i2c_match[] = {
 153         { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
 154         { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
 155         { .compatible = "samsung,s3c2440-hdmiphy-i2c",
 156           .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
 157         { .compatible = "samsung,exynos5-sata-phy-i2c",
 158           .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
 159         {},
 160 };
 161 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
 162 #endif
 163
 164 /*
 165  * Get controller type either from device tree or platform device variant.
 166  */
 167 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
 168 {
 169         if (pdev->dev.of_node) {
 170                 const struct of_device_id *match;
 171
 172                 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
 173                 return (kernel_ulong_t)match->data;
 174         }
 175
 176         return platform_get_device_id(pdev)->driver_data;
 177 }
 178
 179 /*
 180  * Complete the message and wake up the caller, using the given return code,
 181  * or zero to mean ok.
 182  */
 183 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
 184 {
 185         dev_dbg(i2c->dev, "master_complete %d\n", ret);
 186
 187         i2c->msg_ptr = 0;
 188         i2c->msg = NULL;
 189         i2c->msg_idx++;
 190         i2c->msg_num = 0;
 191         if (ret)
 192                 i2c->msg_idx = ret;
 193
 194         if (!(i2c->quirks & QUIRK_POLL))
 195                 wake_up(&i2c->wait);
 196 }
 197
 198 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
 199 {
 200         unsigned long tmp;
 201
 202         tmp = readl(i2c->regs + S3C2410_IICCON);
 203         writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 204 }
 205
 206 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
 207 {
 208         unsigned long tmp;
 209
 210         tmp = readl(i2c->regs + S3C2410_IICCON);
 211         writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
 212 }
 213
 214 /* irq enable/disable functions */
 215 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
 216 {
 217         unsigned long tmp;
 218
 219         tmp = readl(i2c->regs + S3C2410_IICCON);
 220         writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 221 }
 222
 223 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
 224 {
 225         unsigned long tmp;
 226
 227         tmp = readl(i2c->regs + S3C2410_IICCON);
 228         writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
 229 }
 230
 231 static bool is_ack(struct s3c24xx_i2c *i2c)
 232 {
 233         int tries;
 234
 235         for (tries = 50; tries; --tries) {
 236                 if (readl(i2c->regs + S3C2410_IICCON)
 237                         & S3C2410_IICCON_IRQPEND) {
 238                         if (!(readl(i2c->regs + S3C2410_IICSTAT)
 239                                 & S3C2410_IICSTAT_LASTBIT))
 240                                 return true;
 241                 }
 242                 usleep_range(1000, 2000);
 243         }
 244         dev_err(i2c->dev, "ack was not received\n");
 245         return false;
 246 }
 247
 248 /*
 249  * put the start of a message onto the bus
 250  */
 251 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
 252                                       struct i2c_msg *msg)
 253 {
 254         unsigned int addr = (msg->addr & 0x7f) << 1;
 255         unsigned long stat;
 256         unsigned long iiccon;
 257
 258         stat = 0;
 259         stat |=  S3C2410_IICSTAT_TXRXEN;
 260
 261         if (msg->flags & I2C_M_RD) {
 262                 stat |= S3C2410_IICSTAT_MASTER_RX;
 263                 addr |= 1;
 264         } else
 265                 stat |= S3C2410_IICSTAT_MASTER_TX;
 266
 267         if (msg->flags & I2C_M_REV_DIR_ADDR)
 268                 addr ^= 1;
 269
 270         /* todo - check for whether ack wanted or not */
 271         s3c24xx_i2c_enable_ack(i2c);
 272
 273         iiccon = readl(i2c->regs + S3C2410_IICCON);
 274         writel(stat, i2c->regs + S3C2410_IICSTAT);
 275
 276         dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
 277         writeb(addr, i2c->regs + S3C2410_IICDS);
 278
 279         /*
 280          * delay here to ensure the data byte has gotten onto the bus
 281          * before the transaction is started
 282          */
 283         ndelay(i2c->tx_setup);
 284
 285         dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
 286         writel(iiccon, i2c->regs + S3C2410_IICCON);
 287
 288         stat |= S3C2410_IICSTAT_START;
 289         writel(stat, i2c->regs + S3C2410_IICSTAT);
 290
 291         if (i2c->quirks & QUIRK_POLL) {
 292                 while ((i2c->msg_num != 0) && is_ack(i2c)) {
 293                         i2c_s3c_irq_nextbyte(i2c, stat);
 294                         stat = readl(i2c->regs + S3C2410_IICSTAT);
 295
 296                         if (stat & S3C2410_IICSTAT_ARBITR)
 297                                 dev_err(i2c->dev, "deal with arbitration loss\n");
 298                 }
 299         }
 300 }
 301
 302 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
 303 {
 304         unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 305
 306         dev_dbg(i2c->dev, "STOP\n");
 307
 308         /*
 309          * The datasheet says that the STOP sequence should be:
 310          *  1) I2CSTAT.5 = 0    - Clear BUSY (or 'generate STOP')
 311          *  2) I2CCON.4 = 0     - Clear IRQPEND
 312          *  3) Wait until the stop condition takes effect.
 313          *  4*) I2CSTAT.4 = 0   - Clear TXRXEN
 314          *
 315          * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
 316          *
 317          * However, after much experimentation, it appears that:
 318          * a) normal buses automatically clear BUSY and transition from
 319          *    Master->Slave when they complete generating a STOP condition.
 320          *    Therefore, step (3) can be done in doxfer() by polling I2CCON.4
 321          *    after starting the STOP generation here.
 322          * b) HDMIPHY bus does neither, so there is no way to do step 3.
 323          *    There is no indication when this bus has finished generating
 324          *    STOP.
 325          *
 326          * In fact, we have found that as soon as the IRQPEND bit is cleared in
 327          * step 2, the HDMIPHY bus generates the STOP condition, and then
 328          * immediately starts transferring another data byte, even though the
 329          * bus is supposedly stopped.  This is presumably because the bus is
 330          * still in "Master" mode, and its BUSY bit is still set.
 331          *
 332          * To avoid these extra post-STOP transactions on HDMI phy devices, we
 333          * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
 334          * instead of first generating a proper STOP condition.  This should
 335          * float SDA & SCK terminating the transfer.  Subsequent transfers
 336          *  start with a proper START condition, and proceed normally.
 337          *
 338          * The HDMIPHY bus is an internal bus that always has exactly two
 339          * devices, the host as Master and the HDMIPHY device as the slave.
 340          * Skipping the STOP condition has been tested on this bus and works.
 341          */
 342         if (i2c->quirks & QUIRK_HDMIPHY) {
 343                 /* Stop driving the I2C pins */
 344                 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
 345         } else {
 346                 /* stop the transfer */
 347                 iicstat &= ~S3C2410_IICSTAT_START;
 348         }
 349         writel(iicstat, i2c->regs + S3C2410_IICSTAT);
 350
 351         i2c->state = STATE_STOP;
 352
 353         s3c24xx_i2c_master_complete(i2c, ret);
 354         s3c24xx_i2c_disable_irq(i2c);
 355 }
 356
 357 /*
 358  * helper functions to determine the current state in the set of
 359  * messages we are sending
 360  */
 361
 362 /*
 363  * returns TRUE if the current message is the last in the set
 364  */
 365 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
 366 {
 367         return i2c->msg_idx >= (i2c->msg_num - 1);
 368 }
 369
 370 /*
 371  * returns TRUE if we this is the last byte in the current message
 372  */
 373 static inline int is_msglast(struct s3c24xx_i2c *i2c)
 374 {
 375         /*
 376          * msg->len is always 1 for the first byte of smbus block read.
 377          * Actual length will be read from slave. More bytes will be
 378          * read according to the length then.
 379          */
 380         if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 381                 return 0;
 382
 383         return i2c->msg_ptr == i2c->msg->len-1;
 384 }
 385
 386 /*
 387  * returns TRUE if we reached the end of the current message
 388  */
 389 static inline int is_msgend(struct s3c24xx_i2c *i2c)
 390 {
 391         return i2c->msg_ptr >= i2c->msg->len;
 392 }
 393
 394 /*
 395  * process an interrupt and work out what to do
 396  */
 397 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
 398 {
 399         unsigned long tmp;
 400         unsigned char byte;
 401         int ret = 0;
 402
 403         switch (i2c->state) {
 404
 405         case STATE_IDLE:
 406                 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
 407                 goto out;
 408
 409         case STATE_STOP:
 410                 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
 411                 s3c24xx_i2c_disable_irq(i2c);
 412                 goto out_ack;
 413
 414         case STATE_START:
 415                 /*
 416                  * last thing we did was send a start condition on the
 417                  * bus, or started a new i2c message
 418                  */
 419                 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
 420                     !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 421                         /* ack was not received... */
 422                         dev_dbg(i2c->dev, "ack was not received\n");
 423                         s3c24xx_i2c_stop(i2c, -ENXIO);
 424                         goto out_ack;
 425                 }
 426
 427                 if (i2c->msg->flags & I2C_M_RD)
 428                         i2c->state = STATE_READ;
 429                 else
 430                         i2c->state = STATE_WRITE;
 431
 432                 /*
 433                  * Terminate the transfer if there is nothing to do
 434                  * as this is used by the i2c probe to find devices.
 435                  */
 436                 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
 437                         s3c24xx_i2c_stop(i2c, 0);
 438                         goto out_ack;
 439                 }
 440
 441                 if (i2c->state == STATE_READ)
 442                         goto prepare_read;
 443
 444                 /*
 445                  * fall through to the write state, as we will need to
 446                  * send a byte as well
 447                  */
 448
 449         case STATE_WRITE:
 450                 /*
 451                  * we are writing data to the device... check for the
 452                  * end of the message, and if so, work out what to do
 453                  */
 454                 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
 455                         if (iicstat & S3C2410_IICSTAT_LASTBIT) {
 456                                 dev_dbg(i2c->dev, "WRITE: No Ack\n");
 457
 458                                 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
 459                                 goto out_ack;
 460                         }
 461                 }
 462
 463  retry_write:
 464
 465                 if (!is_msgend(i2c)) {
 466                         byte = i2c->msg->buf[i2c->msg_ptr++];
 467                         writeb(byte, i2c->regs + S3C2410_IICDS);
 468
 469                         /*
 470                          * delay after writing the byte to allow the
 471                          * data setup time on the bus, as writing the
 472                          * data to the register causes the first bit
 473                          * to appear on SDA, and SCL will change as
 474                          * soon as the interrupt is acknowledged
 475                          */
 476                         ndelay(i2c->tx_setup);
 477
 478                 } else if (!is_lastmsg(i2c)) {
 479                         /* we need to go to the next i2c message */
 480
 481                         dev_dbg(i2c->dev, "WRITE: Next Message\n");
 482
 483                         i2c->msg_ptr = 0;
 484                         i2c->msg_idx++;
 485                         i2c->msg++;
 486
 487                         /* check to see if we need to do another message */
 488                         if (i2c->msg->flags & I2C_M_NOSTART) {
 489
 490                                 if (i2c->msg->flags & I2C_M_RD) {
 491                                         /*
 492                                          * cannot do this, the controller
 493                                          * forces us to send a new START
 494                                          * when we change direction
 495                                          */
 496                                         dev_dbg(i2c->dev,
 497                                                 "missing START before write->read\n");
 498                                         s3c24xx_i2c_stop(i2c, -EINVAL);
 499                                         break;
 500                                 }
 501
 502                                 goto retry_write;
 503                         } else {
 504                                 /* send the new start */
 505                                 s3c24xx_i2c_message_start(i2c, i2c->msg);
 506                                 i2c->state = STATE_START;
 507                         }
 508
 509                 } else {
 510                         /* send stop */
 511                         s3c24xx_i2c_stop(i2c, 0);
 512                 }
 513                 break;
 514
 515         case STATE_READ:
 516                 /*
 517                  * we have a byte of data in the data register, do
 518                  * something with it, and then work out whether we are
 519                  * going to do any more read/write
 520                  */
 521                 byte = readb(i2c->regs + S3C2410_IICDS);
 522                 i2c->msg->buf[i2c->msg_ptr++] = byte;
 523
 524                 /* Add actual length to read for smbus block read */
 525                 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
 526                         i2c->msg->len += byte;
 527  prepare_read:
 528                 if (is_msglast(i2c)) {
 529                         /* last byte of buffer */
 530
 531                         if (is_lastmsg(i2c))
 532                                 s3c24xx_i2c_disable_ack(i2c);
 533
 534                 } else if (is_msgend(i2c)) {
 535                         /*
 536                          * ok, we've read the entire buffer, see if there
 537                          * is anything else we need to do
 538                          */
 539                         if (is_lastmsg(i2c)) {
 540                                 /* last message, send stop and complete */
 541                                 dev_dbg(i2c->dev, "READ: Send Stop\n");
 542
 543                                 s3c24xx_i2c_stop(i2c, 0);
 544                         } else {
 545                                 /* go to the next transfer */
 546                                 dev_dbg(i2c->dev, "READ: Next Transfer\n");
 547
 548                                 i2c->msg_ptr = 0;
 549                                 i2c->msg_idx++;
 550                                 i2c->msg++;
 551                         }
 552                 }
 553
 554                 break;
 555         }
 556
 557         /* acknowlegde the IRQ and get back on with the work */
 558
 559  out_ack:
 560         tmp = readl(i2c->regs + S3C2410_IICCON);
 561         tmp &= ~S3C2410_IICCON_IRQPEND;
 562         writel(tmp, i2c->regs + S3C2410_IICCON);
 563  out:
 564         return ret;
 565 }
 566
 567 /*
 568  * top level IRQ servicing routine
 569  */
 570 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
 571 {
 572         struct s3c24xx_i2c *i2c = dev_id;
 573         unsigned long status;
 574         unsigned long tmp;
 575
 576         status = readl(i2c->regs + S3C2410_IICSTAT);
 577
 578         if (status & S3C2410_IICSTAT_ARBITR) {
 579                 /* deal with arbitration loss */
 580                 dev_err(i2c->dev, "deal with arbitration loss\n");
 581         }
 582
 583         if (i2c->state == STATE_IDLE) {
 584                 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
 585
 586                 tmp = readl(i2c->regs + S3C2410_IICCON);
 587                 tmp &= ~S3C2410_IICCON_IRQPEND;
 588                 writel(tmp, i2c->regs +  S3C2410_IICCON);
 589                 goto out;
 590         }
 591
 592         /*
 593          * pretty much this leaves us with the fact that we've
 594          * transmitted or received whatever byte we last sent
 595          */
 596         i2c_s3c_irq_nextbyte(i2c, status);
 597
 598  out:
 599         return IRQ_HANDLED;
 600 }
 601
 602 /*
 603  * Disable the bus so that we won't get any interrupts from now on, or try
 604  * to drive any lines. This is the default state when we don't have
 605  * anything to send/receive.
 606  *
 607  * If there is an event on the bus, or we have a pre-existing event at
 608  * kernel boot time, we may not notice the event and the I2C controller
 609  * will lock the bus with the I2C clock line low indefinitely.
 610  */
 611 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
 612 {
 613         unsigned long tmp;
 614
 615         /* Stop driving the I2C pins */
 616         tmp = readl(i2c->regs + S3C2410_IICSTAT);
 617         tmp &= ~S3C2410_IICSTAT_TXRXEN;
 618         writel(tmp, i2c->regs + S3C2410_IICSTAT);
 619
 620         /* We don't expect any interrupts now, and don't want send acks */
 621         tmp = readl(i2c->regs + S3C2410_IICCON);
 622         tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
 623                 S3C2410_IICCON_ACKEN);
 624         writel(tmp, i2c->regs + S3C2410_IICCON);
 625 }
 626
 627
 628 /*
 629  * get the i2c bus for a master transaction
 630  */
 631 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
 632 {
 633         unsigned long iicstat;
 634         int timeout = 400;
 635
 636         while (timeout-- > 0) {
 637                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 638
 639                 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
 640                         return 0;
 641
 642                 msleep(1);
 643         }
 644
 645         return -ETIMEDOUT;
 646 }
 647
 648 /*
 649  * wait for the i2c bus to become idle.
 650  */
 651 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
 652 {
 653         unsigned long iicstat;
 654         ktime_t start, now;
 655         unsigned long delay;
 656         int spins;
 657
 658         /* ensure the stop has been through the bus */
 659
 660         dev_dbg(i2c->dev, "waiting for bus idle\n");
 661
 662         start = now = ktime_get();
 663
 664         /*
 665          * Most of the time, the bus is already idle within a few usec of the
 666          * end of a transaction.  However, really slow i2c devices can stretch
 667          * the clock, delaying STOP generation.
 668          *
 669          * On slower SoCs this typically happens within a very small number of
 670          * instructions so busy wait briefly to avoid scheduling overhead.
 671          */
 672         spins = 3;
 673         iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 674         while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
 675                 cpu_relax();
 676                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 677         }
 678
 679         /*
 680          * If we do get an appreciable delay as a compromise between idle
 681          * detection latency for the normal, fast case, and system load in the
 682          * slow device case, use an exponential back off in the polling loop,
 683          * up to 1/10th of the total timeout, then continue to poll at a
 684          * constant rate up to the timeout.
 685          */
 686         delay = 1;
 687         while ((iicstat & S3C2410_IICSTAT_START) &&
 688                ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
 689                 usleep_range(delay, 2 * delay);
 690                 if (delay < S3C2410_IDLE_TIMEOUT / 10)
 691                         delay <<= 1;
 692                 now = ktime_get();
 693                 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
 694         }
 695
 696         if (iicstat & S3C2410_IICSTAT_START)
 697                 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
 698 }
 699
 700 /*
 701  * this starts an i2c transfer
 702  */
 703 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
 704                               struct i2c_msg *msgs, int num)
 705 {
 706         unsigned long timeout;
 707         int ret;
 708
 709         if (i2c->suspended)
 710                 return -EIO;
 711
 712         ret = s3c24xx_i2c_set_master(i2c);
 713         if (ret != 0) {
 714                 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
 715                 ret = -EAGAIN;
 716                 goto out;
 717         }
 718
 719         i2c->msg     = msgs;
 720         i2c->msg_num = num;
 721         i2c->msg_ptr = 0;
 722         i2c->msg_idx = 0;
 723         i2c->state   = STATE_START;
 724
 725         s3c24xx_i2c_enable_irq(i2c);
 726         s3c24xx_i2c_message_start(i2c, msgs);
 727
 728         if (i2c->quirks & QUIRK_POLL) {
 729                 ret = i2c->msg_idx;
 730
 731                 if (ret != num)
 732                         dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 733
 734                 goto out;
 735         }
 736
 737         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 738
 739         ret = i2c->msg_idx;
 740
 741         /*
 742          * Having these next two as dev_err() makes life very
 743          * noisy when doing an i2cdetect
 744          */
 745         if (timeout == 0)
 746                 dev_dbg(i2c->dev, "timeout\n");
 747         else if (ret != num)
 748                 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
 749
 750         /* For QUIRK_HDMIPHY, bus is already disabled */
 751         if (i2c->quirks & QUIRK_HDMIPHY)
 752                 goto out;
 753
 754         s3c24xx_i2c_wait_idle(i2c);
 755
 756         s3c24xx_i2c_disable_bus(i2c);
 757
 758  out:
 759         i2c->state = STATE_IDLE;
 760
 761         return ret;
 762 }
 763
 764 /*
 765  * first port of call from the i2c bus code when an message needs
 766  * transferring across the i2c bus.
 767  */
 768 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
 769                         struct i2c_msg *msgs, int num)
 770 {
 771         struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
 772         int retry;
 773         int ret;
 774
 775         ret = clk_enable(i2c->clk);
 776         if (ret)
 777                 return ret;
 778
 779         for (retry = 0; retry < adap->retries; retry++) {
 780
 781                 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
 782
 783                 if (ret != -EAGAIN) {
 784                         clk_disable(i2c->clk);
 785                         return ret;
 786                 }
 787
 788                 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
 789
 790                 udelay(100);
 791         }
 792
 793         clk_disable(i2c->clk);
 794         return -EREMOTEIO;
 795 }
 796
 797 /* declare our i2c functionality */
 798 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
 799 {
 800         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
 801                 I2C_FUNC_PROTOCOL_MANGLING;
 802 }
 803
 804 /* i2c bus registration info */
 805 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
 806         .master_xfer            = s3c24xx_i2c_xfer,
 807         .functionality          = s3c24xx_i2c_func,
 808 };
 809
 810 /*
 811  * return the divisor settings for a given frequency
 812  */
 813 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
 814                                    unsigned int *div1, unsigned int *divs)
 815 {
 816         unsigned int calc_divs = clkin / wanted;
 817         unsigned int calc_div1;
 818
 819         if (calc_divs > (16*16))
 820                 calc_div1 = 512;
 821         else
 822                 calc_div1 = 16;
 823
 824         calc_divs += calc_div1-1;
 825         calc_divs /= calc_div1;
 826
 827         if (calc_divs == 0)
 828                 calc_divs = 1;
 829         if (calc_divs > 17)
 830                 calc_divs = 17;
 831
 832         *divs = calc_divs;
 833         *div1 = calc_div1;
 834
 835         return clkin / (calc_divs * calc_div1);
 836 }
 837
 838 /*
 839  * work out a divisor for the user requested frequency setting,
 840  * either by the requested frequency, or scanning the acceptable
 841  * range of frequencies until something is found
 842  */
 843 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
 844 {
 845         struct s3c2410_platform_i2c *pdata = i2c->pdata;
 846         unsigned long clkin = clk_get_rate(i2c->clk);
 847         unsigned int divs, div1;
 848         unsigned long target_frequency;
 849         u32 iiccon;
 850         int freq;
 851
 852         i2c->clkrate = clkin;
 853         clkin /= 1000;          /* clkin now in KHz */
 854
 855         dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
 856
 857         target_frequency = pdata->frequency ? pdata->frequency : 100000;
 858
 859         target_frequency /= 1000; /* Target frequency now in KHz */
 860
 861         freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
 862
 863         if (freq > target_frequency) {
 864                 dev_err(i2c->dev,
 865                         "Unable to achieve desired frequency %luKHz."   \
 866                         " Lowest achievable %dKHz\n", target_frequency, freq);
 867                 return -EINVAL;
 868         }
 869
 870         *got = freq;
 871
 872         iiccon = readl(i2c->regs + S3C2410_IICCON);
 873         iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
 874         iiccon |= (divs-1);
 875
 876         if (div1 == 512)
 877                 iiccon |= S3C2410_IICCON_TXDIV_512;
 878
 879         if (i2c->quirks & QUIRK_POLL)
 880                 iiccon |= S3C2410_IICCON_SCALE(2);
 881
 882         writel(iiccon, i2c->regs + S3C2410_IICCON);
 883
 884         if (i2c->quirks & QUIRK_S3C2440) {
 885                 unsigned long sda_delay;
 886
 887                 if (pdata->sda_delay) {
 888                         sda_delay = clkin * pdata->sda_delay;
 889                         sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
 890                         sda_delay = DIV_ROUND_UP(sda_delay, 5);
 891                         if (sda_delay > 3)
 892                                 sda_delay = 3;
 893                         sda_delay |= S3C2410_IICLC_FILTER_ON;
 894                 } else
 895                         sda_delay = 0;
 896
 897                 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
 898                 writel(sda_delay, i2c->regs + S3C2440_IICLC);
 899         }
 900
 901         return 0;
 902 }
 903
 904 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
 905
 906 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
 907
 908 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
 909                                           unsigned long val, void *data)
 910 {
 911         struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
 912         unsigned int got;
 913         int delta_f;
 914         int ret;
 915
 916         delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
 917
 918         /* if we're post-change and the input clock has slowed down
 919          * or at pre-change and the clock is about to speed up, then
 920          * adjust our clock rate. <0 is slow, >0 speedup.
 921          */
 922
 923         if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
 924             (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
 925                 i2c_lock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
 926                 ret = s3c24xx_i2c_clockrate(i2c, &got);
 927                 i2c_unlock_bus(&i2c->adap, I2C_LOCK_ROOT_ADAPTER);
 928
 929                 if (ret < 0)
 930                         dev_err(i2c->dev, "cannot find frequency (%d)\n", ret);
 931                 else
 932                         dev_info(i2c->dev, "setting freq %d\n", got);
 933         }
 934
 935         return 0;
 936 }
 937
 938 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 939 {
 940         i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
 941
 942         return cpufreq_register_notifier(&i2c->freq_transition,
 943                                          CPUFREQ_TRANSITION_NOTIFIER);
 944 }
 945
 946 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 947 {
 948         cpufreq_unregister_notifier(&i2c->freq_transition,
 949                                     CPUFREQ_TRANSITION_NOTIFIER);
 950 }
 951
 952 #else
 953 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
 954 {
 955         return 0;
 956 }
 957
 958 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
 959 {
 960 }
 961 #endif
 962
 963 #ifdef CONFIG_OF
 964 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
 965 {
 966         int idx, gpio, ret;
 967
 968         if (i2c->quirks & QUIRK_NO_GPIO)
 969                 return 0;
 970
 971         for (idx = 0; idx < 2; idx++) {
 972                 gpio = of_get_gpio(i2c->dev->of_node, idx);
 973                 if (!gpio_is_valid(gpio)) {
 974                         dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
 975                         goto free_gpio;
 976                 }
 977                 i2c->gpios[idx] = gpio;
 978
 979                 ret = gpio_request(gpio, "i2c-bus");
 980                 if (ret) {
 981                         dev_err(i2c->dev, "gpio [%d] request failed (%d)\n",
 982                                 gpio, ret);
 983                         goto free_gpio;
 984                 }
 985         }
 986         return 0;
 987
 988 free_gpio:
 989         while (--idx >= 0)
 990                 gpio_free(i2c->gpios[idx]);
 991         return -EINVAL;
 992 }
 993
 994 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
 995 {
 996         unsigned int idx;
 997
 998         if (i2c->quirks & QUIRK_NO_GPIO)
 999                 return;
1000
1001         for (idx = 0; idx < 2; idx++)
1002                 gpio_free(i2c->gpios[idx]);
1003 }
1004 #else
1005 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
1006 {
1007         return 0;
1008 }
1009
1010 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
1011 {
1012 }
1013 #endif
1014
1015 /*
1016  * initialise the controller, set the IO lines and frequency
1017  */
1018 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
1019 {
1020         struct s3c2410_platform_i2c *pdata;
1021         unsigned int freq;
1022
1023         /* get the plafrom data */
1024
1025         pdata = i2c->pdata;
1026
1027         /* write slave address */
1028
1029         writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
1030
1031         dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
1032
1033         writel(0, i2c->regs + S3C2410_IICCON);
1034         writel(0, i2c->regs + S3C2410_IICSTAT);
1035
1036         /* we need to work out the divisors for the clock... */
1037
1038         if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1039                 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1040                 return -EINVAL;
1041         }
1042
1043         /* todo - check that the i2c lines aren't being dragged anywhere */
1044
1045         dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1046         dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1047                 readl(i2c->regs + S3C2410_IICCON));
1048
1049         return 0;
1050 }
1051
1052 #ifdef CONFIG_OF
1053 /*
1054  * Parse the device tree node and retreive the platform data.
1055  */
1056 static void
1057 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1058 {
1059         struct s3c2410_platform_i2c *pdata = i2c->pdata;
1060         int id;
1061
1062         if (!np)
1063                 return;
1064
1065         pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1066         of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1067         of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1068         of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1069                                 (u32 *)&pdata->frequency);
1070         /*
1071          * Exynos5's legacy i2c controller and new high speed i2c
1072          * controller have muxed interrupt sources. By default the
1073          * interrupts for 4-channel HS-I2C controller are enabled.
1074          * If nodes for first four channels of legacy i2c controller
1075          * are available then re-configure the interrupts via the
1076          * system register.
1077          */
1078         id = of_alias_get_id(np, "i2c");
1079         i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1080                         "samsung,sysreg-phandle");
1081         if (IS_ERR(i2c->sysreg))
1082                 return;
1083
1084         regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1085 }
1086 #else
1087 static void
1088 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c) { }
1089 #endif
1090
1091 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1092 {
1093         struct s3c24xx_i2c *i2c;
1094         struct s3c2410_platform_i2c *pdata = NULL;
1095         struct resource *res;
1096         int ret;
1097
1098         if (!pdev->dev.of_node) {
1099                 pdata = dev_get_platdata(&pdev->dev);
1100                 if (!pdata) {
1101                         dev_err(&pdev->dev, "no platform data\n");
1102                         return -EINVAL;
1103                 }
1104         }
1105
1106         i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1107         if (!i2c)
1108                 return -ENOMEM;
1109
1110         i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1111         if (!i2c->pdata)
1112                 return -ENOMEM;
1113
1114         i2c->quirks = s3c24xx_get_device_quirks(pdev);
1115         i2c->sysreg = ERR_PTR(-ENOENT);
1116         if (pdata)
1117                 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1118         else
1119                 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1120
1121         strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1122         i2c->adap.owner = THIS_MODULE;
1123         i2c->adap.algo = &s3c24xx_i2c_algorithm;
1124         i2c->adap.retries = 2;
1125         i2c->adap.class = I2C_CLASS_DEPRECATED;
1126         i2c->tx_setup = 50;
1127
1128         init_waitqueue_head(&i2c->wait);
1129
1130         /* find the clock and enable it */
1131         i2c->dev = &pdev->dev;
1132         i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1133         if (IS_ERR(i2c->clk)) {
1134                 dev_err(&pdev->dev, "cannot get clock\n");
1135                 return -ENOENT;
1136         }
1137
1138         dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1139
1140         /* map the registers */
1141         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1142         i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1143
1144         if (IS_ERR(i2c->regs))
1145                 return PTR_ERR(i2c->regs);
1146
1147         dev_dbg(&pdev->dev, "registers %p (%p)\n",
1148                 i2c->regs, res);
1149
1150         /* setup info block for the i2c core */
1151         i2c->adap.algo_data = i2c;
1152         i2c->adap.dev.parent = &pdev->dev;
1153         i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1154
1155         /* inititalise the i2c gpio lines */
1156         if (i2c->pdata->cfg_gpio)
1157                 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1158         else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c))
1159                 return -EINVAL;
1160
1161         /* initialise the i2c controller */
1162         ret = clk_prepare_enable(i2c->clk);
1163         if (ret) {
1164                 dev_err(&pdev->dev, "I2C clock enable failed\n");
1165                 return ret;
1166         }
1167
1168         ret = s3c24xx_i2c_init(i2c);
1169         clk_disable(i2c->clk);
1170         if (ret != 0) {
1171                 dev_err(&pdev->dev, "I2C controller init failed\n");
1172                 clk_unprepare(i2c->clk);
1173                 return ret;
1174         }
1175
1176         /*
1177          * find the IRQ for this unit (note, this relies on the init call to
1178          * ensure no current IRQs pending
1179          */
1180         if (!(i2c->quirks & QUIRK_POLL)) {
1181                 i2c->irq = ret = platform_get_irq(pdev, 0);
1182                 if (ret < 0) {
1183                         dev_err(&pdev->dev, "cannot find IRQ\n");
1184                         clk_unprepare(i2c->clk);
1185                         return ret;
1186                 }
1187
1188                 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq,
1189                                        0, dev_name(&pdev->dev), i2c);
1190                 if (ret != 0) {
1191                         dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1192                         clk_unprepare(i2c->clk);
1193                         return ret;
1194                 }
1195         }
1196
1197         ret = s3c24xx_i2c_register_cpufreq(i2c);
1198         if (ret < 0) {
1199                 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1200                 clk_unprepare(i2c->clk);
1201                 return ret;
1202         }
1203
1204         /*
1205          * Note, previous versions of the driver used i2c_add_adapter()
1206          * to add the bus at any number. We now pass the bus number via
1207          * the platform data, so if unset it will now default to always
1208          * being bus 0.
1209          */
1210         i2c->adap.nr = i2c->pdata->bus_num;
1211         i2c->adap.dev.of_node = pdev->dev.of_node;
1212
1213         platform_set_drvdata(pdev, i2c);
1214
1215         pm_runtime_enable(&pdev->dev);
1216
1217         ret = i2c_add_numbered_adapter(&i2c->adap);
1218         if (ret < 0) {
1219                 pm_runtime_disable(&pdev->dev);
1220                 s3c24xx_i2c_deregister_cpufreq(i2c);
1221                 clk_unprepare(i2c->clk);
1222                 return ret;
1223         }
1224
1225         dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1226         return 0;
1227 }
1228
1229 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1230 {
1231         struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1232
1233         clk_unprepare(i2c->clk);
1234
1235         pm_runtime_disable(&pdev->dev);
1236
1237         s3c24xx_i2c_deregister_cpufreq(i2c);
1238
1239         i2c_del_adapter(&i2c->adap);
1240
1241         if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1242                 s3c24xx_i2c_dt_gpio_free(i2c);
1243
1244         return 0;
1245 }
1246
1247 #ifdef CONFIG_PM_SLEEP
1248 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1249 {
1250         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1251
1252         i2c->suspended = 1;
1253
1254         if (!IS_ERR(i2c->sysreg))
1255                 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1256
1257         return 0;
1258 }
1259
1260 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1261 {
1262         struct s3c24xx_i2c *i2c = dev_get_drvdata(dev);
1263         int ret;
1264
1265         if (!IS_ERR(i2c->sysreg))
1266                 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1267
1268         ret = clk_enable(i2c->clk);
1269         if (ret)
1270                 return ret;
1271         s3c24xx_i2c_init(i2c);
1272         clk_disable(i2c->clk);
1273         i2c->suspended = 0;
1274
1275         return 0;
1276 }
1277 #endif
1278
1279 #ifdef CONFIG_PM
1280 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1281         SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(s3c24xx_i2c_suspend_noirq,
1282                                       s3c24xx_i2c_resume_noirq)
1283 };
1284
1285 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1286 #else
1287 #define S3C24XX_DEV_PM_OPS NULL
1288 #endif
1289
1290 static struct platform_driver s3c24xx_i2c_driver = {
1291         .probe          = s3c24xx_i2c_probe,
1292         .remove         = s3c24xx_i2c_remove,
1293         .id_table       = s3c24xx_driver_ids,
1294         .driver         = {
1295                 .name   = "s3c-i2c",
1296                 .pm     = S3C24XX_DEV_PM_OPS,
1297                 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1298         },
1299 };
1300
1301 static int __init i2c_adap_s3c_init(void)
1302 {
1303         return platform_driver_register(&s3c24xx_i2c_driver);
1304 }
1305 subsys_initcall(i2c_adap_s3c_init);
1306
1307 static void __exit i2c_adap_s3c_exit(void)
1308 {
1309         platform_driver_unregister(&s3c24xx_i2c_driver);
1310 }
1311 module_exit(i2c_adap_s3c_exit);
1312
1313 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1314 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1315 MODULE_LICENSE("GPL");