1 /* linux/drivers/i2c/busses/i2c-s3c2410.c
3 * Copyright (C) 2004,2005,2009 Simtec Electronics
4 * Ben Dooks <ben@simtec.co.uk>
6 * S3C2410 I2C Controller
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
19 #include <linux/kernel.h>
20 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/init.h>
24 #include <linux/time.h>
25 #include <linux/interrupt.h>
26 #include <linux/delay.h>
27 #include <linux/errno.h>
28 #include <linux/err.h>
29 #include <linux/platform_device.h>
30 #include <linux/pm_runtime.h>
31 #include <linux/clk.h>
32 #include <linux/cpufreq.h>
33 #include <linux/slab.h>
36 #include <linux/of_gpio.h>
37 #include <linux/pinctrl/consumer.h>
38 #include <linux/mfd/syscon.h>
39 #include <linux/regmap.h>
43 #include <linux/platform_data/i2c-s3c2410.h>
45 /* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
47 #define S3C2410_IICCON 0x00
48 #define S3C2410_IICSTAT 0x04
49 #define S3C2410_IICADD 0x08
50 #define S3C2410_IICDS 0x0C
51 #define S3C2440_IICLC 0x10
53 #define S3C2410_IICCON_ACKEN (1 << 7)
54 #define S3C2410_IICCON_TXDIV_16 (0 << 6)
55 #define S3C2410_IICCON_TXDIV_512 (1 << 6)
56 #define S3C2410_IICCON_IRQEN (1 << 5)
57 #define S3C2410_IICCON_IRQPEND (1 << 4)
58 #define S3C2410_IICCON_SCALE(x) ((x) & 0xf)
59 #define S3C2410_IICCON_SCALEMASK (0xf)
61 #define S3C2410_IICSTAT_MASTER_RX (2 << 6)
62 #define S3C2410_IICSTAT_MASTER_TX (3 << 6)
63 #define S3C2410_IICSTAT_SLAVE_RX (0 << 6)
64 #define S3C2410_IICSTAT_SLAVE_TX (1 << 6)
65 #define S3C2410_IICSTAT_MODEMASK (3 << 6)
67 #define S3C2410_IICSTAT_START (1 << 5)
68 #define S3C2410_IICSTAT_BUSBUSY (1 << 5)
69 #define S3C2410_IICSTAT_TXRXEN (1 << 4)
70 #define S3C2410_IICSTAT_ARBITR (1 << 3)
71 #define S3C2410_IICSTAT_ASSLAVE (1 << 2)
72 #define S3C2410_IICSTAT_ADDR0 (1 << 1)
73 #define S3C2410_IICSTAT_LASTBIT (1 << 0)
75 #define S3C2410_IICLC_SDA_DELAY0 (0 << 0)
76 #define S3C2410_IICLC_SDA_DELAY5 (1 << 0)
77 #define S3C2410_IICLC_SDA_DELAY10 (2 << 0)
78 #define S3C2410_IICLC_SDA_DELAY15 (3 << 0)
79 #define S3C2410_IICLC_SDA_DELAY_MASK (3 << 0)
81 #define S3C2410_IICLC_FILTER_ON (1 << 2)
83 /* Treat S3C2410 as baseline hardware, anything else is supported via quirks */
84 #define QUIRK_S3C2440 (1 << 0)
85 #define QUIRK_HDMIPHY (1 << 1)
86 #define QUIRK_NO_GPIO (1 << 2)
87 #define QUIRK_POLL (1 << 3)
89 /* Max time to wait for bus to become idle after a xfer (in us) */
90 #define S3C2410_IDLE_TIMEOUT 5000
92 /* Exynos5 Sysreg offset */
93 #define EXYNOS5_SYS_I2C_CFG 0x0234
95 /* i2c controller state */
96 enum s3c24xx_i2c_state {
105 wait_queue_head_t wait;
106 kernel_ulong_t quirks;
107 unsigned int suspended:1;
110 unsigned int msg_num;
111 unsigned int msg_idx;
112 unsigned int msg_ptr;
114 unsigned int tx_setup;
117 enum s3c24xx_i2c_state state;
118 unsigned long clkrate;
123 struct i2c_adapter adap;
125 struct s3c2410_platform_i2c *pdata;
127 struct pinctrl *pctrl;
128 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
129 struct notifier_block freq_transition;
131 struct regmap *sysreg;
132 unsigned int sys_i2c_cfg;
135 static const struct platform_device_id s3c24xx_driver_ids[] = {
137 .name = "s3c2410-i2c",
140 .name = "s3c2440-i2c",
141 .driver_data = QUIRK_S3C2440,
143 .name = "s3c2440-hdmiphy-i2c",
144 .driver_data = QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO,
147 MODULE_DEVICE_TABLE(platform, s3c24xx_driver_ids);
149 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat);
152 static const struct of_device_id s3c24xx_i2c_match[] = {
153 { .compatible = "samsung,s3c2410-i2c", .data = (void *)0 },
154 { .compatible = "samsung,s3c2440-i2c", .data = (void *)QUIRK_S3C2440 },
155 { .compatible = "samsung,s3c2440-hdmiphy-i2c",
156 .data = (void *)(QUIRK_S3C2440 | QUIRK_HDMIPHY | QUIRK_NO_GPIO) },
157 { .compatible = "samsung,exynos5440-i2c",
158 .data = (void *)(QUIRK_S3C2440 | QUIRK_NO_GPIO) },
159 { .compatible = "samsung,exynos5-sata-phy-i2c",
160 .data = (void *)(QUIRK_S3C2440 | QUIRK_POLL | QUIRK_NO_GPIO) },
163 MODULE_DEVICE_TABLE(of, s3c24xx_i2c_match);
166 /* s3c24xx_get_device_quirks
168 * Get controller type either from device tree or platform device variant.
171 static inline kernel_ulong_t s3c24xx_get_device_quirks(struct platform_device *pdev)
173 if (pdev->dev.of_node) {
174 const struct of_device_id *match;
175 match = of_match_node(s3c24xx_i2c_match, pdev->dev.of_node);
176 return (kernel_ulong_t)match->data;
179 return platform_get_device_id(pdev)->driver_data;
182 /* s3c24xx_i2c_master_complete
184 * complete the message and wake up the caller, using the given return code,
185 * or zero to mean ok.
188 static inline void s3c24xx_i2c_master_complete(struct s3c24xx_i2c *i2c, int ret)
190 dev_dbg(i2c->dev, "master_complete %d\n", ret);
199 if (!(i2c->quirks & QUIRK_POLL))
203 static inline void s3c24xx_i2c_disable_ack(struct s3c24xx_i2c *i2c)
207 tmp = readl(i2c->regs + S3C2410_IICCON);
208 writel(tmp & ~S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
211 static inline void s3c24xx_i2c_enable_ack(struct s3c24xx_i2c *i2c)
215 tmp = readl(i2c->regs + S3C2410_IICCON);
216 writel(tmp | S3C2410_IICCON_ACKEN, i2c->regs + S3C2410_IICCON);
219 /* irq enable/disable functions */
221 static inline void s3c24xx_i2c_disable_irq(struct s3c24xx_i2c *i2c)
225 tmp = readl(i2c->regs + S3C2410_IICCON);
226 writel(tmp & ~S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
229 static inline void s3c24xx_i2c_enable_irq(struct s3c24xx_i2c *i2c)
233 tmp = readl(i2c->regs + S3C2410_IICCON);
234 writel(tmp | S3C2410_IICCON_IRQEN, i2c->regs + S3C2410_IICCON);
237 static bool is_ack(struct s3c24xx_i2c *i2c)
241 for (tries = 50; tries; --tries) {
242 if (readl(i2c->regs + S3C2410_IICCON)
243 & S3C2410_IICCON_IRQPEND) {
244 if (!(readl(i2c->regs + S3C2410_IICSTAT)
245 & S3C2410_IICSTAT_LASTBIT))
248 usleep_range(1000, 2000);
250 dev_err(i2c->dev, "ack was not received\n");
254 /* s3c24xx_i2c_message_start
256 * put the start of a message onto the bus
259 static void s3c24xx_i2c_message_start(struct s3c24xx_i2c *i2c,
262 unsigned int addr = (msg->addr & 0x7f) << 1;
264 unsigned long iiccon;
267 stat |= S3C2410_IICSTAT_TXRXEN;
269 if (msg->flags & I2C_M_RD) {
270 stat |= S3C2410_IICSTAT_MASTER_RX;
273 stat |= S3C2410_IICSTAT_MASTER_TX;
275 if (msg->flags & I2C_M_REV_DIR_ADDR)
278 /* todo - check for whether ack wanted or not */
279 s3c24xx_i2c_enable_ack(i2c);
281 iiccon = readl(i2c->regs + S3C2410_IICCON);
282 writel(stat, i2c->regs + S3C2410_IICSTAT);
284 dev_dbg(i2c->dev, "START: %08lx to IICSTAT, %02x to DS\n", stat, addr);
285 writeb(addr, i2c->regs + S3C2410_IICDS);
287 /* delay here to ensure the data byte has gotten onto the bus
288 * before the transaction is started */
290 ndelay(i2c->tx_setup);
292 dev_dbg(i2c->dev, "iiccon, %08lx\n", iiccon);
293 writel(iiccon, i2c->regs + S3C2410_IICCON);
295 stat |= S3C2410_IICSTAT_START;
296 writel(stat, i2c->regs + S3C2410_IICSTAT);
298 if (i2c->quirks & QUIRK_POLL) {
299 while ((i2c->msg_num != 0) && is_ack(i2c)) {
300 i2c_s3c_irq_nextbyte(i2c, stat);
301 stat = readl(i2c->regs + S3C2410_IICSTAT);
303 if (stat & S3C2410_IICSTAT_ARBITR)
304 dev_err(i2c->dev, "deal with arbitration loss\n");
309 static inline void s3c24xx_i2c_stop(struct s3c24xx_i2c *i2c, int ret)
311 unsigned long iicstat = readl(i2c->regs + S3C2410_IICSTAT);
313 dev_dbg(i2c->dev, "STOP\n");
316 * The datasheet says that the STOP sequence should be:
317 * 1) I2CSTAT.5 = 0 - Clear BUSY (or 'generate STOP')
318 * 2) I2CCON.4 = 0 - Clear IRQPEND
319 * 3) Wait until the stop condition takes effect.
320 * 4*) I2CSTAT.4 = 0 - Clear TXRXEN
322 * Where, step "4*" is only for buses with the "HDMIPHY" quirk.
324 * However, after much experimentation, it appears that:
325 * a) normal buses automatically clear BUSY and transition from
326 * Master->Slave when they complete generating a STOP condition.
327 * Therefore, step (3) can be done in doxfer() by polling I2CCON.4
328 * after starting the STOP generation here.
329 * b) HDMIPHY bus does neither, so there is no way to do step 3.
330 * There is no indication when this bus has finished generating
333 * In fact, we have found that as soon as the IRQPEND bit is cleared in
334 * step 2, the HDMIPHY bus generates the STOP condition, and then
335 * immediately starts transferring another data byte, even though the
336 * bus is supposedly stopped. This is presumably because the bus is
337 * still in "Master" mode, and its BUSY bit is still set.
339 * To avoid these extra post-STOP transactions on HDMI phy devices, we
340 * just disable Serial Output on the bus (I2CSTAT.4 = 0) directly,
341 * instead of first generating a proper STOP condition. This should
342 * float SDA & SCK terminating the transfer. Subsequent transfers
343 * start with a proper START condition, and proceed normally.
345 * The HDMIPHY bus is an internal bus that always has exactly two
346 * devices, the host as Master and the HDMIPHY device as the slave.
347 * Skipping the STOP condition has been tested on this bus and works.
349 if (i2c->quirks & QUIRK_HDMIPHY) {
350 /* Stop driving the I2C pins */
351 iicstat &= ~S3C2410_IICSTAT_TXRXEN;
353 /* stop the transfer */
354 iicstat &= ~S3C2410_IICSTAT_START;
356 writel(iicstat, i2c->regs + S3C2410_IICSTAT);
358 i2c->state = STATE_STOP;
360 s3c24xx_i2c_master_complete(i2c, ret);
361 s3c24xx_i2c_disable_irq(i2c);
364 /* helper functions to determine the current state in the set of
365 * messages we are sending */
369 * returns TRUE if the current message is the last in the set
372 static inline int is_lastmsg(struct s3c24xx_i2c *i2c)
374 return i2c->msg_idx >= (i2c->msg_num - 1);
379 * returns TRUE if we this is the last byte in the current message
382 static inline int is_msglast(struct s3c24xx_i2c *i2c)
384 /* msg->len is always 1 for the first byte of smbus block read.
385 * Actual length will be read from slave. More bytes will be
386 * read according to the length then. */
387 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
390 return i2c->msg_ptr == i2c->msg->len-1;
395 * returns TRUE if we reached the end of the current message
398 static inline int is_msgend(struct s3c24xx_i2c *i2c)
400 return i2c->msg_ptr >= i2c->msg->len;
403 /* i2c_s3c_irq_nextbyte
405 * process an interrupt and work out what to do
408 static int i2c_s3c_irq_nextbyte(struct s3c24xx_i2c *i2c, unsigned long iicstat)
414 switch (i2c->state) {
417 dev_err(i2c->dev, "%s: called in STATE_IDLE\n", __func__);
421 dev_err(i2c->dev, "%s: called in STATE_STOP\n", __func__);
422 s3c24xx_i2c_disable_irq(i2c);
426 /* last thing we did was send a start condition on the
427 * bus, or started a new i2c message
430 if (iicstat & S3C2410_IICSTAT_LASTBIT &&
431 !(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
432 /* ack was not received... */
434 dev_dbg(i2c->dev, "ack was not received\n");
435 s3c24xx_i2c_stop(i2c, -ENXIO);
439 if (i2c->msg->flags & I2C_M_RD)
440 i2c->state = STATE_READ;
442 i2c->state = STATE_WRITE;
444 /* terminate the transfer if there is nothing to do
445 * as this is used by the i2c probe to find devices. */
447 if (is_lastmsg(i2c) && i2c->msg->len == 0) {
448 s3c24xx_i2c_stop(i2c, 0);
452 if (i2c->state == STATE_READ)
455 /* fall through to the write state, as we will need to
456 * send a byte as well */
459 /* we are writing data to the device... check for the
460 * end of the message, and if so, work out what to do
463 if (!(i2c->msg->flags & I2C_M_IGNORE_NAK)) {
464 if (iicstat & S3C2410_IICSTAT_LASTBIT) {
465 dev_dbg(i2c->dev, "WRITE: No Ack\n");
467 s3c24xx_i2c_stop(i2c, -ECONNREFUSED);
474 if (!is_msgend(i2c)) {
475 byte = i2c->msg->buf[i2c->msg_ptr++];
476 writeb(byte, i2c->regs + S3C2410_IICDS);
478 /* delay after writing the byte to allow the
479 * data setup time on the bus, as writing the
480 * data to the register causes the first bit
481 * to appear on SDA, and SCL will change as
482 * soon as the interrupt is acknowledged */
484 ndelay(i2c->tx_setup);
486 } else if (!is_lastmsg(i2c)) {
487 /* we need to go to the next i2c message */
489 dev_dbg(i2c->dev, "WRITE: Next Message\n");
495 /* check to see if we need to do another message */
496 if (i2c->msg->flags & I2C_M_NOSTART) {
498 if (i2c->msg->flags & I2C_M_RD) {
499 /* cannot do this, the controller
500 * forces us to send a new START
501 * when we change direction */
503 "missing START before write->read\n");
504 s3c24xx_i2c_stop(i2c, -EINVAL);
510 /* send the new start */
511 s3c24xx_i2c_message_start(i2c, i2c->msg);
512 i2c->state = STATE_START;
518 s3c24xx_i2c_stop(i2c, 0);
523 /* we have a byte of data in the data register, do
524 * something with it, and then work out whether we are
525 * going to do any more read/write
528 byte = readb(i2c->regs + S3C2410_IICDS);
529 i2c->msg->buf[i2c->msg_ptr++] = byte;
531 /* Add actual length to read for smbus block read */
532 if (i2c->msg->flags & I2C_M_RECV_LEN && i2c->msg->len == 1)
533 i2c->msg->len += byte;
535 if (is_msglast(i2c)) {
536 /* last byte of buffer */
539 s3c24xx_i2c_disable_ack(i2c);
541 } else if (is_msgend(i2c)) {
542 /* ok, we've read the entire buffer, see if there
543 * is anything else we need to do */
545 if (is_lastmsg(i2c)) {
546 /* last message, send stop and complete */
547 dev_dbg(i2c->dev, "READ: Send Stop\n");
549 s3c24xx_i2c_stop(i2c, 0);
551 /* go to the next transfer */
552 dev_dbg(i2c->dev, "READ: Next Transfer\n");
563 /* acknowlegde the IRQ and get back on with the work */
566 tmp = readl(i2c->regs + S3C2410_IICCON);
567 tmp &= ~S3C2410_IICCON_IRQPEND;
568 writel(tmp, i2c->regs + S3C2410_IICCON);
575 * top level IRQ servicing routine
578 static irqreturn_t s3c24xx_i2c_irq(int irqno, void *dev_id)
580 struct s3c24xx_i2c *i2c = dev_id;
581 unsigned long status;
584 status = readl(i2c->regs + S3C2410_IICSTAT);
586 if (status & S3C2410_IICSTAT_ARBITR) {
587 /* deal with arbitration loss */
588 dev_err(i2c->dev, "deal with arbitration loss\n");
591 if (i2c->state == STATE_IDLE) {
592 dev_dbg(i2c->dev, "IRQ: error i2c->state == IDLE\n");
594 tmp = readl(i2c->regs + S3C2410_IICCON);
595 tmp &= ~S3C2410_IICCON_IRQPEND;
596 writel(tmp, i2c->regs + S3C2410_IICCON);
600 /* pretty much this leaves us with the fact that we've
601 * transmitted or received whatever byte we last sent */
603 i2c_s3c_irq_nextbyte(i2c, status);
610 * Disable the bus so that we won't get any interrupts from now on, or try
611 * to drive any lines. This is the default state when we don't have
612 * anything to send/receive.
614 * If there is an event on the bus, or we have a pre-existing event at
615 * kernel boot time, we may not notice the event and the I2C controller
616 * will lock the bus with the I2C clock line low indefinitely.
618 static inline void s3c24xx_i2c_disable_bus(struct s3c24xx_i2c *i2c)
622 /* Stop driving the I2C pins */
623 tmp = readl(i2c->regs + S3C2410_IICSTAT);
624 tmp &= ~S3C2410_IICSTAT_TXRXEN;
625 writel(tmp, i2c->regs + S3C2410_IICSTAT);
627 /* We don't expect any interrupts now, and don't want send acks */
628 tmp = readl(i2c->regs + S3C2410_IICCON);
629 tmp &= ~(S3C2410_IICCON_IRQEN | S3C2410_IICCON_IRQPEND |
630 S3C2410_IICCON_ACKEN);
631 writel(tmp, i2c->regs + S3C2410_IICCON);
635 /* s3c24xx_i2c_set_master
637 * get the i2c bus for a master transaction
640 static int s3c24xx_i2c_set_master(struct s3c24xx_i2c *i2c)
642 unsigned long iicstat;
645 while (timeout-- > 0) {
646 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
648 if (!(iicstat & S3C2410_IICSTAT_BUSBUSY))
657 /* s3c24xx_i2c_wait_idle
659 * wait for the i2c bus to become idle.
662 static void s3c24xx_i2c_wait_idle(struct s3c24xx_i2c *i2c)
664 unsigned long iicstat;
669 /* ensure the stop has been through the bus */
671 dev_dbg(i2c->dev, "waiting for bus idle\n");
673 start = now = ktime_get();
676 * Most of the time, the bus is already idle within a few usec of the
677 * end of a transaction. However, really slow i2c devices can stretch
678 * the clock, delaying STOP generation.
680 * On slower SoCs this typically happens within a very small number of
681 * instructions so busy wait briefly to avoid scheduling overhead.
684 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
685 while ((iicstat & S3C2410_IICSTAT_START) && --spins) {
687 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
691 * If we do get an appreciable delay as a compromise between idle
692 * detection latency for the normal, fast case, and system load in the
693 * slow device case, use an exponential back off in the polling loop,
694 * up to 1/10th of the total timeout, then continue to poll at a
695 * constant rate up to the timeout.
698 while ((iicstat & S3C2410_IICSTAT_START) &&
699 ktime_us_delta(now, start) < S3C2410_IDLE_TIMEOUT) {
700 usleep_range(delay, 2 * delay);
701 if (delay < S3C2410_IDLE_TIMEOUT / 10)
704 iicstat = readl(i2c->regs + S3C2410_IICSTAT);
707 if (iicstat & S3C2410_IICSTAT_START)
708 dev_warn(i2c->dev, "timeout waiting for bus idle\n");
711 /* s3c24xx_i2c_doxfer
713 * this starts an i2c transfer
716 static int s3c24xx_i2c_doxfer(struct s3c24xx_i2c *i2c,
717 struct i2c_msg *msgs, int num)
719 unsigned long timeout;
725 ret = s3c24xx_i2c_set_master(i2c);
727 dev_err(i2c->dev, "cannot get bus (error %d)\n", ret);
736 i2c->state = STATE_START;
738 s3c24xx_i2c_enable_irq(i2c);
739 s3c24xx_i2c_message_start(i2c, msgs);
741 if (i2c->quirks & QUIRK_POLL) {
745 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
750 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
754 /* having these next two as dev_err() makes life very
755 * noisy when doing an i2cdetect */
758 dev_dbg(i2c->dev, "timeout\n");
760 dev_dbg(i2c->dev, "incomplete xfer (%d)\n", ret);
762 /* For QUIRK_HDMIPHY, bus is already disabled */
763 if (i2c->quirks & QUIRK_HDMIPHY)
766 s3c24xx_i2c_wait_idle(i2c);
768 s3c24xx_i2c_disable_bus(i2c);
771 i2c->state = STATE_IDLE;
778 * first port of call from the i2c bus code when an message needs
779 * transferring across the i2c bus.
782 static int s3c24xx_i2c_xfer(struct i2c_adapter *adap,
783 struct i2c_msg *msgs, int num)
785 struct s3c24xx_i2c *i2c = (struct s3c24xx_i2c *)adap->algo_data;
789 pm_runtime_get_sync(&adap->dev);
790 ret = clk_enable(i2c->clk);
794 for (retry = 0; retry < adap->retries; retry++) {
796 ret = s3c24xx_i2c_doxfer(i2c, msgs, num);
798 if (ret != -EAGAIN) {
799 clk_disable(i2c->clk);
800 pm_runtime_put(&adap->dev);
804 dev_dbg(i2c->dev, "Retrying transmission (%d)\n", retry);
809 clk_disable(i2c->clk);
810 pm_runtime_put(&adap->dev);
814 /* declare our i2c functionality */
815 static u32 s3c24xx_i2c_func(struct i2c_adapter *adap)
817 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART |
818 I2C_FUNC_PROTOCOL_MANGLING;
821 /* i2c bus registration info */
823 static const struct i2c_algorithm s3c24xx_i2c_algorithm = {
824 .master_xfer = s3c24xx_i2c_xfer,
825 .functionality = s3c24xx_i2c_func,
828 /* s3c24xx_i2c_calcdivisor
830 * return the divisor settings for a given frequency
833 static int s3c24xx_i2c_calcdivisor(unsigned long clkin, unsigned int wanted,
834 unsigned int *div1, unsigned int *divs)
836 unsigned int calc_divs = clkin / wanted;
837 unsigned int calc_div1;
839 if (calc_divs > (16*16))
844 calc_divs += calc_div1-1;
845 calc_divs /= calc_div1;
855 return clkin / (calc_divs * calc_div1);
858 /* s3c24xx_i2c_clockrate
860 * work out a divisor for the user requested frequency setting,
861 * either by the requested frequency, or scanning the acceptable
862 * range of frequencies until something is found
865 static int s3c24xx_i2c_clockrate(struct s3c24xx_i2c *i2c, unsigned int *got)
867 struct s3c2410_platform_i2c *pdata = i2c->pdata;
868 unsigned long clkin = clk_get_rate(i2c->clk);
869 unsigned int divs, div1;
870 unsigned long target_frequency;
874 i2c->clkrate = clkin;
875 clkin /= 1000; /* clkin now in KHz */
877 dev_dbg(i2c->dev, "pdata desired frequency %lu\n", pdata->frequency);
879 target_frequency = pdata->frequency ? pdata->frequency : 100000;
881 target_frequency /= 1000; /* Target frequency now in KHz */
883 freq = s3c24xx_i2c_calcdivisor(clkin, target_frequency, &div1, &divs);
885 if (freq > target_frequency) {
887 "Unable to achieve desired frequency %luKHz." \
888 " Lowest achievable %dKHz\n", target_frequency, freq);
894 iiccon = readl(i2c->regs + S3C2410_IICCON);
895 iiccon &= ~(S3C2410_IICCON_SCALEMASK | S3C2410_IICCON_TXDIV_512);
899 iiccon |= S3C2410_IICCON_TXDIV_512;
901 if (i2c->quirks & QUIRK_POLL)
902 iiccon |= S3C2410_IICCON_SCALE(2);
904 writel(iiccon, i2c->regs + S3C2410_IICCON);
906 if (i2c->quirks & QUIRK_S3C2440) {
907 unsigned long sda_delay;
909 if (pdata->sda_delay) {
910 sda_delay = clkin * pdata->sda_delay;
911 sda_delay = DIV_ROUND_UP(sda_delay, 1000000);
912 sda_delay = DIV_ROUND_UP(sda_delay, 5);
915 sda_delay |= S3C2410_IICLC_FILTER_ON;
919 dev_dbg(i2c->dev, "IICLC=%08lx\n", sda_delay);
920 writel(sda_delay, i2c->regs + S3C2440_IICLC);
926 #if defined(CONFIG_ARM_S3C24XX_CPUFREQ)
928 #define freq_to_i2c(_n) container_of(_n, struct s3c24xx_i2c, freq_transition)
930 static int s3c24xx_i2c_cpufreq_transition(struct notifier_block *nb,
931 unsigned long val, void *data)
933 struct s3c24xx_i2c *i2c = freq_to_i2c(nb);
938 delta_f = clk_get_rate(i2c->clk) - i2c->clkrate;
940 /* if we're post-change and the input clock has slowed down
941 * or at pre-change and the clock is about to speed up, then
942 * adjust our clock rate. <0 is slow, >0 speedup.
945 if ((val == CPUFREQ_POSTCHANGE && delta_f < 0) ||
946 (val == CPUFREQ_PRECHANGE && delta_f > 0)) {
947 i2c_lock_adapter(&i2c->adap);
948 ret = s3c24xx_i2c_clockrate(i2c, &got);
949 i2c_unlock_adapter(&i2c->adap);
952 dev_err(i2c->dev, "cannot find frequency\n");
954 dev_info(i2c->dev, "setting freq %d\n", got);
960 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
962 i2c->freq_transition.notifier_call = s3c24xx_i2c_cpufreq_transition;
964 return cpufreq_register_notifier(&i2c->freq_transition,
965 CPUFREQ_TRANSITION_NOTIFIER);
968 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
970 cpufreq_unregister_notifier(&i2c->freq_transition,
971 CPUFREQ_TRANSITION_NOTIFIER);
975 static inline int s3c24xx_i2c_register_cpufreq(struct s3c24xx_i2c *i2c)
980 static inline void s3c24xx_i2c_deregister_cpufreq(struct s3c24xx_i2c *i2c)
986 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
990 if (i2c->quirks & QUIRK_NO_GPIO)
993 for (idx = 0; idx < 2; idx++) {
994 gpio = of_get_gpio(i2c->dev->of_node, idx);
995 if (!gpio_is_valid(gpio)) {
996 dev_err(i2c->dev, "invalid gpio[%d]: %d\n", idx, gpio);
999 i2c->gpios[idx] = gpio;
1001 ret = gpio_request(gpio, "i2c-bus");
1003 dev_err(i2c->dev, "gpio [%d] request failed\n", gpio);
1011 gpio_free(i2c->gpios[idx]);
1015 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
1019 if (i2c->quirks & QUIRK_NO_GPIO)
1022 for (idx = 0; idx < 2; idx++)
1023 gpio_free(i2c->gpios[idx]);
1026 static int s3c24xx_i2c_parse_dt_gpio(struct s3c24xx_i2c *i2c)
1031 static void s3c24xx_i2c_dt_gpio_free(struct s3c24xx_i2c *i2c)
1038 * initialise the controller, set the IO lines and frequency
1041 static int s3c24xx_i2c_init(struct s3c24xx_i2c *i2c)
1043 struct s3c2410_platform_i2c *pdata;
1046 /* get the plafrom data */
1050 /* write slave address */
1052 writeb(pdata->slave_addr, i2c->regs + S3C2410_IICADD);
1054 dev_info(i2c->dev, "slave address 0x%02x\n", pdata->slave_addr);
1056 writel(0, i2c->regs + S3C2410_IICCON);
1057 writel(0, i2c->regs + S3C2410_IICSTAT);
1059 /* we need to work out the divisors for the clock... */
1061 if (s3c24xx_i2c_clockrate(i2c, &freq) != 0) {
1062 dev_err(i2c->dev, "cannot meet bus frequency required\n");
1066 /* todo - check that the i2c lines aren't being dragged anywhere */
1068 dev_info(i2c->dev, "bus frequency set to %d KHz\n", freq);
1069 dev_dbg(i2c->dev, "S3C2410_IICCON=0x%02x\n",
1070 readl(i2c->regs + S3C2410_IICCON));
1076 /* s3c24xx_i2c_parse_dt
1078 * Parse the device tree node and retreive the platform data.
1082 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1084 struct s3c2410_platform_i2c *pdata = i2c->pdata;
1090 pdata->bus_num = -1; /* i2c bus number is dynamically assigned */
1091 of_property_read_u32(np, "samsung,i2c-sda-delay", &pdata->sda_delay);
1092 of_property_read_u32(np, "samsung,i2c-slave-addr", &pdata->slave_addr);
1093 of_property_read_u32(np, "samsung,i2c-max-bus-freq",
1094 (u32 *)&pdata->frequency);
1096 * Exynos5's legacy i2c controller and new high speed i2c
1097 * controller have muxed interrupt sources. By default the
1098 * interrupts for 4-channel HS-I2C controller are enabled.
1099 * If nodes for first four channels of legacy i2c controller
1100 * are available then re-configure the interrupts via the
1103 id = of_alias_get_id(np, "i2c");
1104 i2c->sysreg = syscon_regmap_lookup_by_phandle(np,
1105 "samsung,sysreg-phandle");
1106 if (IS_ERR(i2c->sysreg))
1109 regmap_update_bits(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, BIT(id), 0);
1113 s3c24xx_i2c_parse_dt(struct device_node *np, struct s3c24xx_i2c *i2c)
1119 /* s3c24xx_i2c_probe
1121 * called by the bus driver when a suitable device is found
1124 static int s3c24xx_i2c_probe(struct platform_device *pdev)
1126 struct s3c24xx_i2c *i2c;
1127 struct s3c2410_platform_i2c *pdata = NULL;
1128 struct resource *res;
1131 if (!pdev->dev.of_node) {
1132 pdata = dev_get_platdata(&pdev->dev);
1134 dev_err(&pdev->dev, "no platform data\n");
1139 i2c = devm_kzalloc(&pdev->dev, sizeof(struct s3c24xx_i2c), GFP_KERNEL);
1143 i2c->pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1147 i2c->quirks = s3c24xx_get_device_quirks(pdev);
1148 i2c->sysreg = ERR_PTR(-ENOENT);
1150 memcpy(i2c->pdata, pdata, sizeof(*pdata));
1152 s3c24xx_i2c_parse_dt(pdev->dev.of_node, i2c);
1154 strlcpy(i2c->adap.name, "s3c2410-i2c", sizeof(i2c->adap.name));
1155 i2c->adap.owner = THIS_MODULE;
1156 i2c->adap.algo = &s3c24xx_i2c_algorithm;
1157 i2c->adap.retries = 2;
1158 i2c->adap.class = I2C_CLASS_DEPRECATED;
1161 init_waitqueue_head(&i2c->wait);
1163 /* find the clock and enable it */
1165 i2c->dev = &pdev->dev;
1166 i2c->clk = devm_clk_get(&pdev->dev, "i2c");
1167 if (IS_ERR(i2c->clk)) {
1168 dev_err(&pdev->dev, "cannot get clock\n");
1172 dev_dbg(&pdev->dev, "clock source %p\n", i2c->clk);
1175 /* map the registers */
1177 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1178 i2c->regs = devm_ioremap_resource(&pdev->dev, res);
1180 if (IS_ERR(i2c->regs))
1181 return PTR_ERR(i2c->regs);
1183 dev_dbg(&pdev->dev, "registers %p (%p)\n",
1186 /* setup info block for the i2c core */
1188 i2c->adap.algo_data = i2c;
1189 i2c->adap.dev.parent = &pdev->dev;
1191 i2c->pctrl = devm_pinctrl_get_select_default(i2c->dev);
1193 /* inititalise the i2c gpio lines */
1195 if (i2c->pdata->cfg_gpio) {
1196 i2c->pdata->cfg_gpio(to_platform_device(i2c->dev));
1197 } else if (IS_ERR(i2c->pctrl) && s3c24xx_i2c_parse_dt_gpio(i2c)) {
1201 /* initialise the i2c controller */
1203 clk_prepare_enable(i2c->clk);
1204 ret = s3c24xx_i2c_init(i2c);
1205 clk_disable(i2c->clk);
1207 dev_err(&pdev->dev, "I2C controller init failed\n");
1210 /* find the IRQ for this unit (note, this relies on the init call to
1211 * ensure no current IRQs pending
1214 if (!(i2c->quirks & QUIRK_POLL)) {
1215 i2c->irq = ret = platform_get_irq(pdev, 0);
1217 dev_err(&pdev->dev, "cannot find IRQ\n");
1218 clk_unprepare(i2c->clk);
1222 ret = devm_request_irq(&pdev->dev, i2c->irq, s3c24xx_i2c_irq, 0,
1223 dev_name(&pdev->dev), i2c);
1226 dev_err(&pdev->dev, "cannot claim IRQ %d\n", i2c->irq);
1227 clk_unprepare(i2c->clk);
1232 ret = s3c24xx_i2c_register_cpufreq(i2c);
1234 dev_err(&pdev->dev, "failed to register cpufreq notifier\n");
1235 clk_unprepare(i2c->clk);
1239 /* Note, previous versions of the driver used i2c_add_adapter()
1240 * to add the bus at any number. We now pass the bus number via
1241 * the platform data, so if unset it will now default to always
1245 i2c->adap.nr = i2c->pdata->bus_num;
1246 i2c->adap.dev.of_node = pdev->dev.of_node;
1248 platform_set_drvdata(pdev, i2c);
1250 pm_runtime_enable(&pdev->dev);
1252 ret = i2c_add_numbered_adapter(&i2c->adap);
1254 dev_err(&pdev->dev, "failed to add bus to i2c core\n");
1255 pm_runtime_disable(&pdev->dev);
1256 s3c24xx_i2c_deregister_cpufreq(i2c);
1257 clk_unprepare(i2c->clk);
1261 pm_runtime_enable(&i2c->adap.dev);
1263 dev_info(&pdev->dev, "%s: S3C I2C adapter\n", dev_name(&i2c->adap.dev));
1267 /* s3c24xx_i2c_remove
1269 * called when device is removed from the bus
1272 static int s3c24xx_i2c_remove(struct platform_device *pdev)
1274 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1276 clk_unprepare(i2c->clk);
1278 pm_runtime_disable(&i2c->adap.dev);
1279 pm_runtime_disable(&pdev->dev);
1281 s3c24xx_i2c_deregister_cpufreq(i2c);
1283 i2c_del_adapter(&i2c->adap);
1285 if (pdev->dev.of_node && IS_ERR(i2c->pctrl))
1286 s3c24xx_i2c_dt_gpio_free(i2c);
1291 #ifdef CONFIG_PM_SLEEP
1292 static int s3c24xx_i2c_suspend_noirq(struct device *dev)
1294 struct platform_device *pdev = to_platform_device(dev);
1295 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1299 if (!IS_ERR(i2c->sysreg))
1300 regmap_read(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, &i2c->sys_i2c_cfg);
1305 static int s3c24xx_i2c_resume_noirq(struct device *dev)
1307 struct platform_device *pdev = to_platform_device(dev);
1308 struct s3c24xx_i2c *i2c = platform_get_drvdata(pdev);
1311 if (!IS_ERR(i2c->sysreg))
1312 regmap_write(i2c->sysreg, EXYNOS5_SYS_I2C_CFG, i2c->sys_i2c_cfg);
1314 ret = clk_enable(i2c->clk);
1317 s3c24xx_i2c_init(i2c);
1318 clk_disable(i2c->clk);
1326 static const struct dev_pm_ops s3c24xx_i2c_dev_pm_ops = {
1327 #ifdef CONFIG_PM_SLEEP
1328 .suspend_noirq = s3c24xx_i2c_suspend_noirq,
1329 .resume_noirq = s3c24xx_i2c_resume_noirq,
1330 .freeze_noirq = s3c24xx_i2c_suspend_noirq,
1331 .thaw_noirq = s3c24xx_i2c_resume_noirq,
1332 .poweroff_noirq = s3c24xx_i2c_suspend_noirq,
1333 .restore_noirq = s3c24xx_i2c_resume_noirq,
1337 #define S3C24XX_DEV_PM_OPS (&s3c24xx_i2c_dev_pm_ops)
1339 #define S3C24XX_DEV_PM_OPS NULL
1342 /* device driver for platform bus bits */
1344 static struct platform_driver s3c24xx_i2c_driver = {
1345 .probe = s3c24xx_i2c_probe,
1346 .remove = s3c24xx_i2c_remove,
1347 .id_table = s3c24xx_driver_ids,
1350 .pm = S3C24XX_DEV_PM_OPS,
1351 .of_match_table = of_match_ptr(s3c24xx_i2c_match),
1355 static int __init i2c_adap_s3c_init(void)
1357 return platform_driver_register(&s3c24xx_i2c_driver);
1359 subsys_initcall(i2c_adap_s3c_init);
1361 static void __exit i2c_adap_s3c_exit(void)
1363 platform_driver_unregister(&s3c24xx_i2c_driver);
1365 module_exit(i2c_adap_s3c_exit);
1367 MODULE_DESCRIPTION("S3C24XX I2C Bus driver");
1368 MODULE_AUTHOR("Ben Dooks, <ben@simtec.co.uk>");
1369 MODULE_LICENSE("GPL");