2 * Driver for the Renesas R-Car I2C unit
4 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
5 * Copyright (C) 2011-2015 Renesas Electronics Corporation
7 * Copyright (C) 2012-14 Renesas Solutions Corp.
8 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
10 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
11 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/of_device.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/reset.h>
36 #include <linux/slab.h>
38 /* register offsets */
39 #define ICSCR 0x00 /* slave ctrl */
40 #define ICMCR 0x04 /* master ctrl */
41 #define ICSSR 0x08 /* slave status */
42 #define ICMSR 0x0C /* master status */
43 #define ICSIER 0x10 /* slave irq enable */
44 #define ICMIER 0x14 /* master irq enable */
45 #define ICCCR 0x18 /* clock dividers */
46 #define ICSAR 0x1C /* slave address */
47 #define ICMAR 0x20 /* master address */
48 #define ICRXTX 0x24 /* data port */
49 #define ICDMAER 0x3c /* DMA enable */
50 #define ICFBSCR 0x38 /* first bit setup cycle */
53 #define SDBS (1 << 3) /* slave data buffer select */
54 #define SIE (1 << 2) /* slave interface enable */
55 #define GCAE (1 << 1) /* general call address enable */
56 #define FNA (1 << 0) /* forced non acknowledgment */
59 #define MDBS (1 << 7) /* non-fifo mode switch */
60 #define FSCL (1 << 6) /* override SCL pin */
61 #define FSDA (1 << 5) /* override SDA pin */
62 #define OBPC (1 << 4) /* override pins */
63 #define MIE (1 << 3) /* master if enable */
65 #define FSB (1 << 1) /* force stop bit */
66 #define ESG (1 << 0) /* en startbit gen */
68 /* ICSSR (also for ICSIER) */
69 #define GCAR (1 << 6) /* general call received */
70 #define STM (1 << 5) /* slave transmit mode */
71 #define SSR (1 << 4) /* stop received */
72 #define SDE (1 << 3) /* slave data empty */
73 #define SDT (1 << 2) /* slave data transmitted */
74 #define SDR (1 << 1) /* slave data received */
75 #define SAR (1 << 0) /* slave addr received */
77 /* ICMSR (also for ICMIE) */
78 #define MNR (1 << 6) /* nack received */
79 #define MAL (1 << 5) /* arbitration lost */
80 #define MST (1 << 4) /* sent a stop */
84 #define MAT (1 << 0) /* slave addr xfer done */
87 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */
88 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */
89 #define RMDMAE (1 << 1) /* DMA Master Received Enable */
90 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
93 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */
94 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
97 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
98 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
99 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
100 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
102 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
103 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
104 #define RCAR_IRQ_STOP (MST)
106 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF)
107 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF)
109 #define ID_LAST_MSG (1 << 0)
110 #define ID_FIRST_MSG (1 << 1)
111 #define ID_DONE (1 << 2)
112 #define ID_ARBLOST (1 << 3)
113 #define ID_NACK (1 << 4)
114 /* persistent flags */
115 #define ID_P_NO_RXDMA (1 << 30) /* HW forbids RXDMA sometimes */
116 #define ID_P_PM_BLOCKED (1 << 31)
117 #define ID_P_MASK (ID_P_PM_BLOCKED | ID_P_NO_RXDMA)
125 struct rcar_i2c_priv {
127 struct i2c_adapter adap;
132 wait_queue_head_t wait;
137 enum rcar_i2c_type devtype;
138 struct i2c_client *slave;
140 struct resource *res;
141 struct dma_chan *dma_tx;
142 struct dma_chan *dma_rx;
143 struct scatterlist sg;
144 enum dma_data_direction dma_direction;
146 struct reset_control *rstc;
150 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
151 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
153 #define LOOP_TIMEOUT 1024
156 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
158 writel(val, priv->io + reg);
161 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
163 return readl(priv->io + reg);
166 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
168 /* reset master mode */
169 rcar_i2c_write(priv, ICMIER, 0);
170 rcar_i2c_write(priv, ICMCR, MDBS);
171 rcar_i2c_write(priv, ICMSR, 0);
173 rcar_i2c_write(priv, ICCCR, priv->icccr);
176 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
180 for (i = 0; i < LOOP_TIMEOUT; i++) {
181 /* make sure that bus is not busy */
182 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
190 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
192 u32 scgd, cdf, round, ick, sum, scl, cdf_width;
194 struct device *dev = rcar_i2c_priv_to_dev(priv);
196 /* Fall back to previously used values if not supplied */
197 t->bus_freq_hz = t->bus_freq_hz ?: 100000;
198 t->scl_fall_ns = t->scl_fall_ns ?: 35;
199 t->scl_rise_ns = t->scl_rise_ns ?: 200;
200 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
202 switch (priv->devtype) {
211 dev_err(dev, "device type error\n");
216 * calculate SCL clock
220 * ick = clkp / (1 + CDF)
221 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
223 * ick : I2C internal clock < 20 MHz
224 * ticf : I2C SCL falling time
225 * tr : I2C SCL rising time
226 * intd : LSI internal delay
227 * clkp : peripheral_clk
228 * F[] : integer up-valuation
230 rate = clk_get_rate(priv->clk);
231 cdf = rate / 20000000;
232 if (cdf >= 1U << cdf_width) {
233 dev_err(dev, "Input clock %lu too high\n", rate);
236 ick = rate / (cdf + 1);
239 * it is impossible to calculate large scale
240 * number on u32. separate it
242 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
243 * = F[sum * ick / 1000000000]
244 * = F[(ick / 1000000) * sum / 1000]
246 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
247 round = (ick + 500000) / 1000000 * sum;
248 round = (round + 500) / 1000;
251 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
253 * Calculation result (= SCL) should be less than
254 * bus_speed for hardware safety
256 * We could use something along the lines of
257 * div = ick / (bus_speed + 1) + 1;
258 * scgd = (div - 20 - round + 7) / 8;
259 * scl = ick / (20 + (scgd * 8) + round);
260 * (not fully verified) but that would get pretty involved
262 for (scgd = 0; scgd < 0x40; scgd++) {
263 scl = ick / (20 + (scgd * 8) + round);
264 if (scl <= t->bus_freq_hz)
267 dev_err(dev, "it is impossible to calculate best SCL\n");
271 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
272 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
274 /* keep icccr value */
275 priv->icccr = scgd << cdf_width | cdf;
280 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
282 int read = !!rcar_i2c_is_recv(priv);
285 if (priv->msgs_left == 1)
286 priv->flags |= ID_LAST_MSG;
288 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
290 * We don't have a testcase but the HW engineers say that the write order
291 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
292 * it didn't cause a drawback for me, let's rather be safe than sorry.
294 if (priv->flags & ID_FIRST_MSG) {
295 rcar_i2c_write(priv, ICMSR, 0);
296 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
298 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
299 rcar_i2c_write(priv, ICMSR, 0);
301 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
304 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
308 priv->flags &= ID_P_MASK;
309 rcar_i2c_prepare_msg(priv);
313 * interrupt functions
315 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
317 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
318 ? priv->dma_rx : priv->dma_tx;
320 /* Disable DMA Master Received/Transmitted */
321 rcar_i2c_write(priv, ICDMAER, 0);
323 /* Reset default delay */
324 rcar_i2c_write(priv, ICFBSCR, TCYC06);
326 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
327 sg_dma_len(&priv->sg), priv->dma_direction);
329 /* Gen3 can only do one RXDMA per transfer and we just completed it */
330 if (priv->devtype == I2C_RCAR_GEN3 &&
331 priv->dma_direction == DMA_FROM_DEVICE)
332 priv->flags |= ID_P_NO_RXDMA;
334 priv->dma_direction = DMA_NONE;
337 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
339 if (priv->dma_direction == DMA_NONE)
341 else if (priv->dma_direction == DMA_FROM_DEVICE)
342 dmaengine_terminate_all(priv->dma_rx);
343 else if (priv->dma_direction == DMA_TO_DEVICE)
344 dmaengine_terminate_all(priv->dma_tx);
346 rcar_i2c_dma_unmap(priv);
349 static void rcar_i2c_dma_callback(void *data)
351 struct rcar_i2c_priv *priv = data;
353 priv->pos += sg_dma_len(&priv->sg);
355 rcar_i2c_dma_unmap(priv);
358 static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
360 struct device *dev = rcar_i2c_priv_to_dev(priv);
361 struct i2c_msg *msg = priv->msg;
362 bool read = msg->flags & I2C_M_RD;
363 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
364 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
365 struct dma_async_tx_descriptor *txdesc;
371 /* Do various checks to see if DMA is feasible at all */
372 if (IS_ERR(chan) || msg->len < 8 ||
373 (read && priv->flags & ID_P_NO_RXDMA))
378 * The last two bytes needs to be fetched using PIO in
379 * order for the STOP phase to work.
381 buf = priv->msg->buf;
382 len = priv->msg->len - 2;
385 * First byte in message was sent using PIO.
387 buf = priv->msg->buf + 1;
388 len = priv->msg->len - 1;
391 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
392 if (dma_mapping_error(chan->device->dev, dma_addr)) {
393 dev_dbg(dev, "dma map failed, using PIO\n");
397 sg_dma_len(&priv->sg) = len;
398 sg_dma_address(&priv->sg) = dma_addr;
400 priv->dma_direction = dir;
402 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
403 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
404 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
406 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
407 rcar_i2c_cleanup_dma(priv);
411 txdesc->callback = rcar_i2c_dma_callback;
412 txdesc->callback_param = priv;
414 cookie = dmaengine_submit(txdesc);
415 if (dma_submit_error(cookie)) {
416 dev_dbg(dev, "submitting dma failed, using PIO\n");
417 rcar_i2c_cleanup_dma(priv);
421 /* Set delay for DMA operations */
422 rcar_i2c_write(priv, ICFBSCR, TCYC17);
424 /* Enable DMA Master Received/Transmitted */
426 rcar_i2c_write(priv, ICDMAER, RMDMAE);
428 rcar_i2c_write(priv, ICDMAER, TMDMAE);
430 dma_async_issue_pending(chan);
433 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
435 struct i2c_msg *msg = priv->msg;
437 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
441 if (priv->pos < msg->len) {
443 * Prepare next data to ICRXTX register.
444 * This data will go to _SHIFT_ register.
447 * [ICRXTX] -> [SHIFT] -> [I2C bus]
449 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
453 * Try to use DMA to transmit the rest of the data if
454 * address transfer pashe just finished.
460 * The last data was pushed to ICRXTX on _PREV_ empty irq.
461 * It is on _SHIFT_ register, and will sent to I2C bus.
464 * [ICRXTX] -> [SHIFT] -> [I2C bus]
467 if (priv->flags & ID_LAST_MSG) {
469 * If current msg is the _LAST_ msg,
470 * prepare stop condition here.
471 * ID_DONE will be set on STOP irq.
473 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
475 rcar_i2c_next_msg(priv);
480 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
483 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
485 struct i2c_msg *msg = priv->msg;
487 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
493 * Address transfer phase finished, but no data at this point.
494 * Try to use DMA to receive data.
497 } else if (priv->pos < msg->len) {
498 /* get received data */
499 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
504 * If next received data is the _LAST_, go to STOP phase. Might be
505 * overwritten by REP START when setting up a new msg. Not elegant
506 * but the only stable sequence for REP START I have found so far.
508 if (priv->pos + 1 >= msg->len)
509 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
511 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
512 rcar_i2c_next_msg(priv);
514 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
517 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
519 u32 ssr_raw, ssr_filtered;
522 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
523 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
528 /* address detected */
529 if (ssr_filtered & SAR) {
530 /* read or write request */
532 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
533 rcar_i2c_write(priv, ICRXTX, value);
534 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
536 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
537 rcar_i2c_read(priv, ICRXTX); /* dummy read */
538 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
541 /* Clear SSR, too, because of old STOPs to other clients than us */
542 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
545 /* master sent stop */
546 if (ssr_filtered & SSR) {
547 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
548 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
549 rcar_i2c_write(priv, ICSIER, SAR);
550 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
553 /* master wants to write to us */
554 if (ssr_filtered & SDR) {
557 value = rcar_i2c_read(priv, ICRXTX);
558 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
559 /* Send NACK in case of error */
560 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
561 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
564 /* master wants to read from us */
565 if (ssr_filtered & SDE) {
566 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
567 rcar_i2c_write(priv, ICRXTX, value);
568 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
574 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
576 struct rcar_i2c_priv *priv = ptr;
579 /* Clear START or STOP as soon as we can */
580 val = rcar_i2c_read(priv, ICMCR);
581 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
583 msr = rcar_i2c_read(priv, ICMSR);
585 /* Only handle interrupts that are currently enabled */
586 msr &= rcar_i2c_read(priv, ICMIER);
588 if (rcar_i2c_slave_irq(priv))
594 /* Arbitration lost */
596 priv->flags |= ID_DONE | ID_ARBLOST;
602 /* HW automatically sends STOP after received NACK */
603 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
604 priv->flags |= ID_NACK;
610 priv->msgs_left--; /* The last message also made it */
611 priv->flags |= ID_DONE;
615 if (rcar_i2c_is_recv(priv))
616 rcar_i2c_irq_recv(priv, msr);
618 rcar_i2c_irq_send(priv, msr);
621 if (priv->flags & ID_DONE) {
622 rcar_i2c_write(priv, ICMIER, 0);
623 rcar_i2c_write(priv, ICMSR, 0);
624 wake_up(&priv->wait);
630 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
631 enum dma_transfer_direction dir,
632 dma_addr_t port_addr)
634 struct dma_chan *chan;
635 struct dma_slave_config cfg;
636 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
639 chan = dma_request_chan(dev, chan_name);
641 dev_dbg(dev, "request_channel failed for %s (%ld)\n",
642 chan_name, PTR_ERR(chan));
646 memset(&cfg, 0, sizeof(cfg));
648 if (dir == DMA_MEM_TO_DEV) {
649 cfg.dst_addr = port_addr;
650 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
652 cfg.src_addr = port_addr;
653 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
656 ret = dmaengine_slave_config(chan, &cfg);
658 dev_dbg(dev, "slave_config failed for %s (%d)\n",
660 dma_release_channel(chan);
664 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
668 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
671 struct device *dev = rcar_i2c_priv_to_dev(priv);
673 struct dma_chan *chan;
674 enum dma_transfer_direction dir;
676 read = msg->flags & I2C_M_RD;
678 chan = read ? priv->dma_rx : priv->dma_tx;
679 if (PTR_ERR(chan) != -EPROBE_DEFER)
682 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
683 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
691 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
693 if (!IS_ERR(priv->dma_tx)) {
694 dma_release_channel(priv->dma_tx);
695 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
698 if (!IS_ERR(priv->dma_rx)) {
699 dma_release_channel(priv->dma_rx);
700 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
704 /* I2C is a special case, we need to poll the status of a reset */
705 static int rcar_i2c_do_reset(struct rcar_i2c_priv *priv)
709 ret = reset_control_reset(priv->rstc);
713 for (i = 0; i < LOOP_TIMEOUT; i++) {
714 ret = reset_control_status(priv->rstc);
723 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
724 struct i2c_msg *msgs,
727 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
728 struct device *dev = rcar_i2c_priv_to_dev(priv);
732 pm_runtime_get_sync(dev);
734 /* Gen3 needs a reset before allowing RXDMA once */
735 if (priv->devtype == I2C_RCAR_GEN3) {
736 priv->flags |= ID_P_NO_RXDMA;
737 if (!IS_ERR(priv->rstc)) {
738 ret = rcar_i2c_do_reset(priv);
740 priv->flags &= ~ID_P_NO_RXDMA;
746 ret = rcar_i2c_bus_barrier(priv);
750 for (i = 0; i < num; i++) {
751 /* This HW can't send STOP after address phase */
752 if (msgs[i].len == 0) {
756 rcar_i2c_request_dma(priv, msgs + i);
759 /* init first message */
761 priv->msgs_left = num;
762 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
763 rcar_i2c_prepare_msg(priv);
765 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
766 num * adap->timeout);
768 /* cleanup DMA if it couldn't complete properly due to an error */
769 if (priv->dma_direction != DMA_NONE)
770 rcar_i2c_cleanup_dma(priv);
775 } else if (priv->flags & ID_NACK) {
777 } else if (priv->flags & ID_ARBLOST) {
780 ret = num - priv->msgs_left; /* The number of transfer */
785 if (ret < 0 && ret != -ENXIO)
786 dev_err(dev, "error %d : %x\n", ret, priv->flags);
791 static int rcar_reg_slave(struct i2c_client *slave)
793 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
798 if (slave->flags & I2C_CLIENT_TEN)
799 return -EAFNOSUPPORT;
801 /* Keep device active for slave address detection logic */
802 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
805 rcar_i2c_write(priv, ICSAR, slave->addr);
806 rcar_i2c_write(priv, ICSSR, 0);
807 rcar_i2c_write(priv, ICSIER, SAR);
808 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
813 static int rcar_unreg_slave(struct i2c_client *slave)
815 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
817 WARN_ON(!priv->slave);
819 /* ensure no irq is running before clearing ptr */
820 disable_irq(priv->irq);
821 rcar_i2c_write(priv, ICSIER, 0);
822 rcar_i2c_write(priv, ICSSR, 0);
823 enable_irq(priv->irq);
824 rcar_i2c_write(priv, ICSCR, SDBS);
825 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
829 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
834 static u32 rcar_i2c_func(struct i2c_adapter *adap)
838 * I2C_SMBUS_QUICK (setting FSB during START didn't work)
839 * I2C_M_NOSTART (automatically sends address after START)
840 * I2C_M_IGNORE_NAK (automatically sends STOP after NAK)
842 return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
843 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
846 static const struct i2c_algorithm rcar_i2c_algo = {
847 .master_xfer = rcar_i2c_master_xfer,
848 .functionality = rcar_i2c_func,
849 .reg_slave = rcar_reg_slave,
850 .unreg_slave = rcar_unreg_slave,
853 static const struct of_device_id rcar_i2c_dt_ids[] = {
854 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
855 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
856 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
857 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
858 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
859 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
860 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
861 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
862 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
863 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 }, /* Deprecated */
864 { .compatible = "renesas,rcar-gen1-i2c", .data = (void *)I2C_RCAR_GEN1 },
865 { .compatible = "renesas,rcar-gen2-i2c", .data = (void *)I2C_RCAR_GEN2 },
866 { .compatible = "renesas,rcar-gen3-i2c", .data = (void *)I2C_RCAR_GEN3 },
869 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
871 static int rcar_i2c_probe(struct platform_device *pdev)
873 struct rcar_i2c_priv *priv;
874 struct i2c_adapter *adap;
875 struct device *dev = &pdev->dev;
876 struct i2c_timings i2c_t;
879 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
883 priv->clk = devm_clk_get(dev, NULL);
884 if (IS_ERR(priv->clk)) {
885 dev_err(dev, "cannot get clock\n");
886 return PTR_ERR(priv->clk);
889 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
891 priv->io = devm_ioremap_resource(dev, priv->res);
892 if (IS_ERR(priv->io))
893 return PTR_ERR(priv->io);
895 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
896 init_waitqueue_head(&priv->wait);
900 adap->algo = &rcar_i2c_algo;
901 adap->class = I2C_CLASS_DEPRECATED;
903 adap->dev.parent = dev;
904 adap->dev.of_node = dev->of_node;
905 i2c_set_adapdata(adap, priv);
906 strlcpy(adap->name, pdev->name, sizeof(adap->name));
908 i2c_parse_fw_timings(dev, &i2c_t, false);
911 sg_init_table(&priv->sg, 1);
912 priv->dma_direction = DMA_NONE;
913 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
915 /* Activate device for clock calculation */
916 pm_runtime_enable(dev);
917 pm_runtime_get_sync(dev);
918 ret = rcar_i2c_clock_calculate(priv, &i2c_t);
922 rcar_i2c_write(priv, ICSAR, 0); /* Gen2: must be 0 if not using slave */
924 if (priv->devtype == I2C_RCAR_GEN3) {
925 priv->rstc = devm_reset_control_get_exclusive(&pdev->dev, NULL);
926 if (!IS_ERR(priv->rstc)) {
927 ret = reset_control_status(priv->rstc);
929 priv->rstc = ERR_PTR(-ENOTSUPP);
933 /* Stay always active when multi-master to keep arbitration working */
934 if (of_property_read_bool(dev->of_node, "multi-master"))
935 priv->flags |= ID_P_PM_BLOCKED;
940 priv->irq = platform_get_irq(pdev, 0);
941 ret = devm_request_irq(dev, priv->irq, rcar_i2c_irq, 0, dev_name(dev), priv);
943 dev_err(dev, "cannot get irq %d\n", priv->irq);
947 platform_set_drvdata(pdev, priv);
949 ret = i2c_add_numbered_adapter(adap);
953 dev_info(dev, "probed\n");
960 pm_runtime_disable(dev);
964 static int rcar_i2c_remove(struct platform_device *pdev)
966 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
967 struct device *dev = &pdev->dev;
969 i2c_del_adapter(&priv->adap);
970 rcar_i2c_release_dma(priv);
971 if (priv->flags & ID_P_PM_BLOCKED)
973 pm_runtime_disable(dev);
978 static struct platform_driver rcar_i2c_driver = {
981 .of_match_table = rcar_i2c_dt_ids,
983 .probe = rcar_i2c_probe,
984 .remove = rcar_i2c_remove,
987 module_platform_driver(rcar_i2c_driver);
989 MODULE_LICENSE("GPL v2");
990 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
991 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");