2 * Driver for the Renesas RCar I2C unit
4 * Copyright (C) 2014-15 Wolfram Sang <wsa@sang-engineering.com>
5 * Copyright (C) 2011-2015 Renesas Electronics Corporation
7 * Copyright (C) 2012-14 Renesas Solutions Corp.
8 * Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
10 * This file is based on the drivers/i2c/busses/i2c-sh7760.c
11 * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
22 #include <linux/clk.h>
23 #include <linux/delay.h>
24 #include <linux/dmaengine.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/err.h>
27 #include <linux/interrupt.h>
29 #include <linux/i2c.h>
30 #include <linux/kernel.h>
31 #include <linux/module.h>
32 #include <linux/of_device.h>
33 #include <linux/platform_device.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/slab.h>
37 /* register offsets */
38 #define ICSCR 0x00 /* slave ctrl */
39 #define ICMCR 0x04 /* master ctrl */
40 #define ICSSR 0x08 /* slave status */
41 #define ICMSR 0x0C /* master status */
42 #define ICSIER 0x10 /* slave irq enable */
43 #define ICMIER 0x14 /* master irq enable */
44 #define ICCCR 0x18 /* clock dividers */
45 #define ICSAR 0x1C /* slave address */
46 #define ICMAR 0x20 /* master address */
47 #define ICRXTX 0x24 /* data port */
48 #define ICDMAER 0x3c /* DMA enable */
49 #define ICFBSCR 0x38 /* first bit setup cycle */
52 #define SDBS (1 << 3) /* slave data buffer select */
53 #define SIE (1 << 2) /* slave interface enable */
54 #define GCAE (1 << 1) /* general call address enable */
55 #define FNA (1 << 0) /* forced non acknowledgment */
58 #define MDBS (1 << 7) /* non-fifo mode switch */
59 #define FSCL (1 << 6) /* override SCL pin */
60 #define FSDA (1 << 5) /* override SDA pin */
61 #define OBPC (1 << 4) /* override pins */
62 #define MIE (1 << 3) /* master if enable */
64 #define FSB (1 << 1) /* force stop bit */
65 #define ESG (1 << 0) /* en startbit gen */
67 /* ICSSR (also for ICSIER) */
68 #define GCAR (1 << 6) /* general call received */
69 #define STM (1 << 5) /* slave transmit mode */
70 #define SSR (1 << 4) /* stop received */
71 #define SDE (1 << 3) /* slave data empty */
72 #define SDT (1 << 2) /* slave data transmitted */
73 #define SDR (1 << 1) /* slave data received */
74 #define SAR (1 << 0) /* slave addr received */
76 /* ICMSR (also for ICMIE) */
77 #define MNR (1 << 6) /* nack received */
78 #define MAL (1 << 5) /* arbitration lost */
79 #define MST (1 << 4) /* sent a stop */
83 #define MAT (1 << 0) /* slave addr xfer done */
86 #define RSDMAE (1 << 3) /* DMA Slave Received Enable */
87 #define TSDMAE (1 << 2) /* DMA Slave Transmitted Enable */
88 #define RMDMAE (1 << 1) /* DMA Master Received Enable */
89 #define TMDMAE (1 << 0) /* DMA Master Transmitted Enable */
92 #define TCYC06 0x04 /* 6*Tcyc delay 1st bit between SDA and SCL */
93 #define TCYC17 0x0f /* 17*Tcyc delay 1st bit between SDA and SCL */
96 #define RCAR_BUS_PHASE_START (MDBS | MIE | ESG)
97 #define RCAR_BUS_PHASE_DATA (MDBS | MIE)
98 #define RCAR_BUS_MASK_DATA (~(ESG | FSB) & 0xFF)
99 #define RCAR_BUS_PHASE_STOP (MDBS | MIE | FSB)
101 #define RCAR_IRQ_SEND (MNR | MAL | MST | MAT | MDE)
102 #define RCAR_IRQ_RECV (MNR | MAL | MST | MAT | MDR)
103 #define RCAR_IRQ_STOP (MST)
105 #define RCAR_IRQ_ACK_SEND (~(MAT | MDE) & 0xFF)
106 #define RCAR_IRQ_ACK_RECV (~(MAT | MDR) & 0xFF)
108 #define ID_LAST_MSG (1 << 0)
109 #define ID_FIRST_MSG (1 << 1)
110 #define ID_DONE (1 << 2)
111 #define ID_ARBLOST (1 << 3)
112 #define ID_NACK (1 << 4)
113 /* persistent flags */
114 #define ID_P_PM_BLOCKED (1 << 31)
115 #define ID_P_MASK ID_P_PM_BLOCKED
123 struct rcar_i2c_priv {
125 struct i2c_adapter adap;
130 wait_queue_head_t wait;
135 enum rcar_i2c_type devtype;
136 struct i2c_client *slave;
138 struct resource *res;
139 struct dma_chan *dma_tx;
140 struct dma_chan *dma_rx;
141 struct scatterlist sg;
142 enum dma_data_direction dma_direction;
145 #define rcar_i2c_priv_to_dev(p) ((p)->adap.dev.parent)
146 #define rcar_i2c_is_recv(p) ((p)->msg->flags & I2C_M_RD)
148 #define LOOP_TIMEOUT 1024
151 static void rcar_i2c_write(struct rcar_i2c_priv *priv, int reg, u32 val)
153 writel(val, priv->io + reg);
156 static u32 rcar_i2c_read(struct rcar_i2c_priv *priv, int reg)
158 return readl(priv->io + reg);
161 static void rcar_i2c_init(struct rcar_i2c_priv *priv)
163 /* reset master mode */
164 rcar_i2c_write(priv, ICMIER, 0);
165 rcar_i2c_write(priv, ICMCR, MDBS);
166 rcar_i2c_write(priv, ICMSR, 0);
168 rcar_i2c_write(priv, ICCCR, priv->icccr);
171 static int rcar_i2c_bus_barrier(struct rcar_i2c_priv *priv)
175 for (i = 0; i < LOOP_TIMEOUT; i++) {
176 /* make sure that bus is not busy */
177 if (!(rcar_i2c_read(priv, ICMCR) & FSDA))
185 static int rcar_i2c_clock_calculate(struct rcar_i2c_priv *priv, struct i2c_timings *t)
187 u32 scgd, cdf, round, ick, sum, scl, cdf_width;
189 struct device *dev = rcar_i2c_priv_to_dev(priv);
191 /* Fall back to previously used values if not supplied */
192 t->bus_freq_hz = t->bus_freq_hz ?: 100000;
193 t->scl_fall_ns = t->scl_fall_ns ?: 35;
194 t->scl_rise_ns = t->scl_rise_ns ?: 200;
195 t->scl_int_delay_ns = t->scl_int_delay_ns ?: 50;
197 switch (priv->devtype) {
206 dev_err(dev, "device type error\n");
211 * calculate SCL clock
215 * ick = clkp / (1 + CDF)
216 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
218 * ick : I2C internal clock < 20 MHz
219 * ticf : I2C SCL falling time
220 * tr : I2C SCL rising time
221 * intd : LSI internal delay
222 * clkp : peripheral_clk
223 * F[] : integer up-valuation
225 rate = clk_get_rate(priv->clk);
226 cdf = rate / 20000000;
227 if (cdf >= 1U << cdf_width) {
228 dev_err(dev, "Input clock %lu too high\n", rate);
231 ick = rate / (cdf + 1);
234 * it is impossible to calculate large scale
235 * number on u32. separate it
237 * F[(ticf + tr + intd) * ick] with sum = (ticf + tr + intd)
238 * = F[sum * ick / 1000000000]
239 * = F[(ick / 1000000) * sum / 1000]
241 sum = t->scl_fall_ns + t->scl_rise_ns + t->scl_int_delay_ns;
242 round = (ick + 500000) / 1000000 * sum;
243 round = (round + 500) / 1000;
246 * SCL = ick / (20 + SCGD * 8 + F[(ticf + tr + intd) * ick])
248 * Calculation result (= SCL) should be less than
249 * bus_speed for hardware safety
251 * We could use something along the lines of
252 * div = ick / (bus_speed + 1) + 1;
253 * scgd = (div - 20 - round + 7) / 8;
254 * scl = ick / (20 + (scgd * 8) + round);
255 * (not fully verified) but that would get pretty involved
257 for (scgd = 0; scgd < 0x40; scgd++) {
258 scl = ick / (20 + (scgd * 8) + round);
259 if (scl <= t->bus_freq_hz)
262 dev_err(dev, "it is impossible to calculate best SCL\n");
266 dev_dbg(dev, "clk %d/%d(%lu), round %u, CDF:0x%x, SCGD: 0x%x\n",
267 scl, t->bus_freq_hz, clk_get_rate(priv->clk), round, cdf, scgd);
269 /* keep icccr value */
270 priv->icccr = scgd << cdf_width | cdf;
275 static void rcar_i2c_prepare_msg(struct rcar_i2c_priv *priv)
277 int read = !!rcar_i2c_is_recv(priv);
280 if (priv->msgs_left == 1)
281 priv->flags |= ID_LAST_MSG;
283 rcar_i2c_write(priv, ICMAR, (priv->msg->addr << 1) | read);
285 * We don't have a testcase but the HW engineers say that the write order
286 * of ICMSR and ICMCR depends on whether we issue START or REP_START. Since
287 * it didn't cause a drawback for me, let's rather be safe than sorry.
289 if (priv->flags & ID_FIRST_MSG) {
290 rcar_i2c_write(priv, ICMSR, 0);
291 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
293 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_START);
294 rcar_i2c_write(priv, ICMSR, 0);
296 rcar_i2c_write(priv, ICMIER, read ? RCAR_IRQ_RECV : RCAR_IRQ_SEND);
299 static void rcar_i2c_next_msg(struct rcar_i2c_priv *priv)
303 priv->flags &= ID_P_MASK;
304 rcar_i2c_prepare_msg(priv);
308 * interrupt functions
310 static void rcar_i2c_dma_unmap(struct rcar_i2c_priv *priv)
312 struct dma_chan *chan = priv->dma_direction == DMA_FROM_DEVICE
313 ? priv->dma_rx : priv->dma_tx;
315 /* Disable DMA Master Received/Transmitted */
316 rcar_i2c_write(priv, ICDMAER, 0);
318 /* Reset default delay */
319 rcar_i2c_write(priv, ICFBSCR, TCYC06);
321 dma_unmap_single(chan->device->dev, sg_dma_address(&priv->sg),
322 priv->msg->len, priv->dma_direction);
324 priv->dma_direction = DMA_NONE;
327 static void rcar_i2c_cleanup_dma(struct rcar_i2c_priv *priv)
329 if (priv->dma_direction == DMA_NONE)
331 else if (priv->dma_direction == DMA_FROM_DEVICE)
332 dmaengine_terminate_all(priv->dma_rx);
333 else if (priv->dma_direction == DMA_TO_DEVICE)
334 dmaengine_terminate_all(priv->dma_tx);
336 rcar_i2c_dma_unmap(priv);
339 static void rcar_i2c_dma_callback(void *data)
341 struct rcar_i2c_priv *priv = data;
343 priv->pos += sg_dma_len(&priv->sg);
345 rcar_i2c_dma_unmap(priv);
348 static void rcar_i2c_dma(struct rcar_i2c_priv *priv)
350 struct device *dev = rcar_i2c_priv_to_dev(priv);
351 struct i2c_msg *msg = priv->msg;
352 bool read = msg->flags & I2C_M_RD;
353 enum dma_data_direction dir = read ? DMA_FROM_DEVICE : DMA_TO_DEVICE;
354 struct dma_chan *chan = read ? priv->dma_rx : priv->dma_tx;
355 struct dma_async_tx_descriptor *txdesc;
361 /* Do not use DMA if it's not available or for messages < 8 bytes */
362 if (IS_ERR(chan) || msg->len < 8)
367 * The last two bytes needs to be fetched using PIO in
368 * order for the STOP phase to work.
370 buf = priv->msg->buf;
371 len = priv->msg->len - 2;
374 * First byte in message was sent using PIO.
376 buf = priv->msg->buf + 1;
377 len = priv->msg->len - 1;
380 dma_addr = dma_map_single(chan->device->dev, buf, len, dir);
381 if (dma_mapping_error(chan->device->dev, dma_addr)) {
382 dev_dbg(dev, "dma map failed, using PIO\n");
386 sg_dma_len(&priv->sg) = len;
387 sg_dma_address(&priv->sg) = dma_addr;
389 priv->dma_direction = dir;
391 txdesc = dmaengine_prep_slave_sg(chan, &priv->sg, 1,
392 read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV,
393 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
395 dev_dbg(dev, "dma prep slave sg failed, using PIO\n");
396 rcar_i2c_cleanup_dma(priv);
400 txdesc->callback = rcar_i2c_dma_callback;
401 txdesc->callback_param = priv;
403 cookie = dmaengine_submit(txdesc);
404 if (dma_submit_error(cookie)) {
405 dev_dbg(dev, "submitting dma failed, using PIO\n");
406 rcar_i2c_cleanup_dma(priv);
410 /* Set delay for DMA operations */
411 rcar_i2c_write(priv, ICFBSCR, TCYC17);
413 /* Enable DMA Master Received/Transmitted */
415 rcar_i2c_write(priv, ICDMAER, RMDMAE);
417 rcar_i2c_write(priv, ICDMAER, TMDMAE);
419 dma_async_issue_pending(chan);
422 static void rcar_i2c_irq_send(struct rcar_i2c_priv *priv, u32 msr)
424 struct i2c_msg *msg = priv->msg;
426 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
430 if (priv->pos < msg->len) {
432 * Prepare next data to ICRXTX register.
433 * This data will go to _SHIFT_ register.
436 * [ICRXTX] -> [SHIFT] -> [I2C bus]
438 rcar_i2c_write(priv, ICRXTX, msg->buf[priv->pos]);
442 * Try to use DMA to transmit the rest of the data if
443 * address transfer pashe just finished.
449 * The last data was pushed to ICRXTX on _PREV_ empty irq.
450 * It is on _SHIFT_ register, and will sent to I2C bus.
453 * [ICRXTX] -> [SHIFT] -> [I2C bus]
456 if (priv->flags & ID_LAST_MSG) {
458 * If current msg is the _LAST_ msg,
459 * prepare stop condition here.
460 * ID_DONE will be set on STOP irq.
462 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
464 rcar_i2c_next_msg(priv);
469 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_SEND);
472 static void rcar_i2c_irq_recv(struct rcar_i2c_priv *priv, u32 msr)
474 struct i2c_msg *msg = priv->msg;
476 /* FIXME: sometimes, unknown interrupt happened. Do nothing */
482 * Address transfer phase finished, but no data at this point.
483 * Try to use DMA to receive data.
486 } else if (priv->pos < msg->len) {
487 /* get received data */
488 msg->buf[priv->pos] = rcar_i2c_read(priv, ICRXTX);
493 * If next received data is the _LAST_, go to STOP phase. Might be
494 * overwritten by REP START when setting up a new msg. Not elegant
495 * but the only stable sequence for REP START I have found so far.
497 if (priv->pos + 1 >= msg->len)
498 rcar_i2c_write(priv, ICMCR, RCAR_BUS_PHASE_STOP);
500 if (priv->pos == msg->len && !(priv->flags & ID_LAST_MSG))
501 rcar_i2c_next_msg(priv);
503 rcar_i2c_write(priv, ICMSR, RCAR_IRQ_ACK_RECV);
506 static bool rcar_i2c_slave_irq(struct rcar_i2c_priv *priv)
508 u32 ssr_raw, ssr_filtered;
511 ssr_raw = rcar_i2c_read(priv, ICSSR) & 0xff;
512 ssr_filtered = ssr_raw & rcar_i2c_read(priv, ICSIER);
517 /* address detected */
518 if (ssr_filtered & SAR) {
519 /* read or write request */
521 i2c_slave_event(priv->slave, I2C_SLAVE_READ_REQUESTED, &value);
522 rcar_i2c_write(priv, ICRXTX, value);
523 rcar_i2c_write(priv, ICSIER, SDE | SSR | SAR);
525 i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_REQUESTED, &value);
526 rcar_i2c_read(priv, ICRXTX); /* dummy read */
527 rcar_i2c_write(priv, ICSIER, SDR | SSR | SAR);
530 /* Clear SSR, too, because of old STOPs to other clients than us */
531 rcar_i2c_write(priv, ICSSR, ~(SAR | SSR) & 0xff);
534 /* master sent stop */
535 if (ssr_filtered & SSR) {
536 i2c_slave_event(priv->slave, I2C_SLAVE_STOP, &value);
537 rcar_i2c_write(priv, ICSCR, SIE | SDBS); /* clear our NACK */
538 rcar_i2c_write(priv, ICSIER, SAR);
539 rcar_i2c_write(priv, ICSSR, ~SSR & 0xff);
542 /* master wants to write to us */
543 if (ssr_filtered & SDR) {
546 value = rcar_i2c_read(priv, ICRXTX);
547 ret = i2c_slave_event(priv->slave, I2C_SLAVE_WRITE_RECEIVED, &value);
548 /* Send NACK in case of error */
549 rcar_i2c_write(priv, ICSCR, SIE | SDBS | (ret < 0 ? FNA : 0));
550 rcar_i2c_write(priv, ICSSR, ~SDR & 0xff);
553 /* master wants to read from us */
554 if (ssr_filtered & SDE) {
555 i2c_slave_event(priv->slave, I2C_SLAVE_READ_PROCESSED, &value);
556 rcar_i2c_write(priv, ICRXTX, value);
557 rcar_i2c_write(priv, ICSSR, ~SDE & 0xff);
563 static irqreturn_t rcar_i2c_irq(int irq, void *ptr)
565 struct rcar_i2c_priv *priv = ptr;
568 /* Clear START or STOP as soon as we can */
569 val = rcar_i2c_read(priv, ICMCR);
570 rcar_i2c_write(priv, ICMCR, val & RCAR_BUS_MASK_DATA);
572 msr = rcar_i2c_read(priv, ICMSR);
574 /* Only handle interrupts that are currently enabled */
575 msr &= rcar_i2c_read(priv, ICMIER);
577 if (rcar_i2c_slave_irq(priv))
583 /* Arbitration lost */
585 priv->flags |= ID_DONE | ID_ARBLOST;
591 /* HW automatically sends STOP after received NACK */
592 rcar_i2c_write(priv, ICMIER, RCAR_IRQ_STOP);
593 priv->flags |= ID_NACK;
599 priv->msgs_left--; /* The last message also made it */
600 priv->flags |= ID_DONE;
604 if (rcar_i2c_is_recv(priv))
605 rcar_i2c_irq_recv(priv, msr);
607 rcar_i2c_irq_send(priv, msr);
610 if (priv->flags & ID_DONE) {
611 rcar_i2c_write(priv, ICMIER, 0);
612 rcar_i2c_write(priv, ICMSR, 0);
613 wake_up(&priv->wait);
619 static struct dma_chan *rcar_i2c_request_dma_chan(struct device *dev,
620 enum dma_transfer_direction dir,
621 dma_addr_t port_addr)
623 struct dma_chan *chan;
624 struct dma_slave_config cfg;
625 char *chan_name = dir == DMA_MEM_TO_DEV ? "tx" : "rx";
628 chan = dma_request_chan(dev, chan_name);
631 dev_dbg(dev, "request_channel failed for %s (%d)\n",
636 memset(&cfg, 0, sizeof(cfg));
638 if (dir == DMA_MEM_TO_DEV) {
639 cfg.dst_addr = port_addr;
640 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
642 cfg.src_addr = port_addr;
643 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
646 ret = dmaengine_slave_config(chan, &cfg);
648 dev_dbg(dev, "slave_config failed for %s (%d)\n",
650 dma_release_channel(chan);
654 dev_dbg(dev, "got DMA channel for %s\n", chan_name);
658 static void rcar_i2c_request_dma(struct rcar_i2c_priv *priv,
661 struct device *dev = rcar_i2c_priv_to_dev(priv);
663 struct dma_chan *chan;
664 enum dma_transfer_direction dir;
666 read = msg->flags & I2C_M_RD;
668 chan = read ? priv->dma_rx : priv->dma_tx;
669 if (PTR_ERR(chan) != -EPROBE_DEFER)
672 dir = read ? DMA_DEV_TO_MEM : DMA_MEM_TO_DEV;
673 chan = rcar_i2c_request_dma_chan(dev, dir, priv->res->start + ICRXTX);
681 static void rcar_i2c_release_dma(struct rcar_i2c_priv *priv)
683 if (!IS_ERR(priv->dma_tx)) {
684 dma_release_channel(priv->dma_tx);
685 priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
688 if (!IS_ERR(priv->dma_rx)) {
689 dma_release_channel(priv->dma_rx);
690 priv->dma_rx = ERR_PTR(-EPROBE_DEFER);
694 static int rcar_i2c_master_xfer(struct i2c_adapter *adap,
695 struct i2c_msg *msgs,
698 struct rcar_i2c_priv *priv = i2c_get_adapdata(adap);
699 struct device *dev = rcar_i2c_priv_to_dev(priv);
703 pm_runtime_get_sync(dev);
707 ret = rcar_i2c_bus_barrier(priv);
711 for (i = 0; i < num; i++) {
712 /* This HW can't send STOP after address phase */
713 if (msgs[i].len == 0) {
717 rcar_i2c_request_dma(priv, msgs + i);
720 /* init first message */
722 priv->msgs_left = num;
723 priv->flags = (priv->flags & ID_P_MASK) | ID_FIRST_MSG;
724 rcar_i2c_prepare_msg(priv);
726 time_left = wait_event_timeout(priv->wait, priv->flags & ID_DONE,
727 num * adap->timeout);
729 /* cleanup DMA if it couldn't complete properly due to an error */
730 if (priv->dma_direction != DMA_NONE)
731 rcar_i2c_cleanup_dma(priv);
736 } else if (priv->flags & ID_NACK) {
738 } else if (priv->flags & ID_ARBLOST) {
741 ret = num - priv->msgs_left; /* The number of transfer */
746 if (ret < 0 && ret != -ENXIO)
747 dev_err(dev, "error %d : %x\n", ret, priv->flags);
752 static int rcar_reg_slave(struct i2c_client *slave)
754 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
759 if (slave->flags & I2C_CLIENT_TEN)
760 return -EAFNOSUPPORT;
762 pm_runtime_get_sync(rcar_i2c_priv_to_dev(priv));
765 rcar_i2c_write(priv, ICSAR, slave->addr);
766 rcar_i2c_write(priv, ICSSR, 0);
767 rcar_i2c_write(priv, ICSIER, SAR);
768 rcar_i2c_write(priv, ICSCR, SIE | SDBS);
773 static int rcar_unreg_slave(struct i2c_client *slave)
775 struct rcar_i2c_priv *priv = i2c_get_adapdata(slave->adapter);
777 WARN_ON(!priv->slave);
779 rcar_i2c_write(priv, ICSIER, 0);
780 rcar_i2c_write(priv, ICSCR, 0);
784 pm_runtime_put(rcar_i2c_priv_to_dev(priv));
789 static u32 rcar_i2c_func(struct i2c_adapter *adap)
791 /* This HW can't do SMBUS_QUICK and NOSTART */
792 return I2C_FUNC_I2C | I2C_FUNC_SLAVE |
793 (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
796 static const struct i2c_algorithm rcar_i2c_algo = {
797 .master_xfer = rcar_i2c_master_xfer,
798 .functionality = rcar_i2c_func,
799 .reg_slave = rcar_reg_slave,
800 .unreg_slave = rcar_unreg_slave,
803 static const struct of_device_id rcar_i2c_dt_ids[] = {
804 { .compatible = "renesas,i2c-rcar", .data = (void *)I2C_RCAR_GEN1 },
805 { .compatible = "renesas,i2c-r8a7778", .data = (void *)I2C_RCAR_GEN1 },
806 { .compatible = "renesas,i2c-r8a7779", .data = (void *)I2C_RCAR_GEN1 },
807 { .compatible = "renesas,i2c-r8a7790", .data = (void *)I2C_RCAR_GEN2 },
808 { .compatible = "renesas,i2c-r8a7791", .data = (void *)I2C_RCAR_GEN2 },
809 { .compatible = "renesas,i2c-r8a7792", .data = (void *)I2C_RCAR_GEN2 },
810 { .compatible = "renesas,i2c-r8a7793", .data = (void *)I2C_RCAR_GEN2 },
811 { .compatible = "renesas,i2c-r8a7794", .data = (void *)I2C_RCAR_GEN2 },
812 { .compatible = "renesas,i2c-r8a7795", .data = (void *)I2C_RCAR_GEN3 },
813 { .compatible = "renesas,i2c-r8a7796", .data = (void *)I2C_RCAR_GEN3 },
816 MODULE_DEVICE_TABLE(of, rcar_i2c_dt_ids);
818 static int rcar_i2c_probe(struct platform_device *pdev)
820 struct rcar_i2c_priv *priv;
821 struct i2c_adapter *adap;
822 struct device *dev = &pdev->dev;
823 struct i2c_timings i2c_t;
826 priv = devm_kzalloc(dev, sizeof(struct rcar_i2c_priv), GFP_KERNEL);
830 priv->clk = devm_clk_get(dev, NULL);
831 if (IS_ERR(priv->clk)) {
832 dev_err(dev, "cannot get clock\n");
833 return PTR_ERR(priv->clk);
836 priv->res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
838 priv->io = devm_ioremap_resource(dev, priv->res);
839 if (IS_ERR(priv->io))
840 return PTR_ERR(priv->io);
842 priv->devtype = (enum rcar_i2c_type)of_device_get_match_data(dev);
843 init_waitqueue_head(&priv->wait);
847 adap->algo = &rcar_i2c_algo;
848 adap->class = I2C_CLASS_DEPRECATED;
850 adap->dev.parent = dev;
851 adap->dev.of_node = dev->of_node;
852 i2c_set_adapdata(adap, priv);
853 strlcpy(adap->name, pdev->name, sizeof(adap->name));
855 i2c_parse_fw_timings(dev, &i2c_t, false);
858 sg_init_table(&priv->sg, 1);
859 priv->dma_direction = DMA_NONE;
860 priv->dma_rx = priv->dma_tx = ERR_PTR(-EPROBE_DEFER);
862 pm_runtime_enable(dev);
863 pm_runtime_get_sync(dev);
864 ret = rcar_i2c_clock_calculate(priv, &i2c_t);
868 /* Don't suspend when multi-master to keep arbitration working */
869 if (of_property_read_bool(dev->of_node, "multi-master"))
870 priv->flags |= ID_P_PM_BLOCKED;
875 irq = platform_get_irq(pdev, 0);
876 ret = devm_request_irq(dev, irq, rcar_i2c_irq, 0, dev_name(dev), priv);
878 dev_err(dev, "cannot get irq %d\n", irq);
882 platform_set_drvdata(pdev, priv);
884 ret = i2c_add_numbered_adapter(adap);
888 dev_info(dev, "probed\n");
895 pm_runtime_disable(dev);
899 static int rcar_i2c_remove(struct platform_device *pdev)
901 struct rcar_i2c_priv *priv = platform_get_drvdata(pdev);
902 struct device *dev = &pdev->dev;
904 i2c_del_adapter(&priv->adap);
905 rcar_i2c_release_dma(priv);
906 if (priv->flags & ID_P_PM_BLOCKED)
908 pm_runtime_disable(dev);
913 static struct platform_driver rcar_i2c_driver = {
916 .of_match_table = rcar_i2c_dt_ids,
918 .probe = rcar_i2c_probe,
919 .remove = rcar_i2c_remove,
922 module_platform_driver(rcar_i2c_driver);
924 MODULE_LICENSE("GPL v2");
925 MODULE_DESCRIPTION("Renesas R-Car I2C bus driver");
926 MODULE_AUTHOR("Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>");