1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 #include <linux/acpi.h>
6 #include <linux/dma-mapping.h>
9 #include <linux/interrupt.h>
11 #include <linux/module.h>
13 #include <linux/platform_device.h>
14 #include <linux/pm_runtime.h>
15 #include <linux/qcom-geni-se.h>
16 #include <linux/spinlock.h>
18 #define SE_I2C_TX_TRANS_LEN 0x26c
19 #define SE_I2C_RX_TRANS_LEN 0x270
20 #define SE_I2C_SCL_COUNTERS 0x278
22 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
23 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
24 #define SE_I2C_ABORT BIT(1)
26 /* M_CMD OP codes for I2C */
29 #define I2C_WRITE_READ 0x3
30 #define I2C_ADDR_ONLY 0x4
31 #define I2C_BUS_CLEAR 0x6
32 #define I2C_STOP_ON_BUS 0x7
33 /* M_CMD params for I2C */
34 #define PRE_CMD_DELAY BIT(0)
35 #define TIMESTAMP_BEFORE BIT(1)
36 #define STOP_STRETCH BIT(2)
37 #define TIMESTAMP_AFTER BIT(3)
38 #define POST_COMMAND_DELAY BIT(4)
39 #define IGNORE_ADD_NACK BIT(6)
40 #define READ_FINISHED_WITH_ACK BIT(7)
41 #define BYPASS_ADDR_PHASE BIT(8)
42 #define SLV_ADDR_MSK GENMASK(15, 9)
43 #define SLV_ADDR_SHFT 9
44 /* I2C SCL COUNTER fields */
45 #define HIGH_COUNTER_MSK GENMASK(29, 20)
46 #define HIGH_COUNTER_SHFT 20
47 #define LOW_COUNTER_MSK GENMASK(19, 10)
48 #define LOW_COUNTER_SHFT 10
49 #define CYCLE_COUNTER_MSK GENMASK(9, 0)
51 enum geni_i2c_err_code {
64 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
67 #define I2C_AUTO_SUSPEND_DELAY 250
68 #define KHZ(freq) (1000 * freq)
69 #define PACKING_BYTES_PW 4
71 #define ABORT_TIMEOUT HZ
72 #define XFER_TIMEOUT HZ
73 #define RST_TIMEOUT HZ
80 struct i2c_adapter adap;
81 struct completion done;
87 const struct geni_i2c_clk_fld *clk_fld;
94 struct geni_i2c_err_log {
99 static const struct geni_i2c_err_log gi2c_log[] = {
100 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
101 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
102 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
103 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unepxected start/stop"},
104 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
105 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
106 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
107 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
108 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
109 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
112 struct geni_i2c_clk_fld {
121 * Hardware uses the underlying formula to calculate time periods of
122 * SCL clock cycle. Firmware uses some additional cycles excluded from the
123 * below formula and it is confirmed that the time periods are within
124 * specification limits.
126 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
127 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
128 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
129 * clk_freq_out = t / t_cycle
130 * source_clock = 19.2 MHz
132 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
133 {KHZ(100), 7, 10, 11, 26},
134 {KHZ(400), 2, 5, 12, 24},
135 {KHZ(1000), 1, 3, 9, 18},
138 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
141 const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
143 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
144 if (itr->clk_freq_out == gi2c->clk_freq_out) {
152 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
154 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
157 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
159 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
160 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
162 val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
163 val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
164 val |= itr->t_cycle_cnt;
165 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
168 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
170 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
171 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
172 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
173 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
174 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
178 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
179 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
181 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
182 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
184 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
185 dma, tx_st, rx_st, m_stat);
186 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
187 m_cmd, geni_s, geni_ios);
190 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
193 gi2c->err = gi2c_log[err].err;
195 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
196 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
198 if (err != NACK && err != GENI_ABORT_DONE) {
199 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
200 geni_i2c_err_misc(gi2c);
204 static irqreturn_t geni_i2c_irq(int irq, void *dev)
206 struct geni_i2c_dev *gi2c = dev;
207 void __iomem *base = gi2c->se.base;
217 spin_lock(&gi2c->lock);
218 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
219 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
220 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
221 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
222 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
226 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
227 dm_rx_st & (DM_I2C_CB_ERR)) {
228 if (m_stat & M_GP_IRQ_1_EN)
229 geni_i2c_err(gi2c, NACK);
230 if (m_stat & M_GP_IRQ_3_EN)
231 geni_i2c_err(gi2c, BUS_PROTO);
232 if (m_stat & M_GP_IRQ_4_EN)
233 geni_i2c_err(gi2c, ARB_LOST);
234 if (m_stat & M_CMD_OVERRUN_EN)
235 geni_i2c_err(gi2c, GENI_OVERRUN);
236 if (m_stat & M_ILLEGAL_CMD_EN)
237 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
238 if (m_stat & M_CMD_ABORT_EN)
239 geni_i2c_err(gi2c, GENI_ABORT_DONE);
240 if (m_stat & M_GP_IRQ_0_EN)
241 geni_i2c_err(gi2c, GP_IRQ0);
243 /* Disable the TX Watermark interrupt to stop TX */
245 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
247 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
249 } else if (cur->flags & I2C_M_RD &&
250 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
251 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
253 for (j = 0; j < rxcnt; j++) {
255 val = readl_relaxed(base + SE_GENI_RX_FIFOn);
256 while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
257 cur->buf[gi2c->cur_rd++] = val & 0xff;
261 if (gi2c->cur_rd == cur->len)
264 } else if (!(cur->flags & I2C_M_RD) &&
265 m_stat & M_TX_FIFO_WATERMARK_EN) {
266 for (j = 0; j < gi2c->tx_wm; j++) {
271 while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
272 temp = cur->buf[gi2c->cur_wr++];
273 val |= temp << (p * 8);
276 writel_relaxed(val, base + SE_GENI_TX_FIFOn);
277 /* TX Complete, Disable the TX Watermark interrupt */
278 if (gi2c->cur_wr == cur->len) {
279 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
286 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
289 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
291 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
293 /* if this is err with done-bit not set, handle that through timeout. */
294 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
295 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
296 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
297 complete(&gi2c->done);
299 spin_unlock(&gi2c->lock);
304 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
307 unsigned long time_left = ABORT_TIMEOUT;
310 spin_lock_irqsave(&gi2c->lock, flags);
311 geni_i2c_err(gi2c, GENI_TIMEOUT);
313 geni_se_abort_m_cmd(&gi2c->se);
314 spin_unlock_irqrestore(&gi2c->lock, flags);
316 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
317 val = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
318 } while (!(val & M_CMD_ABORT_EN) && time_left);
320 if (!(val & M_CMD_ABORT_EN))
321 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
324 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
327 unsigned long time_left = RST_TIMEOUT;
329 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
331 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
332 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
333 } while (!(val & RX_RESET_DONE) && time_left);
335 if (!(val & RX_RESET_DONE))
336 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
339 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
342 unsigned long time_left = RST_TIMEOUT;
344 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
346 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
347 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
348 } while (!(val & TX_RESET_DONE) && time_left);
350 if (!(val & TX_RESET_DONE))
351 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
354 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
360 geni_i2c_rx_fsm_rst(gi2c);
361 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
362 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
366 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
372 geni_i2c_tx_fsm_rst(gi2c);
373 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
374 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
378 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
381 dma_addr_t rx_dma = 0;
382 unsigned long time_left;
383 void *dma_buf = NULL;
384 struct geni_se *se = &gi2c->se;
385 size_t len = msg->len;
388 if (!of_machine_is_compatible("lenovo,yoga-c630"))
389 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
392 geni_se_select_mode(se, GENI_SE_DMA);
394 geni_se_select_mode(se, GENI_SE_FIFO);
396 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
397 geni_se_setup_m_cmd(se, I2C_READ, m_param);
399 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
400 geni_se_select_mode(se, GENI_SE_FIFO);
401 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
404 gi2c->xfer_len = len;
405 gi2c->dma_addr = rx_dma;
406 gi2c->dma_buf = dma_buf;
410 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
412 geni_i2c_abort_xfer(gi2c);
414 geni_i2c_rx_msg_cleanup(gi2c, cur);
419 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
422 dma_addr_t tx_dma = 0;
423 unsigned long time_left;
424 void *dma_buf = NULL;
425 struct geni_se *se = &gi2c->se;
426 size_t len = msg->len;
429 if (!of_machine_is_compatible("lenovo,yoga-c630"))
430 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
433 geni_se_select_mode(se, GENI_SE_DMA);
435 geni_se_select_mode(se, GENI_SE_FIFO);
437 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
438 geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
440 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
441 geni_se_select_mode(se, GENI_SE_FIFO);
442 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
445 gi2c->xfer_len = len;
446 gi2c->dma_addr = tx_dma;
447 gi2c->dma_buf = dma_buf;
450 if (!dma_buf) /* Get FIFO IRQ */
451 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
454 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
456 geni_i2c_abort_xfer(gi2c);
458 geni_i2c_tx_msg_cleanup(gi2c, cur);
463 static int geni_i2c_xfer(struct i2c_adapter *adap,
464 struct i2c_msg msgs[],
467 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
471 reinit_completion(&gi2c->done);
472 ret = pm_runtime_get_sync(gi2c->se.dev);
474 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
475 pm_runtime_put_noidle(gi2c->se.dev);
476 /* Set device in suspended since resume failed */
477 pm_runtime_set_suspended(gi2c->se.dev);
481 qcom_geni_i2c_conf(gi2c);
482 for (i = 0; i < num; i++) {
483 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
485 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
487 gi2c->cur = &msgs[i];
488 if (msgs[i].flags & I2C_M_RD)
489 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
491 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
499 pm_runtime_mark_last_busy(gi2c->se.dev);
500 pm_runtime_put_autosuspend(gi2c->se.dev);
506 static u32 geni_i2c_func(struct i2c_adapter *adap)
508 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
511 static const struct i2c_algorithm geni_i2c_algo = {
512 .master_xfer = geni_i2c_xfer,
513 .functionality = geni_i2c_func,
517 static const struct acpi_device_id geni_i2c_acpi_match[] = {
521 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
524 static int geni_i2c_probe(struct platform_device *pdev)
526 struct geni_i2c_dev *gi2c;
527 struct resource *res;
530 struct device *dev = &pdev->dev;
532 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
537 gi2c->se.wrapper = dev_get_drvdata(dev->parent);
538 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
539 gi2c->se.base = devm_ioremap_resource(dev, res);
540 if (IS_ERR(gi2c->se.base))
541 return PTR_ERR(gi2c->se.base);
543 gi2c->se.clk = devm_clk_get(dev, "se");
544 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
545 return PTR_ERR(gi2c->se.clk);
547 ret = device_property_read_u32(dev, "clock-frequency",
548 &gi2c->clk_freq_out);
550 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
551 gi2c->clk_freq_out = KHZ(100);
554 if (has_acpi_companion(dev))
555 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
557 gi2c->irq = platform_get_irq(pdev, 0);
561 ret = geni_i2c_clk_map_idx(gi2c);
563 dev_err(dev, "Invalid clk frequency %d Hz: %d\n",
564 gi2c->clk_freq_out, ret);
568 gi2c->adap.algo = &geni_i2c_algo;
569 init_completion(&gi2c->done);
570 spin_lock_init(&gi2c->lock);
571 platform_set_drvdata(pdev, gi2c);
572 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0,
573 dev_name(dev), gi2c);
575 dev_err(dev, "Request_irq failed:%d: err:%d\n",
579 /* Disable the interrupt so that the system can enter low-power mode */
580 disable_irq(gi2c->irq);
581 i2c_set_adapdata(&gi2c->adap, gi2c);
582 gi2c->adap.dev.parent = dev;
583 gi2c->adap.dev.of_node = dev->of_node;
584 strlcpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
586 ret = geni_icc_get(&gi2c->se, "qup-memory");
590 * Set the bus quota for core and cpu to a reasonable value for
592 * Set quota for DDR based on bus speed.
594 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
595 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
596 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
598 ret = geni_icc_set_bw(&gi2c->se);
602 ret = geni_se_resources_on(&gi2c->se);
604 dev_err(dev, "Error turning on resources %d\n", ret);
607 proto = geni_se_read_proto(&gi2c->se);
608 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
609 if (proto != GENI_SE_I2C) {
610 dev_err(dev, "Invalid proto %d\n", proto);
611 geni_se_resources_off(&gi2c->se);
614 gi2c->tx_wm = tx_depth - 1;
615 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
616 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE, PACKING_BYTES_PW,
618 ret = geni_se_resources_off(&gi2c->se);
620 dev_err(dev, "Error turning off resources %d\n", ret);
624 ret = geni_icc_disable(&gi2c->se);
628 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
631 pm_runtime_set_suspended(gi2c->se.dev);
632 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
633 pm_runtime_use_autosuspend(gi2c->se.dev);
634 pm_runtime_enable(gi2c->se.dev);
636 ret = i2c_add_adapter(&gi2c->adap);
638 dev_err(dev, "Error adding i2c adapter %d\n", ret);
639 pm_runtime_disable(gi2c->se.dev);
643 dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
648 static int geni_i2c_remove(struct platform_device *pdev)
650 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
652 i2c_del_adapter(&gi2c->adap);
653 pm_runtime_disable(gi2c->se.dev);
657 static void geni_i2c_shutdown(struct platform_device *pdev)
659 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
661 /* Make client i2c transfers start failing */
662 i2c_mark_adapter_suspended(&gi2c->adap);
665 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
668 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
670 disable_irq(gi2c->irq);
671 ret = geni_se_resources_off(&gi2c->se);
673 enable_irq(gi2c->irq);
680 return geni_icc_disable(&gi2c->se);
683 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
686 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
688 ret = geni_icc_enable(&gi2c->se);
692 ret = geni_se_resources_on(&gi2c->se);
696 enable_irq(gi2c->irq);
701 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
703 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
705 i2c_mark_adapter_suspended(&gi2c->adap);
707 if (!gi2c->suspended) {
708 geni_i2c_runtime_suspend(dev);
709 pm_runtime_disable(dev);
710 pm_runtime_set_suspended(dev);
711 pm_runtime_enable(dev);
716 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
718 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
720 i2c_mark_adapter_resumed(&gi2c->adap);
724 static const struct dev_pm_ops geni_i2c_pm_ops = {
725 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
726 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
730 static const struct of_device_id geni_i2c_dt_match[] = {
731 { .compatible = "qcom,geni-i2c" },
734 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
736 static struct platform_driver geni_i2c_driver = {
737 .probe = geni_i2c_probe,
738 .remove = geni_i2c_remove,
739 .shutdown = geni_i2c_shutdown,
742 .pm = &geni_i2c_pm_ops,
743 .of_match_table = geni_i2c_dt_match,
744 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
748 module_platform_driver(geni_i2c_driver);
750 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
751 MODULE_LICENSE("GPL v2");