1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
4 #include <linux/acpi.h>
6 #include <linux/dmaengine.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/dma/qcom-gpi-dma.h>
10 #include <linux/i2c.h>
11 #include <linux/interrupt.h>
13 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/soc/qcom/geni-se.h>
18 #include <linux/spinlock.h>
20 #define SE_I2C_TX_TRANS_LEN 0x26c
21 #define SE_I2C_RX_TRANS_LEN 0x270
22 #define SE_I2C_SCL_COUNTERS 0x278
24 #define SE_I2C_ERR (M_CMD_OVERRUN_EN | M_ILLEGAL_CMD_EN | M_CMD_FAILURE_EN |\
25 M_GP_IRQ_1_EN | M_GP_IRQ_3_EN | M_GP_IRQ_4_EN)
26 #define SE_I2C_ABORT BIT(1)
28 /* M_CMD OP codes for I2C */
31 #define I2C_WRITE_READ 0x3
32 #define I2C_ADDR_ONLY 0x4
33 #define I2C_BUS_CLEAR 0x6
34 #define I2C_STOP_ON_BUS 0x7
35 /* M_CMD params for I2C */
36 #define PRE_CMD_DELAY BIT(0)
37 #define TIMESTAMP_BEFORE BIT(1)
38 #define STOP_STRETCH BIT(2)
39 #define TIMESTAMP_AFTER BIT(3)
40 #define POST_COMMAND_DELAY BIT(4)
41 #define IGNORE_ADD_NACK BIT(6)
42 #define READ_FINISHED_WITH_ACK BIT(7)
43 #define BYPASS_ADDR_PHASE BIT(8)
44 #define SLV_ADDR_MSK GENMASK(15, 9)
45 #define SLV_ADDR_SHFT 9
46 /* I2C SCL COUNTER fields */
47 #define HIGH_COUNTER_MSK GENMASK(29, 20)
48 #define HIGH_COUNTER_SHFT 20
49 #define LOW_COUNTER_MSK GENMASK(19, 10)
50 #define LOW_COUNTER_SHFT 10
51 #define CYCLE_COUNTER_MSK GENMASK(9, 0)
53 #define I2C_PACK_TX BIT(0)
54 #define I2C_PACK_RX BIT(1)
56 enum geni_i2c_err_code {
69 #define DM_I2C_CB_ERR ((BIT(NACK) | BIT(BUS_PROTO) | BIT(ARB_LOST)) \
72 #define I2C_AUTO_SUSPEND_DELAY 250
73 #define KHZ(freq) (1000 * freq)
74 #define PACKING_BYTES_PW 4
76 #define ABORT_TIMEOUT HZ
77 #define XFER_TIMEOUT HZ
78 #define RST_TIMEOUT HZ
85 struct i2c_adapter adap;
86 struct completion done;
93 const struct geni_i2c_clk_fld *clk_fld;
98 struct dma_chan *tx_c;
99 struct dma_chan *rx_c;
104 struct geni_i2c_desc {
108 unsigned int tx_fifo_depth;
111 struct geni_i2c_err_log {
116 static const struct geni_i2c_err_log gi2c_log[] = {
117 [GP_IRQ0] = {-EIO, "Unknown I2C err GP_IRQ0"},
118 [NACK] = {-ENXIO, "NACK: slv unresponsive, check its power/reset-ln"},
119 [GP_IRQ2] = {-EIO, "Unknown I2C err GP IRQ2"},
120 [BUS_PROTO] = {-EPROTO, "Bus proto err, noisy/unexpected start/stop"},
121 [ARB_LOST] = {-EAGAIN, "Bus arbitration lost, clock line undriveable"},
122 [GP_IRQ5] = {-EIO, "Unknown I2C err GP IRQ5"},
123 [GENI_OVERRUN] = {-EIO, "Cmd overrun, check GENI cmd-state machine"},
124 [GENI_ILLEGAL_CMD] = {-EIO, "Illegal cmd, check GENI cmd-state machine"},
125 [GENI_ABORT_DONE] = {-ETIMEDOUT, "Abort after timeout successful"},
126 [GENI_TIMEOUT] = {-ETIMEDOUT, "I2C TXN timed out"},
129 struct geni_i2c_clk_fld {
138 * Hardware uses the underlying formula to calculate time periods of
139 * SCL clock cycle. Firmware uses some additional cycles excluded from the
140 * below formula and it is confirmed that the time periods are within
141 * specification limits.
143 * time of high period of SCL: t_high = (t_high_cnt * clk_div) / source_clock
144 * time of low period of SCL: t_low = (t_low_cnt * clk_div) / source_clock
145 * time of full period of SCL: t_cycle = (t_cycle_cnt * clk_div) / source_clock
146 * clk_freq_out = t / t_cycle
147 * source_clock = 19.2 MHz
149 static const struct geni_i2c_clk_fld geni_i2c_clk_map[] = {
150 {KHZ(100), 7, 10, 11, 26},
151 {KHZ(400), 2, 5, 12, 24},
152 {KHZ(1000), 1, 3, 9, 18},
155 static int geni_i2c_clk_map_idx(struct geni_i2c_dev *gi2c)
158 const struct geni_i2c_clk_fld *itr = geni_i2c_clk_map;
160 for (i = 0; i < ARRAY_SIZE(geni_i2c_clk_map); i++, itr++) {
161 if (itr->clk_freq_out == gi2c->clk_freq_out) {
169 static void qcom_geni_i2c_conf(struct geni_i2c_dev *gi2c)
171 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
174 writel_relaxed(0, gi2c->se.base + SE_GENI_CLK_SEL);
176 val = (itr->clk_div << CLK_DIV_SHFT) | SER_CLK_EN;
177 writel_relaxed(val, gi2c->se.base + GENI_SER_M_CLK_CFG);
179 val = itr->t_high_cnt << HIGH_COUNTER_SHFT;
180 val |= itr->t_low_cnt << LOW_COUNTER_SHFT;
181 val |= itr->t_cycle_cnt;
182 writel_relaxed(val, gi2c->se.base + SE_I2C_SCL_COUNTERS);
185 static void geni_i2c_err_misc(struct geni_i2c_dev *gi2c)
187 u32 m_cmd = readl_relaxed(gi2c->se.base + SE_GENI_M_CMD0);
188 u32 m_stat = readl_relaxed(gi2c->se.base + SE_GENI_M_IRQ_STATUS);
189 u32 geni_s = readl_relaxed(gi2c->se.base + SE_GENI_STATUS);
190 u32 geni_ios = readl_relaxed(gi2c->se.base + SE_GENI_IOS);
191 u32 dma = readl_relaxed(gi2c->se.base + SE_GENI_DMA_MODE_EN);
195 rx_st = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
196 tx_st = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
198 rx_st = readl_relaxed(gi2c->se.base + SE_GENI_RX_FIFO_STATUS);
199 tx_st = readl_relaxed(gi2c->se.base + SE_GENI_TX_FIFO_STATUS);
201 dev_dbg(gi2c->se.dev, "DMA:%d tx_stat:0x%x, rx_stat:0x%x, irq-stat:0x%x\n",
202 dma, tx_st, rx_st, m_stat);
203 dev_dbg(gi2c->se.dev, "m_cmd:0x%x, geni_status:0x%x, geni_ios:0x%x\n",
204 m_cmd, geni_s, geni_ios);
207 static void geni_i2c_err(struct geni_i2c_dev *gi2c, int err)
210 gi2c->err = gi2c_log[err].err;
212 dev_dbg(gi2c->se.dev, "len:%d, slv-addr:0x%x, RD/WR:%d\n",
213 gi2c->cur->len, gi2c->cur->addr, gi2c->cur->flags);
216 case GENI_ABORT_DONE:
217 gi2c->abort_done = true;
221 dev_dbg(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
224 dev_err(gi2c->se.dev, "%s\n", gi2c_log[err].msg);
225 geni_i2c_err_misc(gi2c);
230 static irqreturn_t geni_i2c_irq(int irq, void *dev)
232 struct geni_i2c_dev *gi2c = dev;
233 void __iomem *base = gi2c->se.base;
243 spin_lock(&gi2c->lock);
244 m_stat = readl_relaxed(base + SE_GENI_M_IRQ_STATUS);
245 rx_st = readl_relaxed(base + SE_GENI_RX_FIFO_STATUS);
246 dm_tx_st = readl_relaxed(base + SE_DMA_TX_IRQ_STAT);
247 dm_rx_st = readl_relaxed(base + SE_DMA_RX_IRQ_STAT);
248 dma = readl_relaxed(base + SE_GENI_DMA_MODE_EN);
252 m_stat & (M_CMD_FAILURE_EN | M_CMD_ABORT_EN) ||
253 dm_rx_st & (DM_I2C_CB_ERR)) {
254 if (m_stat & M_GP_IRQ_1_EN)
255 geni_i2c_err(gi2c, NACK);
256 if (m_stat & M_GP_IRQ_3_EN)
257 geni_i2c_err(gi2c, BUS_PROTO);
258 if (m_stat & M_GP_IRQ_4_EN)
259 geni_i2c_err(gi2c, ARB_LOST);
260 if (m_stat & M_CMD_OVERRUN_EN)
261 geni_i2c_err(gi2c, GENI_OVERRUN);
262 if (m_stat & M_ILLEGAL_CMD_EN)
263 geni_i2c_err(gi2c, GENI_ILLEGAL_CMD);
264 if (m_stat & M_CMD_ABORT_EN)
265 geni_i2c_err(gi2c, GENI_ABORT_DONE);
266 if (m_stat & M_GP_IRQ_0_EN)
267 geni_i2c_err(gi2c, GP_IRQ0);
269 /* Disable the TX Watermark interrupt to stop TX */
271 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
273 dev_dbg(gi2c->se.dev, "i2c dma tx:0x%x, dma rx:0x%x\n",
275 } else if (cur->flags & I2C_M_RD &&
276 m_stat & (M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN)) {
277 u32 rxcnt = rx_st & RX_FIFO_WC_MSK;
279 for (j = 0; j < rxcnt; j++) {
281 val = readl_relaxed(base + SE_GENI_RX_FIFOn);
282 while (gi2c->cur_rd < cur->len && p < sizeof(val)) {
283 cur->buf[gi2c->cur_rd++] = val & 0xff;
287 if (gi2c->cur_rd == cur->len)
290 } else if (!(cur->flags & I2C_M_RD) &&
291 m_stat & M_TX_FIFO_WATERMARK_EN) {
292 for (j = 0; j < gi2c->tx_wm; j++) {
297 while (gi2c->cur_wr < cur->len && p < sizeof(val)) {
298 temp = cur->buf[gi2c->cur_wr++];
299 val |= temp << (p * 8);
302 writel_relaxed(val, base + SE_GENI_TX_FIFOn);
303 /* TX Complete, Disable the TX Watermark interrupt */
304 if (gi2c->cur_wr == cur->len) {
305 writel_relaxed(0, base + SE_GENI_TX_WATERMARK_REG);
312 writel_relaxed(m_stat, base + SE_GENI_M_IRQ_CLEAR);
315 writel_relaxed(dm_tx_st, base + SE_DMA_TX_IRQ_CLR);
317 writel_relaxed(dm_rx_st, base + SE_DMA_RX_IRQ_CLR);
319 /* if this is err with done-bit not set, handle that through timeout. */
320 if (m_stat & M_CMD_DONE_EN || m_stat & M_CMD_ABORT_EN ||
321 dm_tx_st & TX_DMA_DONE || dm_tx_st & TX_RESET_DONE ||
322 dm_rx_st & RX_DMA_DONE || dm_rx_st & RX_RESET_DONE)
323 complete(&gi2c->done);
325 spin_unlock(&gi2c->lock);
330 static void geni_i2c_abort_xfer(struct geni_i2c_dev *gi2c)
332 unsigned long time_left = ABORT_TIMEOUT;
335 spin_lock_irqsave(&gi2c->lock, flags);
336 geni_i2c_err(gi2c, GENI_TIMEOUT);
338 gi2c->abort_done = false;
339 geni_se_abort_m_cmd(&gi2c->se);
340 spin_unlock_irqrestore(&gi2c->lock, flags);
343 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
344 } while (!gi2c->abort_done && time_left);
347 dev_err(gi2c->se.dev, "Timeout abort_m_cmd\n");
350 static void geni_i2c_rx_fsm_rst(struct geni_i2c_dev *gi2c)
353 unsigned long time_left = RST_TIMEOUT;
355 writel_relaxed(1, gi2c->se.base + SE_DMA_RX_FSM_RST);
357 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
358 val = readl_relaxed(gi2c->se.base + SE_DMA_RX_IRQ_STAT);
359 } while (!(val & RX_RESET_DONE) && time_left);
361 if (!(val & RX_RESET_DONE))
362 dev_err(gi2c->se.dev, "Timeout resetting RX_FSM\n");
365 static void geni_i2c_tx_fsm_rst(struct geni_i2c_dev *gi2c)
368 unsigned long time_left = RST_TIMEOUT;
370 writel_relaxed(1, gi2c->se.base + SE_DMA_TX_FSM_RST);
372 time_left = wait_for_completion_timeout(&gi2c->done, time_left);
373 val = readl_relaxed(gi2c->se.base + SE_DMA_TX_IRQ_STAT);
374 } while (!(val & TX_RESET_DONE) && time_left);
376 if (!(val & TX_RESET_DONE))
377 dev_err(gi2c->se.dev, "Timeout resetting TX_FSM\n");
380 static void geni_i2c_rx_msg_cleanup(struct geni_i2c_dev *gi2c,
386 geni_i2c_rx_fsm_rst(gi2c);
387 geni_se_rx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
388 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
392 static void geni_i2c_tx_msg_cleanup(struct geni_i2c_dev *gi2c,
398 geni_i2c_tx_fsm_rst(gi2c);
399 geni_se_tx_dma_unprep(&gi2c->se, gi2c->dma_addr, gi2c->xfer_len);
400 i2c_put_dma_safe_msg_buf(gi2c->dma_buf, cur, !gi2c->err);
404 static int geni_i2c_rx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
407 dma_addr_t rx_dma = 0;
408 unsigned long time_left;
410 struct geni_se *se = &gi2c->se;
411 size_t len = msg->len;
414 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
416 geni_se_select_mode(se, GENI_SE_DMA);
418 geni_se_select_mode(se, GENI_SE_FIFO);
420 writel_relaxed(len, se->base + SE_I2C_RX_TRANS_LEN);
421 geni_se_setup_m_cmd(se, I2C_READ, m_param);
423 if (dma_buf && geni_se_rx_dma_prep(se, dma_buf, len, &rx_dma)) {
424 geni_se_select_mode(se, GENI_SE_FIFO);
425 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
428 gi2c->xfer_len = len;
429 gi2c->dma_addr = rx_dma;
430 gi2c->dma_buf = dma_buf;
434 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
436 geni_i2c_abort_xfer(gi2c);
438 geni_i2c_rx_msg_cleanup(gi2c, cur);
443 static int geni_i2c_tx_one_msg(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
446 dma_addr_t tx_dma = 0;
447 unsigned long time_left;
449 struct geni_se *se = &gi2c->se;
450 size_t len = msg->len;
453 dma_buf = i2c_get_dma_safe_msg_buf(msg, 32);
455 geni_se_select_mode(se, GENI_SE_DMA);
457 geni_se_select_mode(se, GENI_SE_FIFO);
459 writel_relaxed(len, se->base + SE_I2C_TX_TRANS_LEN);
460 geni_se_setup_m_cmd(se, I2C_WRITE, m_param);
462 if (dma_buf && geni_se_tx_dma_prep(se, dma_buf, len, &tx_dma)) {
463 geni_se_select_mode(se, GENI_SE_FIFO);
464 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
467 gi2c->xfer_len = len;
468 gi2c->dma_addr = tx_dma;
469 gi2c->dma_buf = dma_buf;
472 if (!dma_buf) /* Get FIFO IRQ */
473 writel_relaxed(1, se->base + SE_GENI_TX_WATERMARK_REG);
476 time_left = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
478 geni_i2c_abort_xfer(gi2c);
480 geni_i2c_tx_msg_cleanup(gi2c, cur);
485 static void i2c_gpi_cb_result(void *cb, const struct dmaengine_result *result)
487 struct geni_i2c_dev *gi2c = cb;
489 if (result->result != DMA_TRANS_NOERROR) {
490 dev_err(gi2c->se.dev, "DMA txn failed:%d\n", result->result);
492 } else if (result->residue) {
493 dev_dbg(gi2c->se.dev, "DMA xfer has pending: %d\n", result->residue);
496 complete(&gi2c->done);
499 static void geni_i2c_gpi_unmap(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
500 void *tx_buf, dma_addr_t tx_addr,
501 void *rx_buf, dma_addr_t rx_addr)
504 dma_unmap_single(gi2c->se.dev->parent, tx_addr, msg->len, DMA_TO_DEVICE);
505 i2c_put_dma_safe_msg_buf(tx_buf, msg, !gi2c->err);
509 dma_unmap_single(gi2c->se.dev->parent, rx_addr, msg->len, DMA_FROM_DEVICE);
510 i2c_put_dma_safe_msg_buf(rx_buf, msg, !gi2c->err);
514 static int geni_i2c_gpi(struct geni_i2c_dev *gi2c, struct i2c_msg *msg,
515 struct dma_slave_config *config, dma_addr_t *dma_addr_p,
516 void **buf, unsigned int op, struct dma_chan *dma_chan)
518 struct gpi_i2c_config *peripheral;
522 enum dma_data_direction map_dirn;
523 enum dma_transfer_direction dma_dirn;
524 struct dma_async_tx_descriptor *desc;
527 peripheral = config->peripheral_config;
529 dma_buf = i2c_get_dma_safe_msg_buf(msg, 1);
534 map_dirn = DMA_TO_DEVICE;
536 map_dirn = DMA_FROM_DEVICE;
538 addr = dma_map_single(gi2c->se.dev->parent, dma_buf, msg->len, map_dirn);
539 if (dma_mapping_error(gi2c->se.dev->parent, addr)) {
540 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
544 /* set the length as message for rx txn */
545 peripheral->rx_len = msg->len;
548 ret = dmaengine_slave_config(dma_chan, config);
550 dev_err(gi2c->se.dev, "dma config error: %d for op:%d\n", ret, op);
554 peripheral->set_config = 0;
555 peripheral->multi_msg = true;
556 flags = DMA_PREP_INTERRUPT | DMA_CTRL_ACK;
559 dma_dirn = DMA_MEM_TO_DEV;
561 dma_dirn = DMA_DEV_TO_MEM;
563 desc = dmaengine_prep_slave_single(dma_chan, addr, msg->len, dma_dirn, flags);
565 dev_err(gi2c->se.dev, "prep_slave_sg failed\n");
570 desc->callback_result = i2c_gpi_cb_result;
571 desc->callback_param = gi2c;
573 dmaengine_submit(desc);
580 dma_unmap_single(gi2c->se.dev->parent, addr, msg->len, map_dirn);
581 i2c_put_dma_safe_msg_buf(dma_buf, msg, false);
585 static int geni_i2c_gpi_xfer(struct geni_i2c_dev *gi2c, struct i2c_msg msgs[], int num)
587 struct dma_slave_config config = {};
588 struct gpi_i2c_config peripheral = {};
589 int i, ret = 0, timeout;
590 dma_addr_t tx_addr, rx_addr;
591 void *tx_buf = NULL, *rx_buf = NULL;
592 const struct geni_i2c_clk_fld *itr = gi2c->clk_fld;
594 config.peripheral_config = &peripheral;
595 config.peripheral_size = sizeof(peripheral);
597 peripheral.pack_enable = I2C_PACK_TX | I2C_PACK_RX;
598 peripheral.cycle_count = itr->t_cycle_cnt;
599 peripheral.high_count = itr->t_high_cnt;
600 peripheral.low_count = itr->t_low_cnt;
601 peripheral.clk_div = itr->clk_div;
602 peripheral.set_config = 1;
603 peripheral.multi_msg = false;
605 for (i = 0; i < num; i++) {
606 gi2c->cur = &msgs[i];
608 dev_dbg(gi2c->se.dev, "msg[%d].len:%d\n", i, gi2c->cur->len);
610 peripheral.stretch = 0;
612 peripheral.stretch = 1;
614 peripheral.addr = msgs[i].addr;
616 ret = geni_i2c_gpi(gi2c, &msgs[i], &config,
617 &tx_addr, &tx_buf, I2C_WRITE, gi2c->tx_c);
621 if (msgs[i].flags & I2C_M_RD) {
622 ret = geni_i2c_gpi(gi2c, &msgs[i], &config,
623 &rx_addr, &rx_buf, I2C_READ, gi2c->rx_c);
627 dma_async_issue_pending(gi2c->rx_c);
630 dma_async_issue_pending(gi2c->tx_c);
632 timeout = wait_for_completion_timeout(&gi2c->done, XFER_TIMEOUT);
634 dev_err(gi2c->se.dev, "I2C timeout gpi flags:%d addr:0x%x\n",
635 gi2c->cur->flags, gi2c->cur->addr);
636 gi2c->err = -ETIMEDOUT;
644 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
650 dev_err(gi2c->se.dev, "GPI transfer failed: %d\n", ret);
651 dmaengine_terminate_sync(gi2c->rx_c);
652 dmaengine_terminate_sync(gi2c->tx_c);
653 geni_i2c_gpi_unmap(gi2c, &msgs[i], tx_buf, tx_addr, rx_buf, rx_addr);
657 static int geni_i2c_fifo_xfer(struct geni_i2c_dev *gi2c,
658 struct i2c_msg msgs[], int num)
662 for (i = 0; i < num; i++) {
663 u32 m_param = i < (num - 1) ? STOP_STRETCH : 0;
665 m_param |= ((msgs[i].addr << SLV_ADDR_SHFT) & SLV_ADDR_MSK);
667 gi2c->cur = &msgs[i];
668 if (msgs[i].flags & I2C_M_RD)
669 ret = geni_i2c_rx_one_msg(gi2c, &msgs[i], m_param);
671 ret = geni_i2c_tx_one_msg(gi2c, &msgs[i], m_param);
680 static int geni_i2c_xfer(struct i2c_adapter *adap,
681 struct i2c_msg msgs[],
684 struct geni_i2c_dev *gi2c = i2c_get_adapdata(adap);
688 reinit_completion(&gi2c->done);
689 ret = pm_runtime_get_sync(gi2c->se.dev);
691 dev_err(gi2c->se.dev, "error turning SE resources:%d\n", ret);
692 pm_runtime_put_noidle(gi2c->se.dev);
693 /* Set device in suspended since resume failed */
694 pm_runtime_set_suspended(gi2c->se.dev);
698 qcom_geni_i2c_conf(gi2c);
701 ret = geni_i2c_gpi_xfer(gi2c, msgs, num);
703 ret = geni_i2c_fifo_xfer(gi2c, msgs, num);
705 pm_runtime_mark_last_busy(gi2c->se.dev);
706 pm_runtime_put_autosuspend(gi2c->se.dev);
712 static u32 geni_i2c_func(struct i2c_adapter *adap)
714 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
717 static const struct i2c_algorithm geni_i2c_algo = {
718 .master_xfer = geni_i2c_xfer,
719 .functionality = geni_i2c_func,
723 static const struct acpi_device_id geni_i2c_acpi_match[] = {
728 MODULE_DEVICE_TABLE(acpi, geni_i2c_acpi_match);
731 static void release_gpi_dma(struct geni_i2c_dev *gi2c)
734 dma_release_channel(gi2c->rx_c);
737 dma_release_channel(gi2c->tx_c);
740 static int setup_gpi_dma(struct geni_i2c_dev *gi2c)
744 geni_se_select_mode(&gi2c->se, GENI_GPI_DMA);
745 gi2c->tx_c = dma_request_chan(gi2c->se.dev, "tx");
746 if (IS_ERR(gi2c->tx_c)) {
747 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->tx_c),
748 "Failed to get tx DMA ch\n");
752 gi2c->rx_c = dma_request_chan(gi2c->se.dev, "rx");
753 if (IS_ERR(gi2c->rx_c)) {
754 ret = dev_err_probe(gi2c->se.dev, PTR_ERR(gi2c->rx_c),
755 "Failed to get rx DMA ch\n");
759 dev_dbg(gi2c->se.dev, "Grabbed GPI dma channels\n");
763 dma_release_channel(gi2c->tx_c);
768 static int geni_i2c_probe(struct platform_device *pdev)
770 struct geni_i2c_dev *gi2c;
771 u32 proto, tx_depth, fifo_disable;
773 struct device *dev = &pdev->dev;
774 const struct geni_i2c_desc *desc = NULL;
776 gi2c = devm_kzalloc(dev, sizeof(*gi2c), GFP_KERNEL);
781 gi2c->se.wrapper = dev_get_drvdata(dev->parent);
782 gi2c->se.base = devm_platform_ioremap_resource(pdev, 0);
783 if (IS_ERR(gi2c->se.base))
784 return PTR_ERR(gi2c->se.base);
786 desc = device_get_match_data(&pdev->dev);
788 if (desc && desc->has_core_clk) {
789 gi2c->core_clk = devm_clk_get(dev, "core");
790 if (IS_ERR(gi2c->core_clk))
791 return PTR_ERR(gi2c->core_clk);
794 gi2c->se.clk = devm_clk_get(dev, "se");
795 if (IS_ERR(gi2c->se.clk) && !has_acpi_companion(dev))
796 return PTR_ERR(gi2c->se.clk);
798 ret = device_property_read_u32(dev, "clock-frequency",
799 &gi2c->clk_freq_out);
801 dev_info(dev, "Bus frequency not specified, default to 100kHz.\n");
802 gi2c->clk_freq_out = KHZ(100);
805 if (has_acpi_companion(dev))
806 ACPI_COMPANION_SET(&gi2c->adap.dev, ACPI_COMPANION(dev));
808 gi2c->irq = platform_get_irq(pdev, 0);
812 ret = geni_i2c_clk_map_idx(gi2c);
814 dev_err(dev, "Invalid clk frequency %d Hz: %d\n",
815 gi2c->clk_freq_out, ret);
819 gi2c->adap.algo = &geni_i2c_algo;
820 init_completion(&gi2c->done);
821 spin_lock_init(&gi2c->lock);
822 platform_set_drvdata(pdev, gi2c);
823 ret = devm_request_irq(dev, gi2c->irq, geni_i2c_irq, 0,
824 dev_name(dev), gi2c);
826 dev_err(dev, "Request_irq failed:%d: err:%d\n",
830 /* Disable the interrupt so that the system can enter low-power mode */
831 disable_irq(gi2c->irq);
832 i2c_set_adapdata(&gi2c->adap, gi2c);
833 gi2c->adap.dev.parent = dev;
834 gi2c->adap.dev.of_node = dev->of_node;
835 strscpy(gi2c->adap.name, "Geni-I2C", sizeof(gi2c->adap.name));
837 ret = geni_icc_get(&gi2c->se, desc ? desc->icc_ddr : "qup-memory");
841 * Set the bus quota for core and cpu to a reasonable value for
843 * Set quota for DDR based on bus speed.
845 gi2c->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
846 gi2c->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
847 if (!desc || desc->icc_ddr)
848 gi2c->se.icc_paths[GENI_TO_DDR].avg_bw = Bps_to_icc(gi2c->clk_freq_out);
850 ret = geni_icc_set_bw(&gi2c->se);
854 ret = clk_prepare_enable(gi2c->core_clk);
858 ret = geni_se_resources_on(&gi2c->se);
860 dev_err(dev, "Error turning on resources %d\n", ret);
861 clk_disable_unprepare(gi2c->core_clk);
864 proto = geni_se_read_proto(&gi2c->se);
865 if (proto != GENI_SE_I2C) {
866 dev_err(dev, "Invalid proto %d\n", proto);
867 geni_se_resources_off(&gi2c->se);
868 clk_disable_unprepare(gi2c->core_clk);
872 if (desc && desc->no_dma_support)
873 fifo_disable = false;
875 fifo_disable = readl_relaxed(gi2c->se.base + GENI_IF_DISABLE_RO) & FIFO_IF_DISABLE;
878 /* FIFO is disabled, so we can only use GPI DMA */
879 gi2c->gpi_mode = true;
880 ret = setup_gpi_dma(gi2c);
882 geni_se_resources_off(&gi2c->se);
883 clk_disable_unprepare(gi2c->core_clk);
884 return dev_err_probe(dev, ret, "Failed to setup GPI DMA mode\n");
887 dev_dbg(dev, "Using GPI DMA mode for I2C\n");
889 gi2c->gpi_mode = false;
890 tx_depth = geni_se_get_tx_fifo_depth(&gi2c->se);
892 /* I2C Master Hub Serial Elements doesn't have the HW_PARAM_0 register */
893 if (!tx_depth && desc)
894 tx_depth = desc->tx_fifo_depth;
897 dev_err(dev, "Invalid TX FIFO depth\n");
898 geni_se_resources_off(&gi2c->se);
899 clk_disable_unprepare(gi2c->core_clk);
903 gi2c->tx_wm = tx_depth - 1;
904 geni_se_init(&gi2c->se, gi2c->tx_wm, tx_depth);
905 geni_se_config_packing(&gi2c->se, BITS_PER_BYTE,
906 PACKING_BYTES_PW, true, true, true);
908 dev_dbg(dev, "i2c fifo/se-dma mode. fifo depth:%d\n", tx_depth);
911 clk_disable_unprepare(gi2c->core_clk);
912 ret = geni_se_resources_off(&gi2c->se);
914 dev_err(dev, "Error turning off resources %d\n", ret);
918 ret = geni_icc_disable(&gi2c->se);
923 pm_runtime_set_suspended(gi2c->se.dev);
924 pm_runtime_set_autosuspend_delay(gi2c->se.dev, I2C_AUTO_SUSPEND_DELAY);
925 pm_runtime_use_autosuspend(gi2c->se.dev);
926 pm_runtime_enable(gi2c->se.dev);
928 ret = i2c_add_adapter(&gi2c->adap);
930 dev_err(dev, "Error adding i2c adapter %d\n", ret);
931 pm_runtime_disable(gi2c->se.dev);
935 dev_dbg(dev, "Geni-I2C adaptor successfully added\n");
940 release_gpi_dma(gi2c);
944 static void geni_i2c_remove(struct platform_device *pdev)
946 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
948 i2c_del_adapter(&gi2c->adap);
949 release_gpi_dma(gi2c);
950 pm_runtime_disable(gi2c->se.dev);
953 static void geni_i2c_shutdown(struct platform_device *pdev)
955 struct geni_i2c_dev *gi2c = platform_get_drvdata(pdev);
957 /* Make client i2c transfers start failing */
958 i2c_mark_adapter_suspended(&gi2c->adap);
961 static int __maybe_unused geni_i2c_runtime_suspend(struct device *dev)
964 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
966 disable_irq(gi2c->irq);
967 ret = geni_se_resources_off(&gi2c->se);
969 enable_irq(gi2c->irq);
976 clk_disable_unprepare(gi2c->core_clk);
978 return geni_icc_disable(&gi2c->se);
981 static int __maybe_unused geni_i2c_runtime_resume(struct device *dev)
984 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
986 ret = geni_icc_enable(&gi2c->se);
990 ret = clk_prepare_enable(gi2c->core_clk);
994 ret = geni_se_resources_on(&gi2c->se);
998 enable_irq(gi2c->irq);
1003 static int __maybe_unused geni_i2c_suspend_noirq(struct device *dev)
1005 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1007 i2c_mark_adapter_suspended(&gi2c->adap);
1009 if (!gi2c->suspended) {
1010 geni_i2c_runtime_suspend(dev);
1011 pm_runtime_disable(dev);
1012 pm_runtime_set_suspended(dev);
1013 pm_runtime_enable(dev);
1018 static int __maybe_unused geni_i2c_resume_noirq(struct device *dev)
1020 struct geni_i2c_dev *gi2c = dev_get_drvdata(dev);
1022 i2c_mark_adapter_resumed(&gi2c->adap);
1026 static const struct dev_pm_ops geni_i2c_pm_ops = {
1027 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(geni_i2c_suspend_noirq, geni_i2c_resume_noirq)
1028 SET_RUNTIME_PM_OPS(geni_i2c_runtime_suspend, geni_i2c_runtime_resume,
1032 static const struct geni_i2c_desc i2c_master_hub = {
1033 .has_core_clk = true,
1035 .no_dma_support = true,
1036 .tx_fifo_depth = 16,
1039 static const struct of_device_id geni_i2c_dt_match[] = {
1040 { .compatible = "qcom,geni-i2c" },
1041 { .compatible = "qcom,geni-i2c-master-hub", .data = &i2c_master_hub },
1044 MODULE_DEVICE_TABLE(of, geni_i2c_dt_match);
1046 static struct platform_driver geni_i2c_driver = {
1047 .probe = geni_i2c_probe,
1048 .remove_new = geni_i2c_remove,
1049 .shutdown = geni_i2c_shutdown,
1052 .pm = &geni_i2c_pm_ops,
1053 .of_match_table = geni_i2c_dt_match,
1054 .acpi_match_table = ACPI_PTR(geni_i2c_acpi_match),
1058 module_platform_driver(geni_i2c_driver);
1060 MODULE_DESCRIPTION("I2C Controller Driver for GENI based QUP cores");
1061 MODULE_LICENSE("GPL v2");